CN1174490C - Nitride read-only memory unit structure with double top oxide layer and its manufacture - Google Patents
Nitride read-only memory unit structure with double top oxide layer and its manufacture Download PDFInfo
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- CN1174490C CN1174490C CNB011206888A CN01120688A CN1174490C CN 1174490 C CN1174490 C CN 1174490C CN B011206888 A CNB011206888 A CN B011206888A CN 01120688 A CN01120688 A CN 01120688A CN 1174490 C CN1174490 C CN 1174490C
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- nitride
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- 230000015654 memory Effects 0.000 title claims abstract description 53
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 31
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 37
- 150000002500 ions Chemical class 0.000 claims description 31
- 238000009792 diffusion process Methods 0.000 claims description 26
- 239000004065 semiconductor Substances 0.000 claims description 18
- 239000000377 silicon dioxide Substances 0.000 claims description 18
- 235000012239 silicon dioxide Nutrition 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 80
- 239000011241 protective layer Substances 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
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Abstract
The present invention relates to a nitride read-only memory cell structure with a double top oxide layer and a manufacturing method thereof. An oxide layer is deposited on an ONO structure as a floating gate in a nitride read-only memory cell by a high-temperature chemical vapor deposition method and is used as a protective layer of a silicon nitride layer in the ONO structure. Charges are effectively trapped in the silicon nitride layer, the charges in the silicon nitride layer are prevented from running off from an interface between a polycrystalline silicon layer and the silicon nitride, and thus, the reliability of the memory is strengthened.
Description
Technical field
The present invention relates to nitride ROM (NROM), particularly about a kind of memory cell structure and manufacture method thereof of avoiding the nitride ROM of loss of charge, can erase and programmable ROM (Erasable Programmable ROM to increase, EPROM), can electricity remove and programmable ROM (Electrically Erasable Programmable ROM, EEPROM), the reliability of flash memory (Flash), embedded flash memory read-only memorys such as (Embedded Flash).
Background technology
In today of computing information product prosperity, memory is being played the part of very important role.When the function of computer microprocessor is more and more stronger, program and computing that software carried out are more and more huger, and relatively, the demand of memory is just constantly promoting., processing speed big for the manufacturing capacity is fast, good reliability and cheap again memory, to satisfy the trend of this demand, makes the technology and the processing procedure of memory, has become semiconductor science and technology and has continued toward the actuating force of higher integration challenge.
Consult Fig. 1, to make nitride read-only memory unit (NROM cell) is example, semiconductor substrate 10 at first is provided, and deposit layer of silicon dioxide layer 22 thereon in regular turn, one deck silicon nitride layer 24 is used as the floating grid material, and layer of silicon dioxide layer 26, these three layers is so-called oxide-nitride-oxide skin(coating) (SiO
2-Si
3N
4-SiO
2), be called for short the ONO layer;
Secondly, define this ONO layer, obtain most ONO floating grid structures 20 with the photoengraving lithography, and the zone between these most ONO floating grid structures 20, carry out N
+Ion is implanted, and through suitable thermal diffusion, and form buried regions ions diffusion zone (Buried Diffusion BD) 30;
Then, deposit one deck buried regions oxide layer (BD Oxide) 32 again in 30 tops, buried regions ions diffusion zone.
Consult shown in Figure 2ly, on ONO floating grid structure 2O and buried regions oxide layer 32, deposit a polysilicon layer 40 in regular turn, and utilize the photoengraving lithography to define the structure of the polysilicon control grid utmost point, to form most bar character lines (Word Line).Its major defect is:
Silicon nitride layer 24 in post-depositional polysilicon layer 40 and the ONO floating grid structure 20 has formed a contact-making surface, this contact-making surface just as passage exists, make after the NROM memory cell is carried out sequencing and write data, the electric charge that sinks in (trap) floating grid has part through contact-making surface loss thus, cause the data hold capacity of this memory limited, and influence the reliability of memory cell.
Therefore, the inventor proposes a kind of structure and manufacture method thereof of nitride ROM at above-mentioned defective, to avoid charge loss, improves the data hold capacity of memory.
Summary of the invention
Main purpose of the present invention provides a kind of nitride read-only memory unit structure and manufacture method thereof with double top oxide layer; by around silicon nitride layer, forming a diaphragm; to stop the situation that silicon nitride layer and polysilicon layer form passage fully; overcome the drawback of prior art; reach and avoid charge loss, improve the purpose of the data hold capacity of memory.
Second purpose of the present invention provides a kind of nitride read-only memory unit structure and manufacture method thereof with double top oxide layer, reaches the purpose of the nitride read-only memory unit with preferable data hold capacity.
The 3rd purpose of the present invention provides a kind of nitride read-only memory unit structure and manufacture method thereof with double top oxide layer, reach electric charge is effectively caught in the silicon nitride layer that is trapped in the ONO structure, also can not increase the purpose of the extra heat budget of processing procedure (thermal budget) simultaneously.
The object of the present invention is achieved like this: a kind of nitride read-only memory unit structure with double top oxide layer, it is characterized in that: finish the structure that is provided with most oxide-nitride-oxides, with as floating grid at the semiconductor-based end of FEOL; The semiconductor-based end between the structure of this oxide-nitride-oxide, be provided with most buried regions ions diffusion zones; The top oxide layer is covered in the structure of this oxide-nitride-oxide and the surface in this buried regions ions diffusion zone; A most buried regions oxide layer are positioned on this buried regions ions diffusion zone; Linear this oxide layer top, top that is formed in of most bar polysilicon characters.
The structure of this oxide-nitride-oxide is from bottom to top piled up by silicon dioxide layer, silicon nitride layer and silicon dioxide layer in regular turn and is formed.The silicon dioxide layer via nitride of this bottom is handled, and forms the silicon dioxide layer of nitrogenize.This buried regions ions diffusion zone is a N type ion doped region.This top oxide layer is to utilize the high temperature chemical vapor deposition method to deposit to form.This top thickness of oxide layer is between 20-100 .
The present invention also provides a kind of manufacture method with nitride read-only memory unit structure of double top oxide layer, and it is characterized in that: it comprises the following steps:
(1) provides the semiconductor-based end of finishing FEOL;
(2) utilize the photoetching etch process, on this semiconductor-based end, form the structure of most oxide-nitride-oxides, with as floating grid;
(3) on the semiconductor-based end between the structure of this oxide-nitride-oxide, carry out ion and implant, to form most buried regions ions diffusion zones;
(4) deposition one top oxide layer is covered in the structure of this oxide-nitride-oxide and the surface in this buried regions ions diffusion zone;
(5) on this buried regions ions diffusion zone, be formed with the buried regions oxide layer;
(6) above this top oxide layer, be formed with most bar polysilicon character lines.
The present invention is in the ONO of nitride read-only memory unit superstructure in the high temperature chemical vapor deposition mode; many deposition one decks top oxide layer; make it fully cover the ONO structure; with top as the ONO structure; many deposition one decks top oxide layer makes it fully cover the ONO structure, with the protective layer as the ONO structure; prevent that the electric charge that sinks in the silicon nitride layer runs off from polysilicon and silicon nitride layer interface, thereby increased the reliability of memory.
Illustrate in detail below in conjunction with the preferred embodiment conjunction with figs..
Description of drawings
Fig. 1-Fig. 2 is the part-structure cutaway view of traditional fabrication nitride read-only memory unit.
Fig. 3 is the structural representation of nitride read-only memory unit of the present invention.
Fig. 4-Fig. 7 makes the organigram of each step of memory cell process for the present invention.
Embodiment
The present invention utilizes high temperature chemical vapor deposition mode (HTO) at the ONO of memory cell (Oxide-Nitride-Oxide); many deposition one oxide layers are as protective layer on the floating grid of oxide-nitride-oxide structure; run off from the contact-making surface between polysilicon and silicon nitride layer with the electric charge in the silicon nitride layer that prevents to become trapped in the ONO floating grid, and then increased the reliability of memory.
Figure 3 shows that the structural representation of nitride read-only memory unit of the present invention, at the semiconductor-based end 50 of finishing FEOL, the surface that is generally Silicon Wafer is provided with most ONO structures 60, with as floating grid (Floating Gate), this ONO structure 60 from bottom to top is one silica layer 62 in regular turn, silicon nitride layer 64 and silicon dioxide layer 66, and on the semiconductor-based end 50 between this ONO structure 60, be provided with most buried regions ions diffusion zones 70, and there is a top oxide layer 80 to be covered in the surface in this ONO structure 60 and buried regions ions diffusion zone 70, with protective layer, avoid electric charge to run off from silicon nitride layer 64 as this ONO structure 60;
Other has most buried regions oxide layers 72 to lay respectively on the buried regions ions diffusion zone 70, be formed with most bar polysilicon character lines (Polysilicon Word Line) 90 at last again in these top oxide layer 80 tops, with usefulness as the polysilicon control grid utmost point (Control Gate).
Fig. 4-Figure 7 shows that the present invention makes the schematic flow sheet of nitride read-only memory unit, this manufacture method comprises the following steps:
The semiconductor-based end 50 of finishing the memory cell FEOL, be provided, as shown in Figure 4, form ONO film 60 ' on surface, the semiconductor-based ends 50, promptly utilize chemical vapour deposition technique on the semiconductor-based end 50, to deposit one deck earlier through nitrogen treatment, the silicon dioxide layer 62 of thickness between 30-100 , this is the bottom oxide layer of ONO film 60 ';
Deposit the silicon nitride layer 64 that a layer thickness is 30-100 with CVD again in these silicon dioxide layer 62 tops afterwards, this is the intermediate layer of ONO film, with as floating grid, in order to store charge, then form the silicon oxide layer 66 of a layer thickness between 30-100 in reusable heat oxidizing process above this silicon nitride layer 64, this is the top oxide layer of ONO film 60 '.
Consult Fig. 5, then, carry out photoetching and etch process, utilize gold-tinted development etching technique to go up the photoresist layer (not shown) that forms a patterning earlier in ONO film 60 ', and be mask with this photoresist layer, use existing etching technique, this ONO film 60 ' is carried out etching, forming most ONO structures 60, and on the semiconductor-based end 50 between this ONO structure 60, carry out N as the usefulness of floating grid
+Ion is implanted, to form most buried regions ions diffusion zones (BD) 70.
Consult shown in Figure 6, after above-mentioned ion implantation is finished, comprehensively in high temperature chemical vapor deposition mode (CVD) in the about top oxide layer 80 between 30-100 of ONO structure 60 and buried regions ions diffusion zone 70 surface depositions, one layer thickness, it is the second top oxide layer of ONO structure 60, makes it fully cover ONO structure and buried regions ions diffusion zone 70.
Consult shown in Figure 7, wet oxidation process is carried out in buried regions ions diffusion zone 70, to form buried regions oxide layer (BD Oxide) 72, and deposition one polysilicon layer 90 and tungsten silicide layer 92 on top oxide layer 80 in regular turn, utilize the photoengraving lithography to define the structure of polysilicon bit line then, with usefulness as the control grid.After finishing the making of control grid, follow-up processing procedure then continues to implement according to the standard fabrication steps of General N ROM memory cell.It is a prior art, so do not repeat.
Nitride read-only memory unit of the present invention is in ONO structure 60 surface coverage one top oxide layer 80; form a diaphragm around making its silicon nitride layer 64 in ONO structure 60; the data preservation losing issue that is subjected to stop the situation that silicon nitride layer 64 and polysilicon layer 90 form passages fully, to make effectively to overcome conventional memory cell.Therefore, the present invention can effectively catch electric charge in the silicon nitride layer that is trapped in the nitride read-only memory unit ONO structure, not only can avoid store charge to run off, more make memory cell have preferable data hold capacity, preserve losing issue to solve traditional serious data that nitride read-only memory unit was subjected to, simultaneously also can not increase the extra heat budget of processing procedure (hermalbudget), and then improve the reliability of whole nitride ROM.
The above only is explanation technological thought of the present invention and characteristics; its purpose makes the personage who has the knack of this skill can understand content of the present invention and is implementing according to this; all equalizations of doing according to disclosed spirit change and modify, and all should be encompassed within the protection range of wood invention.
Claims (12)
1, a kind of nitride read-only memory unit structure with double top oxide layer is characterized in that: finish the structure that is provided with most oxide-nitride thing-oxides, with as floating grid at the semiconductor-based end of FEOL; The semiconductor-based end between the structure of this oxide-nitride thing-oxide, be provided with most buried regions ions diffusion zones; The top oxide layer is covered in the structure of this oxide-nitride thing-oxide and the surface in this buried regions ions diffusion zone; A most buried regions oxide layer are positioned on this buried regions ions diffusion zone; Linear this oxide layer top, top that is formed in of most bar polysilicon characters.
2, nitride read-only memory unit structure according to claim 1 is characterized in that: the structure of this oxide-nitride thing-oxide is from bottom to top piled up by silicon dioxide layer, silicon nitride layer and silicon dioxide layer in regular turn and is formed.
3, nitride read-only memory unit structure according to claim 2 is characterized in that: the silicon dioxide layer via nitride of this bottom is handled, and forms the silicon dioxide layer of nitrogenize.
4, nitride read-only memory unit structure according to claim 1 is characterized in that: this buried regions ions diffusion zone is N type ion doped region.
5, nitride read-only memory unit structure according to claim 1 is characterized in that: this top oxide layer is to utilize the high temperature chemical vapor deposition method to deposit to form.
6, nitride read-only memory unit structure according to claim 1 is characterized in that: this top thickness of oxide layer is between 20-100 .
7, a kind of manufacture method with nitride read-only memory unit structure of double top oxide layer, it is characterized in that: it comprises the following steps:
(1) provides the semiconductor-based end of finishing FEOL;
(2) utilize the photoetching etch process, on this semiconductor-based end, form the structure of most oxide-nitride thing-oxides, with as floating grid;
(3) on the semiconductor-based end between the structure of this oxide-nitride thing-oxide, carry out ion and implant, to form most buried regions ions diffusion zones;
(4) deposition one top oxide layer is covered in the structure of this oxide-nitride thing-oxide and the surface in this buried regions ions diffusion zone;
(5) on this buried regions ions diffusion zone, be formed with the buried regions oxide layer;
(6) above this top oxide layer, be formed with most bar polysilicon character lines.
8, the manufacture method with nitride read-only memory unit structure of double top oxide layer according to claim 7 is characterized in that: the structure of this oxide-nitride thing-oxide is from bottom to top piled up by silicon dioxide layer, silicon nitride layer and silicon dioxide layer in regular turn and is formed.
9, the manufacture method with nitride read-only memory unit structure of double top oxide layer according to claim 8 is characterized in that: the silicon dioxide layer via nitride of this bottom is handled, and forms the silicon dioxide layer of nitrogenize.
10, the manufacture method with nitride read-only memory unit structure of double top oxide layer according to claim 7 is characterized in that: this buried regions ions diffusion zone is N type ion doped region.
11, the manufacture method with nitride read-only memory unit structure of double top oxide layer according to claim 7 is characterized in that: this top oxide layer is to utilize the high temperature chemical vapor deposition method to deposit to form.
12, the manufacture method with nitride read-only memory unit structure of double top oxide layer according to claim 7, it is characterized in that: this top thickness of oxide layer is between 20-100 .
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| CNB011206888A CN1174490C (en) | 2001-07-27 | 2001-07-27 | Nitride read-only memory unit structure with double top oxide layer and its manufacture |
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| JP4198903B2 (en) * | 2001-08-31 | 2008-12-17 | 株式会社東芝 | Semiconductor memory device |
| CN108155193A (en) * | 2017-12-21 | 2018-06-12 | 上海华力微电子有限公司 | The production method of semiconductor structure |
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