CN1201388C - Manufacture of flash memory - Google Patents
Manufacture of flash memory Download PDFInfo
- Publication number
- CN1201388C CN1201388C CN01123961.1A CN01123961A CN1201388C CN 1201388 C CN1201388 C CN 1201388C CN 01123961 A CN01123961 A CN 01123961A CN 1201388 C CN1201388 C CN 1201388C
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- Prior art keywords
- conductive layer
- flash memory
- layer
- manufacture method
- shallow trench
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- 230000015654 memory Effects 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 238000002955 isolation Methods 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 238000007667 floating Methods 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 125000006850 spacer group Chemical group 0.000 abstract description 8
- 230000008878 coupling Effects 0.000 description 9
- 238000010168 coupling process Methods 0.000 description 9
- 238000005859 coupling reaction Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 6
- 238000012856 packing Methods 0.000 description 3
- 230000002860 competitive effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000013500 data storage Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
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- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention relates to a manufacturing method of a flash memory, which comprises: a half manufactured semiconductor base plate is provided, wherein a tunnel oxide layer is formed on the semiconductor base plate, a first conducting layer is formed on the tunnel oxide layer, and shallow channel isolation is formed; a part of the first conducting layer is removed, so that the shallow channel isolation is higher than the first conducting layer; a dielectric layer is deposited, and etchback is stopped on the first conduct layer to form a spacer; the first conducting layer is etched with the spacer as an etching shadow mask to form a groove; a part of the shallow channel isolation is removed, so that the outer surface of the groove is exposed; the spacer is removed to form a floating gate; finally, a thin dielectric layer is deposited, and a second conducting layer is deposited and patterned to form a control gate.
Description
(1) technical field
The present invention relates to a kind of manufacture method of flash memory, particularly a kind of stacking gate formula flash memory manufacturing method that high capacitance coupling ratio (capacitive coupling ratio) is provided.
(2) background technology
Read-only memory (Read Only Memory) abbreviates ROM as, and memory that ROM deposited in or data can not disappear because of the interruption of power supply supply, therefore is called nonvolatile memory (Non-VolatileMemory) again.And nonvolatile memory is under updating, and develops flash memory (flashmemory).Flash memory (flash memory) has electricity programming (electrical program) and electricity is wiped (electrical erasure) two kinds of operations.Generally speaking, flash memory is made up of mnemon array (memory cell array) and peripheral circuit two large divisions, is to be made of in staggered word line (word line) of array and bit line (bit line) many mnemon marshallings as the flash memory cell array of data storage wherein.Required power supply circuit when peripheral circuit then provides flash memory operation, and the interlock circuit of data input, output.According to the gate electrode Shape Classification, flash memory cell can be divided into two big classes, and one is stacking gate formula (stack-gate) flash memory cell, and another is separate gate formula (split-gate) flash memory cell.
The technology of traditional stacking gate formula flash memory referring to United States Patent (USP) 6,180,459, can be a typically representative.Shown in Figure 1A, a semiconductor substrate 1 is provided, form tunnel oxidation layer 2, first polysilicon layer 3 and silicon nitride layer 4 in regular turn.Shown in Figure 1B, on semiconductor substrate 1, form shallow trench isolation from 5, to define active region.Shown in Fig. 1 C, behind the removal silicon nitride layer 4, deposit a thin dielectric layer 6 and second polysilicon layer 7 more in regular turn.Shown in Fig. 1 D, patterning defines control gate (controlgate), and uses lithography to finish control gate (control gate), finishes whole stacking gate (stack-gate) at last.
Clearly, the stacking gate formula flash memory that uses conventional art to make, fabrication steps is numerous and diverse, does not cause reliability good and reduce acceptance rate, increases manufacturing cost, influences its competitiveness.And conventional art, when integrated circuit manufacture process enters time micron or deep-sub-micrometer technology, will have a strong impact on its competitiveness.In addition, conventional art can't further improve capacitive coupling ratio (capacitive coupling ratio), to increase the electrical of flash memory, when integrated circuit manufacture process enters time micron or deep-sub-micrometer technology, can't further promote the electrical of flash memory, also can't improve product quality, thereby lose the competitive advantage in market, lag behind other rivals.
(3) summary of the invention
The manufacture method that the purpose of this invention is to provide a kind of flash memory, this method can reduce the complexity of processing procedure, and reliability is increased and the acceptance rate raising.
According to an aspect of the present invention, a kind of manufacture method of flash memory may further comprise the steps: a semiconductor substrate of having finished FEOL (a) is provided, wherein formed first conductive layer of a tunnel oxidation layer and top thereof on this semiconductor substrate, with shallow trench isolation from (STI); (b) remove this first conductive layer of part, make this shallow trench isolation exceed this first conductive layer from (STI); (c) deposition one dielectric layer, and eat-back (etchback) and stop at this first conductive layer, to form clearance wall (spacer); (d) be etching mask with this clearance wall, this first conductive layer of etching forms a groove; (e) remove this shallow trench isolation of part from (STI), this groove outer surface is exposed; (f) remove this clearance wall, to form a floating grid (floating gate).
According to another aspect of the present invention, a kind of manufacture method of flash memory may further comprise the steps: a semiconductor substrate of having finished FEOL (a) is provided, wherein formed first conductive layer of a tunnel oxidation layer and top thereof on this semiconductor substrate, with shallow trench isolation from (STI); (b) remove this first conductive layer of part, make this shallow trench isolation exceed this first conductive layer from (STI); (c) deposition one dielectric layer, this dielectric layer and this shallow trench isolation use same material from (STI), and eat-back (etchback) and stop at this first conductive layer, with formation clearance wall (spacer); (d) be etching mask with this clearance wall, this first conductive layer of etching forms a groove; (e) remove this clearance wall and this shallow trench isolation of part simultaneously from (STI), this groove outer surface is exposed, to form a floating grid (floating gate).
By following detailed description of the invention in conjunction with the accompanying drawings, will make above-mentioned purpose of the present invention, advantage and summary of the invention become clearer.
(4) description of drawings
Figure 1A to Fig. 1 D is traditional flash memory process schematic diagram.
Fig. 2 A to Fig. 2 F is preferred embodiment of the present invention, and the fabrication steps schematic diagram.
Drawing reference numeral:
1,8 semiconductor substrates; 2,9 tunnel oxidation layers; 5,11 shallow trench isolations from; 3 first polysilicon layers; 4 silicon nitride layers; 6,15 thin dielectric layers; 7 second polysilicon layers; 10 first conductive layers; 12 dielectric layers; 13 grooves; 14 floating grids; 16 second conductive layers; 17 control gates.
(5) embodiment
A kind of manufacture method of flash memory, its step is as follows: semiconductor substrate 8 is provided, form a tunnel oxidation layer 9 and first conductive layer 10 in regular turn after, form shallow trench isolation again from 11 (Shallow trenchisolation; ST1), finished FEOL so, wherein first conductive layer 10 is that polysilicon (poly-silicon), metal silicide (metal silicide) or amorphous silicon (amorphous silicon) are wherein a kind of, and its thickness is between 1000 to 5000 .Certainly be that industry is known, FEOL also can make different order into and realize, for example: form shallow trench isolation earlier from (STI) on semiconductor substrate, deposit a tunnel oxidation layer 9 and first conductive layer 10 more in regular turn.
Emphasis of the present invention is, removes part first conductive layer 10, makes this shallow trench isolation exceed this first conductive layer 10 from 11 (STI), needs in order to successive process, shown in Fig. 2 A.
Shown in Fig. 2 B, deposit a dielectric layer 12, and carry out this dielectric layer 12 and eat-back (etchback), stop at first conductive layer 10, make this dielectric layer 12 form clearance wall (spacer), and expose the part surface of first conductive layer 10, wherein these dielectric layer 12 thickness are between 100 to 1000 .
Shown in Fig. 2 C, the clearance wall (spacer) that forms with dielectric layer 12 is etching mask (etchingmask), utilize the technology of traditional lithography, first conductive layer 10 is formed a groove 13, and the inner surface that groove 13 is exposed, promptly be to hold surface area partly between floating grid 14 (floating gate) and the control gate 17 (control gate) (shown in Fig. 2 F), when the surface area that holds part is big, (capacitive coupling ratio) is also bigger for the capacitive coupling ratio, thereby increases the electrical of flash memory.
Generally speaking, shallow trench isolation is silicon dioxide (SiO from 11 employed packing materials
2), but also the someone adopts silicon nitride (Si
xN
y), material that uses when dielectric layer 12 and shallow trench isolation are when 11 employed packing materials are inequality, remove the part shallow trench isolation after 11, just shown in Fig. 2 D, the outer surface of groove 13 is exposed, with increase with control gate 17 (control gate) (shown in Fig. 2 F) between institute held the surface area of part, increasing capacitive coupling ratio (capacitive coupling ratio).The material that uses when dielectric layer 12 and shallow trench isolation just can remove dielectric layer 12 formation clearance walls (spacer) and part shallow trench isolation simultaneously from 11 when 11 employed packing materials are identical, this groove outer surface is exposed, to form a floating grid 14.
Shown in Fig. 2 E, remove dielectric layer 12 after, deposit a thin dielectric layer 15 again as the intermediate layer, it is a kind of in nitride-oxide skin(coating) (NO) or the oxide-nitride-oxide layer (ONO), and thickness is between 50 to 300 .Deposit one second conductive layer 16 again, it is a kind of in polysilicon or metal silicide or the amorphous silicon.
Shown in Fig. 2 F, patterning second conductive layer 16 utilizes photolithography techniques to form a control gate 17 (control gate), just so finish stacking gate (Stack-gate) then.
In sum, the present invention has following advantage at least: simple with the prepared floating grid of method of the present invention than the conventional art processing procedure, and reliability is risen, and then promote acceptance rate, reduce manufacturing cost, increase the competitiveness of industry.And mode of the present invention, can reach the more effect of narrow linewidth, when integrated circuit manufacture process enters time micron or deep-sub-micrometer technology, will further more promote the competitiveness of industry.In addition,,, can further improve the capacitive coupling ratio, and then increase the electrical of flash memory, product quality is promoted, thereby strengthen the competitive advantage in market because expose more surface area with the prepared floating grid of method of the present invention.
Above-mentioned in conjunction with the accompanying drawings to the detailed description of preferred embodiment of the present invention, only be used to understand enforcement of the present invention, non-ly be used to limit the present invention, and the technical staff who is familiar with this field skill is after comprehension spirit of the present invention, can in not break away from the present invention's spiritual scope, do some some change, revise and equal variation replacement.Therefore protection scope of the present invention is limited by thereafter claims.
Claims (10)
1, a kind of manufacture method of flash memory may further comprise the steps:
(a) provide a semiconductor substrate of having finished FEOL, wherein formed first conductive layer of a tunnel oxidation layer and top thereof on this semiconductor substrate, with shallow trench isolation from;
(b) remove this first conductive layer of part, make this shallow trench isolation from exceeding this first conductive layer;
(c) deposition one dielectric layer, and eat-back and stop at this first conductive layer, to form clearance wall;
(d) be etching mask with this clearance wall, this first conductive layer of etching forms a groove;
(e) remove the part this shallow trench isolation from, this groove outer surface is exposed;
(f) remove this clearance wall, to form a floating grid.
2, the manufacture method of flash memory as claimed in claim 1 wherein comprises afterwards in step (f):
(g) deposition one thin dielectric layer:
(h) deposit one second conductive layer again, and this second conductive layer of patterning, to form a control gate.
3, the manufacture method of flash memory as claimed in claim 1, wherein this first conductive layer is a kind of in polysilicon, metal silicide or the amorphous silicon.
4, as the manufacture method of claim 1 a described flash memory, wherein this dielectric layer is a kind of in silicon dioxide or the silicon nitride.
5, the manufacture method of flash memory as claimed in claim 1, wherein this medium thickness is between 100 to 1000 .
6, the manufacture method of flash memory as claimed in claim 2, wherein this thin dielectric layer thickness is between 50 to 300 .
7, as the manufacture method of claim 2 a described flash memory, wherein this thin dielectric layer is a kind of in nitride-oxide skin(coating) or the oxide-nitride-oxide layer.
8, the manufacture method of flash memory as claimed in claim 2, wherein this this second conductive layer is a kind of in polysilicon, metal silicide or the amorphous silicon.
9, a kind of manufacture method of flash memory may further comprise the steps:
(a) provide a semiconductor substrate of having finished FEOL, wherein formed first conductive layer of a tunnel oxidation layer and top thereof on this semiconductor substrate, with shallow trench isolation from;
(b) remove this first conductive layer of part, make this shallow trench isolation from exceeding this first conductive layer;
(c) deposition one dielectric layer, this dielectric layer and this shallow trench isolation be from using same material, and eat-back and stop at this first conductive layer, with the formation clearance wall;
(d) be etching mask with this clearance wall, this first conductive layer of etching forms a groove;
(e) remove simultaneously this clearance wall and the part this shallow trench isolation from, this groove outer surface is exposed, to form a floating grid.
10, as the manufacture method of claim the 9 described flash memories, wherein also comprise afterwards in step (e):
(f) deposition one thin dielectric layer;
(g) deposit one second conductive layer again, and this second conductive layer of patterning, to form a control grid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN01123961.1A CN1201388C (en) | 2001-08-08 | 2001-08-08 | Manufacture of flash memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN01123961.1A CN1201388C (en) | 2001-08-08 | 2001-08-08 | Manufacture of flash memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1332474A CN1332474A (en) | 2002-01-23 |
| CN1201388C true CN1201388C (en) | 2005-05-11 |
Family
ID=4665396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN01123961.1A Expired - Lifetime CN1201388C (en) | 2001-08-08 | 2001-08-08 | Manufacture of flash memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1201388C (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100390964C (en) * | 2004-11-03 | 2008-05-28 | 力晶半导体股份有限公司 | Nonvolatile memory and manufacturing method thereof |
| CN100446220C (en) * | 2005-08-16 | 2008-12-24 | 力晶半导体股份有限公司 | Method of manufacturing semiconductor components |
| US7355239B1 (en) * | 2006-08-31 | 2008-04-08 | Promos Technologies Pte. Ltd. | Fabrication of semiconductor device exhibiting reduced dielectric loss in isolation trenches |
| KR100861218B1 (en) * | 2007-06-26 | 2008-09-30 | 주식회사 동부하이텍 | Method of manufacturing flash memory device |
| CN101740521B (en) * | 2008-11-25 | 2011-06-22 | 上海华虹Nec电子有限公司 | Manufacturing method of flash memory |
| CN102420229A (en) * | 2011-07-12 | 2012-04-18 | 上海华力微电子有限公司 | Structure of metal-insulator-metal MOS capacitor and manufacturing method thereof |
| CN104617048B (en) * | 2013-11-05 | 2017-11-03 | 中芯国际集成电路制造(上海)有限公司 | Flash memory and forming method thereof |
| CN105575969B (en) * | 2014-10-17 | 2020-06-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN108133937A (en) * | 2017-12-21 | 2018-06-08 | 上海华力微电子有限公司 | Flush memory device and its manufacturing method |
-
2001
- 2001-08-08 CN CN01123961.1A patent/CN1201388C/en not_active Expired - Lifetime
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| Publication number | Publication date |
|---|---|
| CN1332474A (en) | 2002-01-23 |
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