CN100446220C - Method of manufacturing semiconductor components - Google Patents
Method of manufacturing semiconductor components Download PDFInfo
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- CN100446220C CN100446220C CNB2005100920404A CN200510092040A CN100446220C CN 100446220 C CN100446220 C CN 100446220C CN B2005100920404 A CNB2005100920404 A CN B2005100920404A CN 200510092040 A CN200510092040 A CN 200510092040A CN 100446220 C CN100446220 C CN 100446220C
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- 239000004065 semiconductor Substances 0.000 title claims description 41
- 238000004519 manufacturing process Methods 0.000 title claims description 34
- 239000004020 conductor Substances 0.000 claims abstract description 126
- 239000000463 material Substances 0.000 claims abstract description 78
- 238000000034 method Methods 0.000 claims abstract description 74
- 239000000758 substrate Substances 0.000 claims abstract description 64
- 238000002955 isolation Methods 0.000 claims abstract description 58
- 238000005530 etching Methods 0.000 claims abstract description 45
- 239000012774 insulation material Substances 0.000 claims description 21
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 238000000059 patterning Methods 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 239000003795 chemical substances by application Substances 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 238000005260 corrosion Methods 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 230000005641 tunneling Effects 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 3
- 239000002210 silicon-based material Substances 0.000 claims 2
- 239000011810 insulating material Substances 0.000 abstract description 5
- 239000002131 composite material Substances 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 210000003323 beak Anatomy 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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Abstract
The method includes steps: first, forming multiple isolation structure on substrate to define out active region; next, forming multiple component structures on substrate of the active region, and top parts of these component structures are higher than surface of the substrate; then, forming isolation layer on surface of the component structure; forming conductor layer and material layer on the substrate in sequence in order to cover the isolation layer and exposed substrate, and the material layer possesses fluidity; afterwards, carrying out first etching step to remove the material layer, and partial conductor layer; forming insulating material layer on the substrate layer; finally, carrying out second etching procedure for the insulating material layer to form a pair of gap wall of conductor.
Description
Technical field
The present invention relates to a kind of semiconductor technology, particularly relate to a kind of manufacture method of semiconductor element.
Background technology
In recent years, semi-conducting material has been widely used in the middle of the various electronics industries because of characteristics such as its special conductive capabilities.The application category of semi-conducting material is very extensive, and transistor, high voltage devices, logic element, memory component or the like all are contained in wherein such as.On the other hand, when component size is dwindled gradually, integrated level (Integration) improves gradually, and interelement isolation structure also must dwindle, so the degree of difficulty of element separation technology also increases gradually.With present isolation technology, because fleet plough groove isolation structure (Shallow Trench Isolation, STI) has the easy advantage of adjusting size, and can avoid the shortcoming that beak corrodes in traditional area oxidation (LOCOS) the method isolation technology, therefore, it is a kind of comparatively desirable isolation technology for inferior half micron and following metal-oxide-semiconductor's technology.
In general, before the element technology of being correlated with, can carry out the related process of fleet plough groove isolation structure earlier.Therefore, by finishing of fleet plough groove isolation structure 100, can in substrate 102, define active area 104 (as shown in Figure 1).And the making of relevant semiconductor element can be carried out on active area 104 subsequently, and for example, the memory component 106 among Fig. 1 is formed on the active area 104.
Yet,, may have following problem if desire on the sidewall of memory component 106, to form clearance wall 108.In general, the formation method of clearance wall 108 is to form one deck spacer material layer earlier, and then carries out anisotropic etching process, and forms it.But, when carrying out anisotropic etching process, because the existence, the particularly top of fleet plough groove isolation structure 100 of fleet plough groove isolation structure 100 and the difference in height between substrate 102 surfaces, but may make 110 (as shown in Figure 1) of its sidewall generation residual gap wall.So will cause adjacent two memory components 106 to interconnect (Bridge).And, if the material of this gap wall material layer is a conductor material, more will cause the short circuit each other of continuous memory component.
Summary of the invention
In view of this, purpose of the present invention is exactly that a kind of manufacture method of semiconductor element is being provided, to solve adjacent two semiconductor elements because of the interconnective problem of isolation structure.
The present invention proposes a kind of manufacture method of semiconductor element, and the method provides a substrate earlier, and this substrate comprises that at least a plurality of isolation structures are disposed in the substrate, and wherein these isolation structures define active area, and the top of these isolation structures is higher than substrate surface; A plurality of component structures are arranged in the substrate of active area, and wherein the end face of these component structures is higher than the item face of these isolation structures; And one the edge layer cover these component structures.Then, in substrate, form first conductor layer, cover insulating barrier and substrate.Afterwards, form material layer on first conductor layer, wherein material layer has flowability.Then, carry out first etching step, remove material layer and first conductor layer partly.Continue it, in substrate, form insulation material layer, cover first conductor layer that remains.Then, insulation material layer is carried out second etching step, to form the pair of conductors clearance wall.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, the material of above-mentioned material layer for example is to be selected from a photo anti-corrosion agent material and an antireflection coating material one.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, wherein first etching step is to utilize be selected from those component structure tops and those isolation structure tops one as etching end point.
Because the present invention is before forming the conductor clearance wall, form first conductor layer and material layer earlier, and its etch-back made its planarization, therefore can avoid when forming the conductor clearance wall, the conductor clearance wall also is formed at the sidewall of isolation structure, and causes the interconnective problem of adjacent two semiconductor elements.
The present invention proposes a kind of manufacture method of semiconductor element, and the method is prior to forming a plurality of isolation structures in the substrate, to define an active area.Then, in the substrate of active area, form the mask layer of patterning.Then, be etching mask with the mask layer of patterning, and in mask layer and substrate, form a plurality of grooves.Afterwards, in groove, form a plurality of plough groove type elements, and the top of these plough groove type elements is higher than the top of isolation structure.Continue it, remove the mask layer of patterning.Then, in substrate, form dielectric layer, covering groove formula element.Then, in substrate, form first conductor layer, cover dielectric layer and substrate.Afterwards, form material layer on first conductor layer, wherein material layer has flowability.Then, carry out first etching step, remove material layer and first conductor layer partly.Then, in substrate, form insulation material layer, cover first conductor layer that remains.Continue it, insulation material layer is carried out second etching step, to form the conductor clearance wall.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, the material of above-mentioned material layer for example is to be selected from a photo anti-corrosion agent material and an antireflection coating material one.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, the first above-mentioned etching step is to utilize be selected from those plough groove type element tops and those isolation structure tops one as etching end point.
Because the present invention is before forming the conductor clearance wall, form first conductor layer and material layer earlier, and its etch-back made its planarization, therefore can avoid when forming the conductor clearance wall, the conductor clearance wall also is formed at the sidewall of isolation structure, and causes the interconnective problem of adjacent two semiconductor elements.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 illustrates to looking schematic diagram on existing a kind of memory component.
Fig. 2 illustrates to according to looking schematic diagram on a kind of memory component of a preferred embodiment of the present invention.
Fig. 3 A to Fig. 3 H illustrates and is wherein two memory cell 10 of Fig. 2 manufacturing process generalized section by I-I ' section gained.
The simple symbol explanation
10: memory cell
20: isolation structure
100: fleet plough groove isolation structure
102: substrate
104,30: active area
106: memory component
108,212,236a: clearance wall
110: the residual gap wall
202: lining
204: mask layer
206: groove
208: tunneling layer
210,210a, 228,228a, 232: conductor layer
214a, 214b: floating grid
216: source area
218,218a, 226: dielectric layer between grid
222: source electrode line
224: cap layer
230: material layer
234: the composite conductor layer
236: insulation material layer
238a, 238b: composite conductor clearance wall
Embodiment
Be to do explanation in following explanation with the memory component in the semiconductor element, only non-in order to limit the present invention.In the following embodiments, memory component is arranged in groove, therefore it can be considered as a plough groove type element.
Fig. 2 illustrates according to looking schematic diagram on a kind of memory component of one embodiment of the present invention.Fig. 3 A to Fig. 3 H is the manufacturing process generalized section of wherein two memory cell 10 of Fig. 2 by I-I ' section gained.
At first, please be simultaneously with reference to Fig. 2 and Fig. 3 A, substrate 200 is provided, this substrate 200 has formed at least one isolation structure 20, this isolation structure 20 is the strip layout, and define active area 30, and the top of these isolation structures 20 is higher than substrate 200 surfaces, and its top of follow-up formed plough groove type element can be higher than the top of isolation structure 20.Wherein, the formation method of isolation structure 20 for example is regional oxidizing process or shallow trench isolation method.
Then, form lining 202 in substrate 200 surfaces of active area 30, the material of this lining 202 for example is a silica, and its formation method for example is a thermal oxidation method.In addition, in another preferred embodiment, also can go up and form the thicker dielectric layer (not illustrating) of thickness, and its formation method for example is a chemical vapour deposition technique in substrate 200 surfaces.Then, form mask layer 204 on lining 202, the material of this mask layer 204 for example is a silicon nitride, and its formation method for example is a chemical vapour deposition technique.Continue it, patterned mask layer 204, lining 202 and substrate 200 are to form groove 206 in mask layer 204, lining 202 and substrate 200.
Afterwards, 200 surfaces of the substrate in groove 206 form tunneling layer 208.Wherein, the material of tunneling layer 208 for example is a silica, and its formation method for example is a thermal oxidation method.Then, in groove 206, insert conductor layer 210.Wherein, the material of conductor layer 210 for example is a doped polycrystalline silicon, and its formation method for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer, to carry out the ion implantation step, and form it.
Then, please refer to Fig. 3 B, carry out the etch-back step, the conductor layer 210 of etching part, and stay conductor layer 210a in the groove 206, so that the top of conductor layer 210a is higher than substrate 200 surfaces, and be lower than mask layer 204 surfaces.At this moment, can utilize isolation structure 20 highly to define the height of conductor layer 210a, just utilize isolation structure 20 to be used as etching end point, make that the end face of conductor layer 210a and isolation structure 20 end faces are rough contour.Continue it, form a pair of clearance wall 212, and cover the upper surface of the conductor layer 210a of part in exposed groove 206 sidewalls.Wherein, the material of clearance wall 212 for example is to have different etching selectivity persons with conductor layer 210a.The formation method of clearance wall 212 for example is to form one deck spacer material layer (not illustrating) earlier, utilizes anisotropic etch process to remove part spacer material layer then, and forms it.
Afterwards, please refer to Fig. 3 C, is etching mask with this to clearance wall 212, removes the conductor layer 210a of part once more, forms floating grid 214a and floating grid 214b with the sidewall in groove 206.
Then, in the substrate 200 of groove 206 bottoms, form source area 216.Wherein, the formation method of source area 216 for example is an ion implantation technology.
Then, please refer to Fig. 3 D, go up dielectric layer 218 between the formation grid in substrate 200 and groove 206 surfaces.Wherein, the material of dielectric layer 218 for example is silicon oxide/silicon nitride/silicon oxide or silica between grid.
Then, please refer to Fig. 3 E, remove dielectric layer 218 and tunneling layer 208 between the grid of part, exposing substrate 200 surfaces of groove 206 bottoms, and form dielectric layer 218a between grid.Wherein, the method that removes comprises anisotropic etching process, and it for example is a dry etch process.
Then, insert a conductor material with as source electrode line 222 in groove 206, the top of this source electrode line 222 is higher than floating grid 214a and 214b.At this moment, the configuration relation of source electrode line 222 and isolation structure 20 as shown in Figure 2, promptly source electrode line 222 strides across isolation structure 20.In addition, the material of source electrode line 222 for example is a doped polycrystalline silicon.Continue it, form cap layer 224, filling up groove 206, and cover source electrode line 222.
Afterwards, please refer to Fig. 3 F, remove lining 202 and mask layer 204.In forming dielectric layer 226 between the grid that cover substrate 200 and substrate 200 surface textures in the substrate 200.Wherein, the material of dielectric layer 226 for example is silica or silicon oxide/silicon nitride/silicon oxide between grid.
Then, in substrate 200, form conductor layer 228, dielectric layer 226 and exposed substrate 200 between covering gate.Wherein, the material of conductor layer 228 for example is polysilicon, doped polycrystalline silicon or other suitable material, and its formation method for example is a chemical vapor deposition method.
Continue it, on conductor layer 228, form material layer 230.In a preferred embodiment, the material of material layer 230 for example is a material of flowable, so that most material can be inserted the zone between the isolation structure 20 among Fig. 2, and form the rete of non-conformal (no-conformal), to reach the purpose of subsequent planarization.That is material layer 230 thickness between isolation structure 20 can be greater than other zone.And in a better embodiment, the material of material layer 230 for example is photo anti-corrosion agent material or organic antireflecting coating material etc., and its formation method for example is spin coating method (Spin Coating).
Afterwards, please refer to Fig. 3 G, carry out etching step, remove material layer 230 and conductor layer 228 partly.Wherein above-mentioned etching step can with the cap layer on the source electrode line 222 224 be etching end point or with the top of isolation structure 20 as etching end point.That is, when being used for stopping etch-back when etched sensing instrument detects cap layer 224 tops on the source electrode line 222, or in the follow-up etch-back that stops when detecting isolation structure 20 tops.At this moment, the conductor layer 228 that is remained can dwindle and the evenly isolation structure 20 among Fig. 2 and the difference in height between the substrate 200.
Then, in substrate 200, form conductor layer 232.This conductor layer 232 for example is to have the material of low resistance more than conductor layer 228a, to adjust the resistance of whole composite conductor layer 234.For instance, if the material of conductor layer 228a is polysilicon or doped polycrystalline silicon, then the material of conductor layer 232 can be a metal silicide such as tungsten silicide for example, to reduce the resistance of whole composite conductor layer 234.In addition, in a preferred embodiment, before forming conductor layer 232, more can be prior to the rete (not illustrating) of another layer of the last formation of conductor layer 228a with the identical or different material of conductor layer 228a, it for example is polysilicon or doped polycrystalline silicon, and this rete also has the effect of the resistance of adjusting whole composite conductor layer 234 equally.Subsequently, in substrate 200, form insulation material layer 236, cover conductor layer 232.Wherein, insulation material layer 236 for example is a silicon nitride layer.
Continue it, please refer to Fig. 3 H, insulation material layer 236 is carried out etch process, on source electrode line 222 sidewalls, form a pair of clearance wall 236a, the conductor layer 232 of cover part after the etch-back.Wherein, etch process for example is an anisotropic etching process.
Then, be mask with clearance wall 236a, definition conductor layer 232,228a (composite conductor layer 234), to form a pair of composite conductor clearance wall 238a and 238b, this composite conductor clearance wall 238a and 238b can be used as and select the grid or the usefulness of word line.
The conductor clearance wall of the preferred embodiment of the present invention, promptly be by conductor layer 228, perhaps add conductor layer 232 and optionally and again between conductor layer 228 and conductor layer 232, increase another conductor layer (not illustrating) that forms, 236 storehouses of insulating material of adding outermost constitute, generally with material, for example be to constitute conductor layer by polysilicon (conductor layer 228)/polysilicon (another conductor layer)/metal silicide (conductor layer 232), and outermost again covering insulating material 236 be electrically connected preventing.So, though describe in the foregoing description, the clearance wall 236a of the insulating material 236 after can defining defines as mask and forms the conductor clearance wall, but also can utilize for example single etching step of anisotropic etching, define insulation material layer 236, conductor layer 232 and conductor layer 228a (composite conductor layer 234) simultaneously and form the conductor clearance wall, the invention is not restricted to this.
What deserves to be mentioned is, because the present invention is before the two side conductor clearance walls that form above-mentioned plough groove type element, forming first conductor layer and utilization earlier has mobile layer of material covers and makes its planarization, therefore etch-back after, can dwindle and even Fig. 2 in isolation structure 20 and the difference in height between the substrate 200, thereby when forming conductor clearance wall 238a, 238b, can avoid forming the conductor clearance wall in the sidewall of isolation structure 20.That is to say that though we utilize isolation structure to make floating grid, and make the end face of the end face of floating grid and isolation structure contour, we are when forming first conductor layer, it can fill up the gap between the isolation structure.Therefore, when follow-up both sides definition at the plough groove type element forms clearance wall, be not easy to form undesirable clearance wall in the gap of isolation structure.So, utilize method of the present invention can solve existing adjacent two memory components and interconnect because of isolation structure, even problem of short-circuit.
In addition, utilize method of the present invention can also avoid problems such as the damage of formed metal silicide and formed clearance wall are too little.Detailed says so, owing to utilize the formed clearance wall 236a of method of the present invention can have bigger size, thereby composite conductor clearance wall 238a, its size of 238b of defining out by this gap wall 236a are also bigger, and promptly (Critical Dimension CD) can become big to critical dimension.So this composite conductor clearance wall also can have than lower in the past resistance.And; be positioned at clearance wall 236a on composite conductor clearance wall 238a, the 238b when it is applied to follow-up contact window technology, because its size is bigger, and thickness is thicker; therefore can effectively protect composite conductor clearance wall 238a, the 238b of its below, avoid it to sustain damage.
In addition, method of the present invention, i.e. the step of before the composite conductor clearance wall forms, being carried out, for example the formation of conductor layer and material layer with and the etch-back step, be not limited in above-mentioned element technology.In other words, the technology of the element of other type also can be applied to method of the present invention wherein.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (22)
1, a kind of manufacture method of semiconductor element comprises:
One substrate is provided, and this substrate comprises at least:
A plurality of isolation structures are disposed in this substrate, and wherein those isolation structures define an active area, and the top of those isolation structures is higher than this substrate surface;
A plurality of component structures are arranged in this substrate of this active area, and wherein the end face of those component structures is higher than the end face of those isolation structures; And
One insulating barrier covers those component structures;
In this substrate, form one first conductor layer, cover this insulating barrier and this substrate;
Form a material layer on this first conductor layer, wherein this material layer has flowability;
Carry out one first etching step, remove this material layer and this first conductor layer of part;
In this substrate, form an insulation material layer, cover this first conductor layer that remains; And
This insulation material layer is carried out one second etching step, to form a conductor clearance wall.
2, the manufacture method of semiconductor element as claimed in claim 1, wherein the material of this material layer is selected from a photo anti-corrosion agent material and an antireflection coating material one.
3, the manufacture method of semiconductor element as claimed in claim 1, wherein this first etching step utilization is selected from those component structure tops and those isolation structure tops one as etching end point.
4, the manufacture method of semiconductor element as claimed in claim 1, wherein after carrying out this first etching step and before forming this insulation material layer, also be included in this substrate and form one second conductor layer, and this second conductor layer and this first conductor layer constitute this conductor clearance wall behind this second etching step.
5, the manufacture method of semiconductor element as claimed in claim 4, wherein the material of this first conductor layer and this second conductor layer is all polycrystalline silicon material.
6, the manufacture method of semiconductor element as claimed in claim 4, wherein after forming this second conductor layer and before forming this insulation material layer, also be included in and form one the 3rd conductor layer on this second conductor layer, and the 3rd conductor layer, this second conductor layer and this first conductor layer constitute this conductor clearance wall behind this second etching step.
7, the manufacture method of semiconductor element as claimed in claim 6, wherein the material of the 3rd conductor layer is a metal silicide.
8, the manufacture method of semiconductor element as claimed in claim 1, wherein the material of this insulation material layer is a silicon nitride.
9, the manufacture method of semiconductor element as claimed in claim 1, wherein this second etching step utilizes an anisotropic etching process.
10, the manufacture method of semiconductor element as claimed in claim 1, wherein when carrying out this second etching step, this insulation material layer of first patterning, and utilize this insulation material layer behind the patterning to be mask again, come this first conductor layer of patterning.
11, a kind of manufacture method of semiconductor element comprises:
In a substrate, form a plurality of isolation structures, to define an active area;
In this substrate of this active area, form the mask layer of a patterning;
Mask layer with this patterning is an etching mask, and forms a plurality of grooves in this mask layer and this substrate;
In those grooves, form a plurality of plough groove type elements, and the top of those plough groove type elements is higher than the top of those isolation structures;
Remove the mask layer of this patterning;
In this substrate, form a dielectric layer, cover those plough groove type elements;
In this substrate, form one first conductor layer, cover this dielectric layer and this substrate;
Form a material layer on this first conductor layer, wherein this material layer has flowability;
Carry out one first etching step, remove this material layer and this first conductor layer of part;
In this substrate, form an insulation material layer, cover this first conductor layer that remains; And
This insulation material layer is carried out one second etching step, to form a conductor clearance wall.
12, the manufacture method of semiconductor element as claimed in claim 11, wherein the material of this material layer is selected from a photo anti-corrosion agent material and an antireflection coating material one.
13, the manufacture method of semiconductor element as claimed in claim 11, wherein this first etching step utilization is selected from those plough groove type element tops and those isolation structure tops one as etching end point.
14, the manufacture method of semiconductor element as claimed in claim 11, wherein after carrying out this first etching step and before forming this insulation material layer, also be included in and form one second conductor layer in this substrate, and this second conductor layer and this first conductor layer constitute this conductor clearance wall after this second etching step.
15, the manufacture method of semiconductor element as claimed in claim 14, wherein the material of this first conductor layer and this second conductor layer is all polycrystalline silicon material.
16, the manufacture method of semiconductor element as claimed in claim 14, wherein after forming this second conductor layer and before forming this insulation material layer, also be included in and form one the 3rd conductor layer on this second conductor layer, and the 3rd conductor layer, this second conductor layer and this first conductor layer constitute this conductor clearance wall after this second etching step.
17, the manufacture method of semiconductor element as claimed in claim 16, wherein the material of the 3rd conductor layer is a metal silicide.
18, the manufacture method of semiconductor element as claimed in claim 11, wherein the material of this insulation material layer is a silicon nitride.
19, the manufacture method of semiconductor element as claimed in claim 11, wherein this second etching step adopts an anisotropic etching process.
20, the manufacture method of semiconductor element as claimed in claim 11, wherein respectively the formation method of this plough groove type element comprises:
This substrate surface in this groove respectively forms a tunneling layer;
Form one first floating grid and one second floating grid in the sidewall of this groove respectively; And
In respectively inserting a conductor material in this groove, and between this conductor material and this first floating grid and this second floating grid, form a gate dielectric as isolation.
21, the manufacture method of semiconductor element as claimed in claim 20, wherein the formation method of this plough groove type element also is included in this substrate of this channel bottom respectively and forms the one source pole district.
22, the manufacture method of semiconductor element as claimed in claim 20, this conductor material of wherein inserting this groove are as the one source pole line, and the top of this source electrode line is higher than the top of this first floating grid and this second floating grid.
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| CNB2005100920404A CN100446220C (en) | 2005-08-16 | 2005-08-16 | Method of manufacturing semiconductor components |
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|---|---|---|---|
| CNB2005100920404A CN100446220C (en) | 2005-08-16 | 2005-08-16 | Method of manufacturing semiconductor components |
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| CN100446220C true CN100446220C (en) | 2008-12-24 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW227545B (en) * | 1992-01-27 | 1994-08-01 | Shinko Denki Kabushiri Kaisha | |
| US5998263A (en) * | 1996-05-16 | 1999-12-07 | Altera Corporation | High-density nonvolatile memory cell |
| US6284597B1 (en) * | 1999-01-30 | 2001-09-04 | United Microelectronics, Corp. | Method of fabricating flash memory |
| CN1332474A (en) * | 2001-08-08 | 2002-01-23 | 世界先进积体电路股份有限公司 | Manufacture of flash memory |
| CN1450628A (en) * | 2002-04-08 | 2003-10-22 | 华邦电子股份有限公司 | Flash memory structure and mfg method thereof |
| CN1577803A (en) * | 2003-06-30 | 2005-02-09 | 海力士半导体有限公司 | Method for manufacturing flash memory device |
-
2005
- 2005-08-16 CN CNB2005100920404A patent/CN100446220C/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW227545B (en) * | 1992-01-27 | 1994-08-01 | Shinko Denki Kabushiri Kaisha | |
| US5998263A (en) * | 1996-05-16 | 1999-12-07 | Altera Corporation | High-density nonvolatile memory cell |
| US6284597B1 (en) * | 1999-01-30 | 2001-09-04 | United Microelectronics, Corp. | Method of fabricating flash memory |
| CN1332474A (en) * | 2001-08-08 | 2002-01-23 | 世界先进积体电路股份有限公司 | Manufacture of flash memory |
| CN1450628A (en) * | 2002-04-08 | 2003-10-22 | 华邦电子股份有限公司 | Flash memory structure and mfg method thereof |
| CN1577803A (en) * | 2003-06-30 | 2005-02-09 | 海力士半导体有限公司 | Method for manufacturing flash memory device |
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| CN1917172A (en) | 2007-02-21 |
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