CN1450628A - Flash memory structure and mfg method thereof - Google Patents
Flash memory structure and mfg method thereof Download PDFInfo
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- CN1450628A CN1450628A CN02106191.2A CN02106191A CN1450628A CN 1450628 A CN1450628 A CN 1450628A CN 02106191 A CN02106191 A CN 02106191A CN 1450628 A CN1450628 A CN 1450628A
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- 238000002955 isolation Methods 0.000 claims abstract description 50
- 238000005530 etching Methods 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052710 silicon Inorganic materials 0.000 claims description 23
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- 229910052814 silicon oxide Inorganic materials 0.000 description 26
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- 229910052581 Si3N4 Inorganic materials 0.000 description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 18
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Abstract
This invention relates to a flash structure and its processing method in which, the finished flash suspended grating does not need microimage method, so situation of mistaken aligning will not occur between the suspended grating layer and the active zone, utilizing etching channel insulation zone to reach convex structure and its only necessary to add the etching depth of channel isolation area to increase the couple area between suspending grating layer and controlling grating to increase their cross link capacity without sacrificing flash total area.
Description
Technical field
The present invention relates to a kind of memory device, relate in particular to a kind of flash memory (Flash memory) structure and preparation method thereof, flash memory structure tool autoregistration (self-align).
Background technology
When the function of computer microprocessor is more and more strong, the data computation that software carried out is also more and more huge, and the demand of internal memory is also just higher certainly.Therefore more the development of high integration is meaning the generation of more jumbo internal memory.When latter stage in the 1980's Intel with erasable programmable read only memory (Electrically Erasable Programmable ROM, when EEPROM) identical structural development goes out " flash memory " (Flash memory), because data can repeatedly deposit in, read and remove, therefore become the internal memory of new generation of speed with fastest developing speed.
Non-voltile memory, especially flash memory, cumulative its importance in various application.In recent years, the demand of flash memory is higher than other internal memory gradually, therefore, how to develop the flash memory technology of new generation and the area of reduction flash memory and has become an important topic.
The similar EPROM of flash memory also has the stacked gate of control gate and suspension grid, and unique difference is for there being the high-quality thin tunnel silicon dioxide layer of wearing of one deck under the suspension grid.Write fashionablely when program, hot electron will be worn tunnel (Tunneling), and this thin wear the tunnel silicon dioxide layer and enters the suspension grid, similar EPROM; When memory is wiped, can be as long as control gate is imposed negative voltage by thin the wearing the tunnel silicon dioxide layer and leave the suspension grid of cold electrons tunnel to source electrode.
Though the structure of flash memory is identical with EEPROM, because mechanism is wiped in its storage and EEPROM is not quite similar, so volume is more much smaller than EEPROM; Simultaneously the erasing time of its data is about 1 or 2 second, and is also faster with about 20 minutes of UV-irradiation than EPROM.Therefore come flash memory to combine the advantage of EPROM and EEPROM as can be seen.
As shown in fig. 1 be flash memory according to the prior art manufacturing, it has comprised in P type semiconductor substrate 10, with photoresistance pattern (not marking) definition active region 16.Then, with the dry-etching method form dark about 300-450nm in the recessed semiconductor chip shallow trench isolation regions 17 (ShallowTrench Isolation, STI).Then remove the photoresistance pattern, and form a storehouse grid structure thereon.Stacked gate has comprised wears tunnel silicon dioxide layer 12, suspended grid layer 13.Wear after tunnel silicon dioxide layer 12 and suspended grid layer 13 form thin, then form the insulating barrier 14 and the control grid layer 15 of silicon oxide/silicon nitride/silicon oxide (ONO).Wherein, when forming suspended grid layer 13, need to be defined its position with another light shield.Therefore, in traditional technology, I haven't seen you for ages usually requires the twice light shield to form suspended grid layer 13 and active region 16.
Suppose voltage V is added on the control grid layer 15, and the voltage that makes the semiconductor-based end 10 is 0 o'clock, owing to be electric capacity commissure (Capacitance Coupling) state between the semiconductor-based end 10, suspended grid layer 13 and the control grid layer 15, so be added in the voltage (V on the suspended grid layer 13
FG) can calculate by following formula:
In the following formula, C
1Commissure electric capacity for 13 on the semiconductor-based end 10 and suspended grid layer.C
2The commissure electric capacity that suspended grid layer 13 and control grid layer are 15.
When the technology of flash memory drops to 0.18 μ m with the size of channel length, even during 0.13 μ m,, can be subjected to the alignment issues of 16 of suspended grid layer 13 and active regions for the flash memory method of previous non-use autoregistration (self-align) technology.On the other hand, for inject the flash memory of suspended grid by source electrode with electronics, suspended grid can cover source electrode area the more or wear tunnel silicon dioxide layer 12 thinner, and the sequencing speed that heals big is just arranged, yet lowers the problem that the thickness of wearing tunnel silicon dioxide layer 12 has the data holding time.
On the other hand, when being under the situation of definite value at applied voltage, in order to increase the voltage (V on the suspended grid layer 13
FG), wear tunnel silicon dioxide layer electric current to reach under the minimum voltage applied situation, to produce, can utilize increases C
2Capacitance, cause most applied voltage all to drop on the suspended grid layer 13 and reach, that is increase the area of 15 of suspended grid layer 13 and control grid layers.But, make suspended grid interlayer separation distance each other that its threshold value be arranged because lithography has its dimension limit.Therefore if will utilize the mode that increases area to strengthen C
2Capacitance because the restriction of threshold value also causes and need use larger area shallow trench isolation regions 17, amplified whole flash memory area on the contrary.Though, the dimension limit of utilizing partition crack method to overcome lithography is arranged traditionally, further reduce suspended grid interlayer separation distance each other.But, still be limited therefore reducing on the whole flash memory area because it still will use lithography.
Therefore how to solve the alignment issues of 16 of suspended grid layer 13 and active regions and under the situation that does not increase whole flash memory area, increase C
2Capacitance, become the maximum problem that flash memory technology faced now.
In above-mentioned background of invention, according to the formed flash memory of conventional art,, therefore carrying out light shield on time owing between its suspended grid layer and active region, need use the different light shield in two sides to form respectively at least, Chang Wufa does more accurate control.
Summary of the invention
A purpose of the present invention is to provide a kind of flash memory structure and preparation method thereof, uses a kind of flash memory of autoregistration formula to solve the problems referred to above.
Another object of the present invention is to provide a kind of suspended grid layer structure and its method, under the area of not sacrificing flash memory, promote the coupling area of suspended grid layer and control grid interlayer, to increase commissure electric capacity therebetween.
According to the method disclosed in the present, its step that comprises is isolated active region at first form the shallow trench isolation regions of isolating usefulness on the semiconductor-based end.The described shallow trench isolation regions of etching forms one silica layer on the surface of shallow trench isolation regions that caves in and chip again to form the shallow trench isolation regions of a depression.Utilize the described silicon oxide layer of anisotropic dry ecthing, the side at active region forms the partition crack.Utilize thermal oxidation method to form the thin tunnel silicon dioxide layer of wearing, form doped polycrystalline silicon layer on the shallow trench isolation regions surface of tunnel silicon dioxide layer, partition crack layer and depression with as suspended grid wearing then.Then backfill one silicon nitride layer utilizes thermal oxidation method that the polysilicon layer that do not covered by silicon nitride layer is oxidized to silica in the shallow trench isolation regions of this depression, and with the hot phosphoric acid solution etches both silicon nitride layer.With the silicon oxide layer is this polysilicon layer of etch mask etching, makes suspended grid separated from one another.Then form silicon oxide layer, silicon nitride layer and silicon oxide layer in regular turn to finish the dielectric layer of an ONO structure, on the ONO dielectric layer, form the polysilicon doping grid then with as controlling grid, utilize the grid structure etching in addition of traditional little shadow and engraving method again with storehouse, to form character line, produce required doped region with traditional ion implantation method more at last and finish this invention with the drain electrode back as source electrode.
The suspended grid of the flash memory of being finished need not use method for photolithography in this way, therefore can't be as conventional art, owing between suspended grid layer and active region, need use the different light shield in two sides to form respectively at least, and the situation of alignment error often takes place.And suspended grid of the present invention utilizes the etch channels isolated area to reach lobed structure, therefore if desire promotes the coupling area of suspended grid layer and control grid interlayer, only need increase etch depth,, increase commissure electric capacity therebetween so can not sacrifice under the flash memory gross area situation.
In other words, the present invention discloses a kind of manufacture method of flash memory, is applied to it is characterized in that in the semiconductor substrate, has the active region that is isolated by isolation structure at described the semiconductor-based end, and described method comprises the following step at least:
Described isolation structure to a degree of depth of etching is to form the umbilicate type isolation structure;
Form the first conformal dielectric layer on described active region and described umbilicate type isolation structure;
Described first dielectric layer of etching is to form the partition crack on described active region sidewall;
Carry out thermal oxidation process to form tunnel oxide on described active region surface;
Form conformal doped silicon layer on described tunnel oxide and described umbilicate type isolation structure;
Backfill one sacrifice layer is in described umbilicate type isolation structure;
Form oxide layer on the described doped silicon layer surface that exposes;
With described oxide layer is the cover curtain, and described sacrifice layer of etching and described doped silicon layer are to expose the upper surface of described umbilicate type isolation structure;
Remove described oxide layer;
Form one second dielectric layer on the surface of described doped silicon layer and described umbilicate type isolation structure;
Form a conductor layer on described second dielectric layer;
The described conductor layer of patterning is to form character line; And
Described isolation structure is shallow trench isolation regions or field oxide.
The described degree of depth of the described isolation structure of etching is about 200 to 400nm.
The material of described first dielectric layer must have high etch-selectivity with silicon.
The dosage that described doped silicon layer ion is implanted then is about 1 * 10
18To 1 * 10
21Cm
-3Between.
Described sacrifice layer tool high antioxidant.
The present invention also discloses a kind of flash memory structure, be formed on the semiconductor chip, it is characterized in that, described semiconductor chip comprises the semiconductor substrate, have the island active region that is isolated by the umbilicate type isolation structure on the described semiconductor-based end, described structure comprises at least:
One partition crack is positioned on the described active region sidewall;
One tunnel oxide is positioned on the described active region surface;
A conformal doped silicon layer is covered on described tunnel oxide and the described partition crack, with being suspended grid;
One dielectric layer is covered on the surface of described doped silicon layer and described umbilicate type isolation structure; And
One conductor layer is positioned on the described dielectric layer, with being control gate.
The upper surface of the described umbilicate type isolation structure of described etching is about 200 to 400nm than the upper surface of described island active region is low.
The ion doping dosage of described doped silicon layer is about 1 * 10
18To 1 * 10
21Cm
-3Between.
Afore-mentioned of the present invention and many attendant advantages be as with reference to following being described in detail, and will be more prone in conjunction with the accompanying drawings understand.
Description of drawings
Fig. 1 is the cross sectional view of semiconductor chip, has exemplified according to the formed flash memory of prior art;
Fig. 2 is the cross sectional view that forms shallow trench isolation according to the present invention on the semiconductor chip;
Fig. 3 is the cross sectional view that forms shallow trench isolation according to the present invention on the semiconductor chip;
Fig. 4 is the cross sectional view according to the present invention's etching shallow trench isolation to a degree of depth on the semiconductor chip;
Fig. 5 is the cross sectional view that forms first dielectric layer of a concurrence according to the present invention on the semiconductor chip;
Fig. 6 is according to the cross sectional view of the present invention behind this first dielectric layer of etching on the semiconductor chip;
Fig. 7 is the cross sectional view that forms the doped silicon layer of a tunnel oxide and a concurrence according to the present invention on the semiconductor chip;
Fig. 8 is the cross sectional view according to the present invention's backfill one sacrifice layer on the semiconductor chip;
Fig. 9 is according to the cross sectional view of the present invention after carrying out by the use of thermal means on the semiconductor chip;
Figure 10 is according to the cross sectional view of the present invention behind this sacrifice layer of etching on the semiconductor chip;
Figure 11 is according to the cross sectional view of the present invention behind etching doped silicon layer on the semiconductor chip;
Figure 12 is for pressing the cross sectional view of the present invention after forming the O/N/O dielectric layer on the semiconductor chip;
Figure 13-1 is the cross sectional view that forms a conductor layer according to the present invention on an O/N/O dielectric layer;
Figure 13-2 is the vertical view of semiconductor chip.Among the figure:
10 12 silicon dioxide layers, 13 suspended grid layers, 14 insulating barrier of the semiconductor-based end
15 control grid layers, 16 active regions, 17 shallow trench isolation regions
20 semiconductor chips, 22 pad oxides, 24 silicon nitride layers, 26 active regions
28 trench isolation regions, 30,32 silicon oxide layers
Tunnel silicon dioxide layer 38 amorphous silicons or polysilicon layer are worn in 34 partition cracks 36
40 silicon nitride layers, 42 silicon oxide layers, 44 suspended grids
Embodiment
Do not limiting under spirit of the present invention and the range of application, below promptly with an embodiment, introduce enforcement of the present invention; Those of ordinary skills, after understanding spirit of the present invention, be used for various flash memory method when using method of the present invention, eliminate traditionally because between suspended grid layer and active region, at least need use the different light shield in two sides to form respectively, so that aim at the shortcoming that alignment error takes place often carrying out light shield.Simultaneously, flash memory structure of the present invention can not sacrificed under the flash memory gross area situation, improves the coupling area of suspended grid layer and control grid interlayer, to increase commissure electric capacity therebetween.Application of the present invention is as the embodiment that is not limited only to the following stated.
As described in background of invention, when being under the situation of definite value at applied voltage, for increasing the voltage (V on the suspended grid layer
FG), the commissure electric capacity that can increase suspended grid layer and control grid interlayer is reached, and promptly increases the area of suspended grid layer and control grid interlayer.But, make between suspended grid separation distance each other that its threshold value is arranged because lithography has its dimension limit.When the assembly channel is reduced to 0.13 μ m or littler again by 0.18 μ m, certainly will to take another kind of flash memory structure to solve above-mentioned problem.Therefore, the present invention provides one to utilize the methods of making some coupling areas in the method for shallow trench isolation at above-mentioned problem more, to reach the purpose of the commissure electric capacity that increases suspended grid layer and control grid interlayer.
Because the method for flash memory comprises many known technology, little shadow shielding for example well known and engraving method, therefore many steps will be at this detailed description.
Detail content of the present invention can come to be described in detail with reference to the accompanying drawings.Cross sectional representation as shown in Figure 2 at first, forms pad oxide 22 at the upper surface of semiconductor chip (for example silicon) 20 with thermal oxidation process, to relax the then stress of the silicon nitride layer 24 of deposition.Then, with photoresistance pattern (not icon) definition active region 26.Then, form the trench isolation regions 28 of dark about 300-450nm in the recessed semiconductor chip with the dry-etching method.Remove photoresistance pattern (not icon) earlier, afterwards,, deposit another silicon oxide layer 30 again with chemical vapour deposition technique.And fill up trench isolation regions 28.Inferior is that stop layer carries out chemical and mechanical grinding method with silicon nitride layer 24.Subsequently, as Fig. 3 with hot phosphoric acid etch silicon nitride layer 24.Again with HF solution etching pad oxide 22.Above-mentioned trench isolation regions 28 also can be regional the oxidizing process field oxide that forms replace.
Subsequently, for reaching the coupling area of increase suspended grid layer of the present invention and control grid interlayer.Cross sectional representation as shown in Figure 4.Utilize carbon monofluoride (CF
4) the electric selectivity dry-etching of carrying out silicon oxide layer 30 of starching, to remove the silicon oxide layer 30 of part, form the shallow trench isolation regions of a depression.Etched depth is about 200 to 400nm, looks closely institute's desire suspended grid layer that increases and the coupling area of controlling the grid interlayer.
As shown in Figure 5, then deposit the dielectric layer of one deck conformal (conformal) on the surface of the active region 26 and the shallow trench isolation regions 28 of depression, wherein said dielectric layer must have high etching selectivity with silicon layer.Dielectric layer 32 is generally silicon oxide layer 32, and its thickness is about 400 to 1000 dusts.Then, consult Fig. 6, be coated with the chip of silicon oxide layer 32, will be placed into dry etcher,, form partition crack (Spacer) 34 as shown in Figure 6 with the etching mode (Anisotropic Etch) of anisotropic.Carry out etching as traditional grid partition crack.This step, it mainly is the anisotropic that utilizes dry ecthing, major part is deposited on silicon oxide layer 32 on the chip, with the thickness that it was deposited is that benchmark is removed, because silicon oxide layer 32 thickness that are positioned on active region 26 sidewalls are height than other parts, therefore after the anisotropic dry ecthing, the silicon oxide layer 32 that part is positioned on active region 26 sidewalls will can not be removed fully, form partition crack (Spacer) 34 as shown in Figure 6.
Then please refer to cross sectional representation shown in Figure 7, one silica layer forms on the surface of active region 26 with as wearing tunnel silicon dioxide layer 36.In one embodiment, this to wear tunnel silicon dioxide layer 36 be to utilize oxygen atmosphere thermal growth oxide and forming between 800 to 1000 ℃ of temperature.And this thickness of wearing tunnel silicon dioxide layer 36 can arrive required thickness easily via the control of pressure and time, and in one embodiment, the thickness of wearing tunnel silicon dioxide layer 36 is greatly between 80 to 100 dusts.
Still consult Fig. 7, then an amorphous silicon or polysilicon layer 38 are deposited on the surface of chip with the method for concurrence.Amorphous silicon or polysilicon layer 38 can utilize traditional chemical vapour deposition technique (CVD) and form, and also can utilize other known method to be formed simultaneously.This doped amorphous silicon or polysilicon layer 38 thickness are about between 200 to 800 dusts.In flash memory, this amorphous silicon or polysilicon layer 38 are called suspended grid because be not connected with other conductor.This suspended grid can be used to store charge simultaneously.
Consult Fig. 7 again, after amorphous silicon or polysilicon layer 38 forms, utilize N type or p type impurity carry out ion be implanted to this amorphous silicon or polysilicon layer 38 in.In a preferred embodiment, implant energy between 5 to 30KeV, the dosage of implantation then is about 1 * 10
18To 1 * 10
21Cm
-3
Please refer to cross sectional representation shown in Figure 8, again again with chemical vapour deposition technique (CVD), deposit a silicon nitride layer 40 in the depression shallow trench isolation regions in as sacrifice layer, then again with etching method or chemical mechanical milling method (Chemical Mechanical Polish, CMP), the part that will exceed raceway groove is removed.Using silicon nitride is because silicon nitride layer has good non-oxidizability as the backfilling material most important reason, with in method for oxidation thereafter, can not form silicon oxide layer thereon.
Please refer to cross sectional representation shown in Figure 9.With the thermal oxidation method of high temperature, form the silicon oxide layer 42 of thick about 100 to 300 dusts.Because silicon nitride layer has good non-oxidizability, therefore can not form silicon oxide layer 42 thereon.Then, please refer to cross sectional representation shown in Figure 10, for example can use hot phosphoric acid solution that silicon nitride layer 40 is etched away.
Please refer to cross sectional representation shown in Figure 11.The silicon oxide layer 42 that utilization is deposited on the polysilicon layer 38 is the cover curtain, etching mode (Anisotropic Etch) with anisotropic, the polysilicon layer that not oxidized silicon layer 42 is covered carries out the dry ecthing of anisotropic, forms suspended grid 44 separated from one another.This moment, formed suspended grid 44 was self-aligned to active region 26, in other words, use method of the present invention when forming suspended grid 44, and unlike as the conventional method, need carry out one method for photolithography again, therefore can eliminate the alignment error problem of 26 of suspended grid 44 and active regions.Then, the silicon oxide layer 42 that will be deposited on again on the polysilicon layer 38 removes, and this method that removes can dry ecthing method or utilized hydrofluoric acid solution to carry out.
Please refer to cross sectional representation shown in Figure 12.Then the mode with oxide layer-nitride layer-oxide layer (ONO) forms a dielectric layer 46.In the method for ONO, form the bottom silicon oxide layer of ONO dielectric layer 46 earlier earlier with the thermal oxidation process of high temperature.The thickness of this bottom silicon oxide layer is preferably between about 40 to 120 dusts.Then utilize once more traditional Low Pressure Chemical Vapor Deposition (LPCVD) with silicon nitride layer be deposited on the bottom silicon oxide layer on, and again with thermal oxidation or similarly method the top layer silicon oxide layer is formed at going up of silicon nitride layer and constitutes complete ONO dielectric layer 46.The thickness of this silicon nitride layer is preferably between about 60-120 dust, and the thickness of top silicon oxide layer then is between the 20-80 dust.
Please refer to the cross sectional representation shown in Figure 13-1.One conductor layer 48 forms on ONO dielectric layer 46.This conductor layer 48 is also formed with traditional chemical vapour deposition technique (CVD) or other suitable method.In one embodiment, it forms thickness greatly between the 1000-3000 dust.Conductor layer 48 is to be selected from doped polycrystalline silicon, doped amorphous silicon or metal silicide layer.Wherein this metal silicide layer can be made up of the polysilicon and the tungsten silicide that mix.This conductor layer 48 also can be described as the control grid, is used for the access of control data.
Still please refer to the cross sectional representation shown in Figure 13-1.Then, use the photoresistance pattern (not showing among the figure) of a covering place book character line to cover All Ranges and define character line, and utilize traditional engraving method with in addition etching and form character line 50 of polysilicon layer 48, shown in Figure 13-2.The vertical view that Figure 13-2 correspondence is looked along b-b ' direction, wherein figure number 50 is represented the character line that is defined.
Still please refer to shown in Figure 13-2 vertical view then along b-b '.With another photoresistance pattern (not showing among the figure) that exposes source/drain regions, in active region 26, define source/drain regions.Impose again n+ (if N type substrate then for or P+) implanting ions, n type impurity is to be selected from one of group that arsenic and phosphorus forms.Energy and dosage are about 20-60keV and 1 * 10 respectively
14To 1 * 10
16/ cm
2Remove the photoresistance pattern at last, promptly finish this method.
Autoregistration flash memory method of the present invention has following advantage, owing to utilize method of the present invention to form suspended grid, need not use method for photolithography, therefore can't be as the conventional art, because between suspended grid layer and active region, at least need use the different light shield in two sides to form respectively, and the situation of alignment error often takes place.On the other hand, the flash memory structure of finishing via this method, owing to have partition crack 34 in the both sides of active region 26, these partition cracks 34 mainly are the commissure electric capacity that is used for reducing by 44 of active region 26 and suspended grids.
Suspended grid 44 lobed structures of the present invention, he utilizes etch channels isolated area 28 to reach, so if desire promotes the coupling area of suspended grid layer and control grid interlayer, only need increase etch depth, therefore can not sacrifice under the flash memory gross area situation, increase commissure electric capacity therebetween.
Understand as the person skilled in the art, the above only is preferred embodiment of the present invention, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the claim.
Claims (9)
1. the manufacture method of a flash memory is applied to it is characterized in that in the semiconductor substrate, and have the active region that is isolated by isolation structure, described method comprises the following step at least at described the semiconductor-based end:
Described isolation structure to a degree of depth of etching is to form the umbilicate type isolation structure;
Form the first conformal dielectric layer on described active region and described umbilicate type isolation structure;
Described first dielectric layer of etching is to form the partition crack on described active region sidewall;
Carry out thermal oxidation process to form tunnel oxide on described active region surface;
Form conformal doped silicon layer on described tunnel oxide and described umbilicate type isolation structure;
Backfill one sacrifice layer is in described umbilicate type isolation structure;
Form oxide layer on the described doped silicon layer surface that exposes;
With described oxide layer is the cover curtain, and described sacrifice layer of etching and described doped silicon layer are to expose the upper surface of described umbilicate type isolation structure;
Remove described oxide layer;
Form one second dielectric layer on the surface of described doped silicon layer and described umbilicate type isolation structure;
Form a conductor layer on described second dielectric layer;
The described conductor layer of patterning is to form character line; And
With described character line serves as to cover an act implanting ions that carries out described active region to form source electrode and drain electrode.
2. the manufacture method of flash memory as claimed in claim 1 is characterized in that, described isolation structure is shallow trench isolation regions or field oxide.
3. the manufacture method of flash memory as claimed in claim 1 is characterized in that, the described degree of depth of the described isolation structure of etching is about 200 to 400nm.
4. the manufacture method of flash memory as claimed in claim 1 is characterized in that, the material of described first dielectric layer must have high etch-selectivity with silicon.
5. the manufacture method of flash memory as claimed in claim 1 is characterized in that, the dosage that described doped silicon layer ion is implanted then is about 1 * 10
18To 1 * 10
21Cm
-3Between.
6. the manufacture method of flash memory as claimed in claim 1 is characterized in that, described sacrifice layer tool high antioxidant.
7. a flash memory structure is formed on the semiconductor chip, it is characterized in that, described semiconductor chip comprises the semiconductor substrate, has the island active region that is isolated by the umbilicate type isolation structure on the described semiconductor-based end, and described structure comprises at least:
One partition crack is positioned on the described active region sidewall;
One tunnel oxide is positioned on the described active region surface;
A conformal doped silicon layer is covered on described tunnel oxide and the described partition crack, with being suspended grid;
One dielectric layer is covered on the surface of described doped silicon layer and described umbilicate type isolation structure; And
One conductor layer is positioned on the described dielectric layer, with being control gate.
8. flash memory structure as claimed in claim 7 is characterized in that, the upper surface of the described umbilicate type isolation structure of described etching is about 200 to 400nm than the upper surface of described island active region is low.
9. flash memory structure as claimed in claim 7 is characterized in that, the ion doping dosage of described doped silicon layer is about 1 * 10
18To 1 * 10
21Cm
-3Between.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100446220C (en) * | 2005-08-16 | 2008-12-24 | 力晶半导体股份有限公司 | Method of manufacturing semiconductor components |
| CN101419932B (en) * | 2007-06-26 | 2011-04-13 | 东部高科股份有限公司 | Production method of flash memory |
| CN102420214A (en) * | 2010-09-25 | 2012-04-18 | 中芯国际集成电路制造(上海)有限公司 | Method for forming strengthened aligning marks and semiconductor device |
| CN101783349B (en) * | 2009-01-15 | 2012-07-11 | 旺宏电子股份有限公司 | Data storage structure, memory device and process for fabricating memory device |
| CN104167354B (en) * | 2014-09-18 | 2017-07-28 | 上海华力微电子有限公司 | The method that gate oxide homogeneity is improved by the dual oxide of grid oxygen |
| US20230284444A1 (en) * | 2022-03-03 | 2023-09-07 | Nanya Technology Corporation | Memory device having active area in strip and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105192846A (en) * | 2015-08-21 | 2015-12-30 | 四川省汇泉罐头食品有限公司 | Preservative applicable to cans |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5460988A (en) * | 1994-04-25 | 1995-10-24 | United Microelectronics Corporation | Process for high density flash EPROM cell |
| US5414287A (en) * | 1994-04-25 | 1995-05-09 | United Microelectronics Corporation | Process for high density split-gate memory cell for flash or EPROM |
| US6215145B1 (en) * | 1998-04-06 | 2001-04-10 | Micron Technology, Inc. | Dense SOI flash memory array structure |
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2002
- 2002-04-08 CN CNB021061912A patent/CN100395885C/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100446220C (en) * | 2005-08-16 | 2008-12-24 | 力晶半导体股份有限公司 | Method of manufacturing semiconductor components |
| CN101419932B (en) * | 2007-06-26 | 2011-04-13 | 东部高科股份有限公司 | Production method of flash memory |
| CN101783349B (en) * | 2009-01-15 | 2012-07-11 | 旺宏电子股份有限公司 | Data storage structure, memory device and process for fabricating memory device |
| CN102420214A (en) * | 2010-09-25 | 2012-04-18 | 中芯国际集成电路制造(上海)有限公司 | Method for forming strengthened aligning marks and semiconductor device |
| CN102420214B (en) * | 2010-09-25 | 2017-06-13 | 中芯国际集成电路制造(上海)有限公司 | Form the method and semiconductor devices of reinforcing alignment mark |
| CN104167354B (en) * | 2014-09-18 | 2017-07-28 | 上海华力微电子有限公司 | The method that gate oxide homogeneity is improved by the dual oxide of grid oxygen |
| US20230284444A1 (en) * | 2022-03-03 | 2023-09-07 | Nanya Technology Corporation | Memory device having active area in strip and manufacturing method thereof |
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| Publication number | Publication date |
|---|---|
| CN100395885C (en) | 2008-06-18 |
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