CN1309056C - Structure of non-volatile memory and its making method - Google Patents
Structure of non-volatile memory and its making method Download PDFInfo
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- CN1309056C CN1309056C CNB2004100332696A CN200410033269A CN1309056C CN 1309056 C CN1309056 C CN 1309056C CN B2004100332696 A CNB2004100332696 A CN B2004100332696A CN 200410033269 A CN200410033269 A CN 200410033269A CN 1309056 C CN1309056 C CN 1309056C
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000007667 floating Methods 0.000 claims abstract description 123
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 238000003860 storage Methods 0.000 claims description 41
- 238000004519 manufacturing process Methods 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims 2
- 230000005641 tunneling Effects 0.000 abstract 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- 238000005530 etching Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
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- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
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- 239000004065 semiconductor Substances 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
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Abstract
The present invention relates to a structure of a non-volatile memory and a making method thereof. The making method comprises: firstly, a mask layer is formed on a substrate, a channel is formed in the mask layer and the substrate, and a tunneling dielectric layer is formed in the channel; subsequently, a floating gate is formed in the channel, and the mask layer is removed; then, a high voltage doped region is formed in the substrate at one side of the floating gate and is simultaneously used as a first source/drain region and a control gate; finally, a second source/drain region is formed in the substrate at the other side of the floating gate.
Description
Technical field
The present invention relates to a kind of structure and manufacture method thereof of semiconductor subassembly, particularly relate to structure and the manufacture method thereof of a kind of nonvolatile storage (non-volatile memory).
Background technology
Because the nonvolatile storage of can electricity programming and erasing has can preserve when non-transformer is supplied that data, access speed are fast, the light weight capacity greatly, advantage such as the access device volume is little, so become one of main product of portable type memory media gradually.The basic structure of this kind nonvolatile storage comprises floating grid, control gate and source/drain region, wherein floating grid is other can establish selection grid in addition, and form a separate gate (Split-gate) structure, in order to the problem that prevents to be caused because of excessively erase (over-erase).
The structure of existing a kind of nonvolatile storage of can electricity programming and erasing as shown in Figure 6, it comprises substrate 600, is positioned at the thermal oxide layer 604 and clearance wall 606, high voltage doped region 608, two selection grid 610 of substrate 600 lip-deep two floating grids 602, floating grid 602 tops and sidewall, and two sources/drain region 612.Wherein, in the substrate 600 of high voltage doped region 608 between two floating grids 602, and overlap with the base section of two floating grids 602, with simultaneously as common source/drain region and control gate.Selection grid 610 are positioned at the outside of floating grid 602, and are separated by with floating grid 602 with thermal oxide layer 604 and clearance wall 606, and source/drain region 612 then is arranged in the substrate 600 of selecting grid 610 outsides.
Though the application of said structure is quite a lot, it still has following problem.Please refer to Fig. 6 because the high voltage doped region 608 of double as control gate only overlaps with the base section of two floating grids 602, so its gate coupled than (
GAte
COupling
RAtio, GCR) very low, make to write and erase operation for use must carry out with high voltage, and be unfavorable for the downsizing of assembly.In addition,, floating grid 602 select the two height of grid 610 very big, so the definition etching of follow-up selection grid 610 difficulty comparatively because adding.Moreover because high voltage doped region 608 must have enough low resistance, but its degree of depth again can not be excessive, in order to avoid cause puncture (punch-thorough) electric leakage, so the reduction space of the width of high voltage doped region 608 is very little, is unfavorable for the downsizing of assembly.
Summary of the invention
For addressing the above problem, the present invention proposes a kind of structure and manufacture method of nonvolatile storage, wherein floating grid some imbed in the substrate, make that high voltage doped region can be adjacent with the side of floating grid.
The manufacture method step of a kind of nonvolatile storage of the present invention is as follows.At first in substrate, form mask layer, in mask layer and substrate, form a groove again, in groove, form tunnel dielectric layer then.Then in groove, form a floating grid, remove mask layer again.Afterwards, form high voltage doped region in the substrate of floating grid one side, it forms second source/drain region more simultaneously as first a source/drain region and a control gate in the substrate of floating grid opposite side.In addition, the opposite side of floating grid also can form one and select grid, and it and is separated with a gate dielectric layer between itself and the substrate between floating grid and second source/drain region.
In the manufacture method of the another kind of nonvolatile storage of the present invention, high voltage doped region is formed in the substrate between two floating grids, and is shared by two memory cell.In addition, the outside of each floating grid also forms one and selects grid, and each selects the outside of grid to be formed with one source/drain region.So-called herein " outside ", promptly be across floating grid and and the part of facing each other of the zone between two floating grids, and the zone between two floating grids is to be " inboard ".
On the other hand, a kind of nonvolatile storage of the present invention comprises a substrate, a floating grid, simultaneously as the high voltage doped region of first source/drain region and control gate, and second source/drain region.Wherein, a groove is arranged in the substrate, and the surface of groove there is a tunnel dielectric layer.Floating grid fills up this groove, and on the outstanding groove.High voltage doped region is arranged in the substrate of floating grid one side, and second source/drain region then is arranged in the substrate of floating grid opposite side.In addition, the opposite side of floating grid also configurable is selected grid, and it and is separated with a gate dielectric layer between itself and the substrate between floating grid and second source/drain region.
In the structure of the another kind of nonvolatile storage of the present invention, in the substrate of high voltage doped region morpheme between two floating grids, and shared by two memory cell.In addition, the outside of each floating grid also has one to select grid, and each selects the outside of grid that one source/drain region is arranged.
As mentioned above, in Nonvolatile memory structure of the present invention, owing to can overlap with the side of floating grid as the high voltage doped region of control gate, so gate coupled can significantly improve than (GCR).In addition, some is imbedded in the substrate owing to floating grid, and therefore its height reduces, so the definition etching of follow-up selection grid is more or less freely.Moreover, because the bottom of floating grid is goed deep in the substrate,, and needn't worry to puncture the problem of electric leakage so high voltage doped region can form deeply with reduction resistance.Therefore, the width of high voltage doped region is promptly reduced, and helps the downsizing of assembly.
Description of drawings
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate institute's accompanying drawing to be described in detail below:
Fig. 1～5 illustrate the manufacturing process profile of the nonvolatile storage of the preferred embodiment of the present invention, and wherein Fig. 5 shows corresponding Nonvolatile memory structure.
Fig. 6 illustrates a kind of section of structure of existing nonvolatile memory cell.
The simple symbol explanation
100: substrate 102: pad oxide
104: silicon nitride hardmask layer 106: groove
108: tunnel oxide 110: floating grid
112: thermal oxide layer 114: mask layer
116: ion injects 118: high voltage doped region
120: silicon oxide layer 122: silicon nitride layer
124: silicon oxide layer 126:ONO clearance wall
128: select grid 130: source/drain electrode
600: substrate 602: floating grid
604: thermal oxide layer 606: clearance wall
608: high voltage doped region 610: select grid
612: source/drain electrode
Embodiment
Fig. 1～5 illustrate the manufacturing process profile of the nonvolatile storage of the preferred embodiment of the present invention, and wherein Fig. 5 shows corresponding Nonvolatile memory structure.
Please refer to Fig. 1, in substrate 100, form pad oxide 102 and silicon nitride hardmask layer 104 at first in regular turn, substrate 100 monocrystal silicon substrate of for example mixing wherein for the P type, and the formation method of silicon nitride hardmask layer 104 for example is a Low Pressure Chemical Vapor Deposition (LPCVD).Then, form a pair of groove 106 in silicon nitride hardmask layer 104 and substrate 100, its step comprises a lithographic fabrication processes and follow-up anisotropic etching manufacturing process.
Please refer to Fig. 2, then the surface of substrate 100 in groove 106 forms tunnel oxide (tunneloxide layer) 108, and its method for example is a thermal oxidation method.Then with a conductor layer, for example be that a doped polysilicon layer fills up groove 106, with as floating grid 110, carry out a severe step of thermal oxidation again, to form the thermal oxide layer 112 of thick middle, thin edge at the top of floating grid 110, its shape makes the top of floating grid 110 be tip-angled shape, and the function of this shape will be in explanation after a while.
Please refer to Fig. 3, then remove silicon nitride hardmask layer 104 and pad oxide 102, form mask layer 114 again in substrate 100, it exposes the substrate 100 between two floating grids 110, and this mask layer 114 for example is the photoresist layer.Then, carry out ion and inject 116, to form high voltage doped region 118 in the substrate 100 between two floating grids 110, common source/drain region and control gate that it is shared as two memory cell are simultaneously removed mask layer 114 again.Then carry out tempering and inject the lattice structure of destroying, and make the below of the range expansion of high voltage doped region 118 simultaneously to the floating grid 110 of part to repair by ion.
Please refer to Fig. 4, then the sidewall that exposes at each floating grid 110 forms the ON clearance wall that is made of silicon oxide layer 120 and silicon nitride layer 122, its formation method comprises and forms conformal silicon oxide layer conformal silicon nitride layer (not illustrating) together in regular turn, this conformal silicon nitride layer of anisotropic etching conformal silicon oxide layer together makes it form the shape of clearance wall again.Then, in substrate 100, form conformal silicon oxide layer 124, with as the separator between floating grid 110 and the selection grid 128 (Fig. 5) that will form after a while, and the gate dielectric layer (Fig. 5) of conduct selection grid 128.
Please refer to Fig. 5, silicon oxide layer 124, the silicon oxide layer 120 of part are set up into an ONO clearance wall 126 jointly with silicon nitride layer 122, and it has the good effect of leaking electricity that prevents.Afterwards, form to select grid 128 in floating grid 110 outsides, the floating grid 110 of its cover part, and be separated by with the top of thermal oxide layer 112 with floating grid 110, be separated by with the ONO clearance wall 126 and the sidewall of floating grid 110, and be separated by with gate dielectric layer 124 and substrate 100.Then, select the outside of grid 126 to form source/drain region 130, promptly finish the manufacturing process of the nonvolatile storage of this preferred embodiment at each.
On the other hand, the Nonvolatile memory structure of the preferred embodiment of the present invention as shown in Figure 5.This structure comprises substrate 100, two floating grids 110, high voltage doped region 118, selects grid 128 and two sources/drain region 130.Wherein, a pair of groove 106 is arranged in the substrate 100, there is tunnel dielectric layer 108 on its surface.Floating grid 110 fills up groove 106, and protrudes on the groove 106.One thermal oxide layer 112 is arranged at the top of each floating grid 110, and its shape makes the top of floating grid 110 be tip-angled shape, and sidewall then has an ONO clearance wall 126.In the substrate 100 of high voltage doped region 118 between two floating grids 110, and two select grid 128 to lay respectively at the outside of two floating grids 110, wherein each selects grid 128 to be separated by with the top of corresponding floating grid 110 with thermal oxide layer 112, be separated by with the ONO clearance wall 126 and the sidewall of this floating grid 110, and be separated by with gate dielectric layer 127 and substrate 100.Two sources/130 of drain regions lay respectively at two and select in the substrate 100 in grid 110 outsides.
In addition, the method for operation illustration of the nonvolatile storage of the preferred embodiment of the present invention is as follows.Please refer to Fig. 5, as the memory cell on the left of desiring to write, then must make the voltage that channel is opened below it applying foot on the selection grid 128 in left side, on source/drain region, left side, apply low-voltage (often being 0V), and on high voltage doped region 118, apply high voltage simultaneously, on floating grid 110, to induce a low slightly high voltage, hot electron is attracted in the floating grid 110, shown in arrow p by this.Otherwise, as the memory cell on the left of desiring to erase, then must on the selection grid 128 in left side, apply positive voltage, simultaneously on high voltage doped region 118, apply negative voltage, can cause the point discharge effect this moment at the left side on floating grid 110 tops sharp corner, and the electronics in the floating grid 110 is expelled in the selection grid 128, shown in arrow e.Because the sharp corner on floating grid 110 tops can produce the point discharge effect, so the positive voltage that is applied on the selection grid 128 can be lower than the required person of erase operation for use of general nonvolatile storage.
As mentioned above, please refer to Fig. 5, in the Nonvolatile memory structure of the preferred embodiment of the present invention, not only overlap as the high voltage doped region 118 of control gate with the bottom of floating grid 110, also simultaneously relative with the side of floating grid 110 across tunnel dielectric layer 108, thus its gate coupled than (GCR) when can significantly improving.In addition and since floating grid 110 some imbed in the substrate 100, therefore its height reduces, so the definition etching of follow-up selection grid 128 is more or less freely.Moreover, because the bottom of floating grid 110 is goed deep in the substrate 100,, and needn't worry to puncture the problem of electric leakage so high voltage doped region 118 can form deeply with reduction resistance.Therefore, the width of high voltage doped region 118 is promptly reduced, and helps the downsizing of assembly.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (26)
1. the manufacture method of a nonvolatile storage comprises:
In a substrate, form a mask layer;
In this mask layer and this substrate, form a groove;
In this groove, form a tunnel dielectric layer;
In this groove, form a floating grid;
Remove this mask layer;
Form a high voltage doped region in this substrate of this floating grid one side, this high voltage doped region is simultaneously as first a source/drain region and a control gate; And
In this substrate of this floating grid opposite side, form second source/drain region.
2. the manufacture method of nonvolatile storage as claimed in claim 1 also comprises:
In this substrate, form a gate dielectric layer; And
Opposite side in this floating grid forms selection grid, and this selects grid between this second source/drain region and this floating grid, and is separated by with this gate dielectric layer and this substrate.
3. the manufacture method of nonvolatile storage as claimed in claim 2, wherein
This floating grid is a doped silicon layer; And this method also comprises:
Carry out a step of thermal oxidation form this floating grid in this groove after, to form a thermal oxide layer at this floating grid top, the shape of this thermal oxide layer makes the top of this floating grid be tip-angled shape; And
After removing this mask layer, the sidewall that exposes in this floating grid forms a clearance wall, wherein
This selects grid this floating grid of cover part at least, and these selection grid are separated by with the top of this thermal oxide layer and this floating grid, and is separated by with the sidewall of this clearance wall and this floating grid.
4. the manufacture method of nonvolatile storage as claimed in claim 3, wherein this clearance wall comprises an ONO clearance wall.
5. the manufacture method of nonvolatile storage as claimed in claim 4, wherein the formation method of this ONO clearance wall comprises:
The sidewall that exposes in this floating grid forms an ON clearance wall; And
Form conformal one silica layer in this substrate, some of these silicon oxide layers are set up into this ONO clearance wall jointly with this ON clearance wall, and this silicon oxide layer of another part is as this gate dielectric layer of this floating grid.
6. the manufacture method of nonvolatile storage as claimed in claim 1, wherein the degree of depth of this high voltage doped region reaches the bottom of this floating grid.
7. the manufacture method of nonvolatile storage as claimed in claim 6, wherein this high voltage doped region also extends to the below of this floating grid of part.
8. the manufacture method of nonvolatile storage as claimed in claim 1, wherein this floating grid fills up this groove.
9. the manufacture method of a nonvolatile storage comprises:
In a substrate, form a mask layer;
In this mask layer and this substrate, form a pair of groove;
Form a tunnel dielectric layer in each flute surfaces;
In each groove, form a floating grid;
Remove this mask layer;
The sidewall that exposes in this floating grid forms a clearance wall;
Form a high voltage doped region in this in to this substrate between the groove, this high voltage doped region is simultaneously as one a common source/drain region and a control gate;
In this substrate, form a gate dielectric layer;
Form one in the outside of each floating grid and select grid, these selection grid are separated by with this gate dielectric layer and this substrate; And
Form one source/drain region in this substrate outside each selects grid.
10. the manufacture method of nonvolatile storage as claimed in claim 9, wherein
Each floating grid is a doped silicon layer; And
This method also comprises:
Carry out a step of thermal oxidation form a floating grid in each groove after, to form a thermal oxide layer at each floating grid top, the shape of this thermal oxide layer makes the top of this floating grid be tip-angled shape, wherein
This selects grid this floating grid of cover part at least, and these selection grid are separated by with the top of this thermal oxide layer and this floating grid, and is separated by with the sidewall of this clearance wall and this floating grid.
11. the manufacture method of nonvolatile storage as claimed in claim 9, wherein each clearance wall comprises an ONO clearance wall.
12. the manufacture method of nonvolatile storage as claimed in claim 11, wherein the formation method of this ONO clearance wall comprises:
The sidewall that exposes in each floating grid forms an ON clearance wall; And
Form conformal one silica layer in this substrate, some of these silicon oxide layers are set up into this ONO clearance wall jointly with this ON clearance wall, and this silicon oxide layer of another part is as this gate dielectric layer of this floating grid.
13. the manufacture method of nonvolatile storage as claimed in claim 9, wherein the degree of depth of this high voltage doped region reaches the bottom of this floating grid.
14. the manufacture method of nonvolatile storage as claimed in claim 13, wherein this high voltage doped region also extends to the below of this floating grid of part.
15. the manufacture method of nonvolatile storage as claimed in claim 9, wherein each floating grid fills up this corresponding groove.
16. a nonvolatile storage comprises:
One substrate has a groove on it, this flute surfaces has a tunnel dielectric layer;
One floating grid, it fills up this groove, and on outstanding this groove;
One high voltage doped region is arranged in this substrate of this floating grid one side, and this high voltage doped region is simultaneously as first a source/drain region and a control gate; And
One second source/drain region is arranged in this substrate of this floating grid opposite side.
17. nonvolatile storage as claimed in claim 16, it also comprises:
One gate dielectric layer is positioned in this substrate;
One selects grid, be positioned at the opposite side of this floating grid, and between this floating grid and this second source/drain region, these selection grid is separated by with this gate dielectric layer and this substrate.
18. nonvolatile storage as claimed in claim 17, wherein
This floating grid is a doped silicon layer, and a thermal oxide layer is arranged at its top, and sidewall has a clearance wall, and wherein the shape of this thermal oxide layer makes the top of this floating grid be tip-angled shape; And
This selects grid this floating grid of cover part at least, and is separated by with the top of this thermal oxide layer and this floating grid, and is separated by with the sidewall of this clearance wall and this floating grid.
19. nonvolatile storage as claimed in claim 18, wherein this clearance wall comprises an ONO clearance wall.
20. nonvolatile storage as claimed in claim 16, wherein the degree of depth of high voltage doped region reaches the bottom of this floating grid.
21. nonvolatile storage as claimed in claim 20, wherein this high voltage doped region also extends to the below of this floating grid of part.
22. a nonvolatile storage comprises:
One substrate has a pair of groove in this substrate, wherein each flute surfaces has a tunnel dielectric layer;
Two floating grids, it fills up this respectively to groove, and gives prominence to this on the groove, and wherein the sidewall of each floating grid has a clearance wall;
One high voltage doped region, in this substrate between this two floating grid, this high voltage doped region is simultaneously as one a common source/drain region and a control gate;
Two select grid, lay respectively at the outside of this two floating grid, and wherein each selects between grid and this substrate gate oxide is arranged; And
Two sources/drain region lay respectively in this substrate in this two selections grid outside.
23. nonvolatile storage as claimed in claim 22, wherein
Each floating grid is a doped polysilicon layer, and a thermal oxide layer is arranged at its top, and the shape of this thermal oxide layer makes the top of this floating grid be tip-angled shape; And
One selection grid cover the part of this corresponding floating grid at least, and are separated by with the top of this thermal oxide layer and this floating grid, and are separated by with the sidewall of this clearance wall and this floating grid.
24. nonvolatile storage as claimed in claim 22, wherein this clearance wall comprises an ONO clearance wall.
25. nonvolatile storage as claimed in claim 22, wherein the degree of depth of this high voltage doped region reaches the bottom of this two floating grid.
26. nonvolatile storage as claimed in claim 25, wherein this high voltage doped region also extends to the below of this two floating grid of part.
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| CNB2004100332696A CN1309056C (en) | 2004-03-29 | 2004-03-29 | Structure of non-volatile memory and its making method |
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| CNB2004100332696A CN1309056C (en) | 2004-03-29 | 2004-03-29 | Structure of non-volatile memory and its making method |
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| CN1309056C true CN1309056C (en) | 2007-04-04 |
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| CN102437161B (en) * | 2011-11-24 | 2015-09-09 | 上海华虹宏力半导体制造有限公司 | Splitting grid memory cell and method of operation thereof |
| US20150255614A1 (en) * | 2014-03-05 | 2015-09-10 | Powerchip Technology Corporation | Split gate flash memory and manufacturing method thereof |
| CN104979354B (en) * | 2014-04-01 | 2018-02-09 | 北京兆易创新科技股份有限公司 | A kind of structure of ETOX NOR-types flash memory and preparation method thereof |
| CN107658298A (en) * | 2016-07-25 | 2018-02-02 | 闪矽公司 | Recessed channel Nonvolatile semiconductor memory device and its manufacture method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5970341A (en) * | 1997-12-11 | 1999-10-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming vertical channels in split-gate flash memory cell |
| US6124608A (en) * | 1997-12-18 | 2000-09-26 | Advanced Micro Devices, Inc. | Non-volatile trench semiconductor device having a shallow drain region |
| US6171906B1 (en) * | 1998-07-06 | 2001-01-09 | Taiwan Semiconductor Manufacturing Company | Method of forming sharp beak of poly to improve erase speed in split gate flash |
| US20040056299A1 (en) * | 2002-09-19 | 2004-03-25 | Yi Ding | Nonvolatile memory cell with a floating gate at least partially located in a trench in a semiconductor substrate |
-
2004
- 2004-03-29 CN CNB2004100332696A patent/CN1309056C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5970341A (en) * | 1997-12-11 | 1999-10-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming vertical channels in split-gate flash memory cell |
| US6124608A (en) * | 1997-12-18 | 2000-09-26 | Advanced Micro Devices, Inc. | Non-volatile trench semiconductor device having a shallow drain region |
| US6171906B1 (en) * | 1998-07-06 | 2001-01-09 | Taiwan Semiconductor Manufacturing Company | Method of forming sharp beak of poly to improve erase speed in split gate flash |
| US20040056299A1 (en) * | 2002-09-19 | 2004-03-25 | Yi Ding | Nonvolatile memory cell with a floating gate at least partially located in a trench in a semiconductor substrate |
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