CN1224080C - Method for producing floating grid in flash memory - Google Patents
Method for producing floating grid in flash memory Download PDFInfo
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- CN1224080C CN1224080C CN 01109538 CN01109538A CN1224080C CN 1224080 C CN1224080 C CN 1224080C CN 01109538 CN01109538 CN 01109538 CN 01109538 A CN01109538 A CN 01109538A CN 1224080 C CN1224080 C CN 1224080C
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- floating grid
- clearance wall
- silicon nitride
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Abstract
The present invention relates to a floating grid making method in a flash memory. The present invention comprises that the present invention provides a basement; a gate oxide layer, a polycrystalline silicon layer and a silicon nitride layer are formed on the basement; the position of a gate is defined, and the silicon nitride layer above the gate is removed; the exposed polycrystalline silicon layer is oxidized to form a floating gate oxide layer; a buffering layer is formed to cover on the silicon nitride layer and the floating gate oxide layer; a first gap wall is formed on the side wall of the buffering layer, and then, the second gap wall is formed; the second gap wall is used as a cover curtain, and the floating gate oxide layer which is not covered by the second gap wall is removed; the buffering layer above the polycrystalline silicon layer and the floating gate oxide layer, the first gap wall and the second gap wall are removed; the polycrystalline silicon layer which is not covered by the floating gate oxide layer is removed. Then, the making process of the floating gate is completed.
Description
The invention relates to a kind of manufacture method of flash memory, particularly about the manufacture method of floating grid in a kind of flash memory.
Nonvolatile memory has been applied in the use of various electronic building bricks, as memory structure data, program data and other can repeated access data.But and on the program non-volatile internal memory, emphasize especially recently and can remove and programmable read only memory (EEPROMs) by electricity, its be in the personal computer with the memory subassembly of the extensive employing of electronic equipment institute.Traditional can electricity removing and programmable read only memory system finishes with floating grid (floating gate) transistor arrangement, it has the advantage that can write, can erase and can preserve data, but the slower shortcoming of access speed is also arranged.Yet can removing and programmable read only memory by electricity of the flash memory structure of development had access speed faster recently.
The flash memory cell of general flash memory has two grid structures, and one is floating grid, and another is the control grid.Floating grid is used for store charge, the control grid then is used for the control data access, wherein control grid then usually and word line join, and floating grid is positioned at control grid below, it is in floating state usually, do not join, and can roughly be divided into two kinds of stacking-type and separable grids by the position that forms of control grid with any circuit.
The channel of known separable grid flash memory comprises two parts, and one is control grid channel, and one is the floating grid channel, controls the on off state of this mnemon by both.Control grid in the separable grid flash memory only part is covered on the floating grid, owing to have a coupling coefficient (coupling ratio, α between control grid and the floating grid
CF), in order to increase the coupling coefficient between control grid and the floating grid, avoid error to accuracy to cause not being subjected to active region that floating grid contains after the control grid forms simultaneously, form the conducting between source electrode, the drain electrode, therefore the both sides of floating grid can cover the partial separating zone territory usually, with the coupling coefficient between increasing, and guarantee that active region is covered fully by floating grid.
Fig. 1 to Fig. 7 is the making flow chart of floating grid in the known flash memory.At first please be earlier with reference to Fig. 1, one substrate 100 is provided, form one deck gate oxide 104 in the active region in this substrate 100, on gate oxide 104, form again one deck the polysilicon layer 106 of overdoping with material as floating grid, after forming polysilicon layer 106, then forming one deck first silicon nitride layer 108 is covered on the polysilicon layer 106, if will obtain the floating grid that width is 3000 , then the thickness of first silicon nitride layer 108 need be slightly larger than 3000 , last be covered on first silicon nitride layer 108 with the photoresist 110 of a patterning again, to define the position of floating grid.
Then please refer to Fig. 2, this substrate 100 has isolation structure of shallow trench 102, in order to define active region.And after defining the position of floating grid, first silicon nitride layer 108 that not covered by photoresist 110 is removed till the exposed polysilicon layer 106, polysilicon layer 106 oxidations that then will expose, to form floating grid oxide layer 112, because both sides are near the oxidation of the polysilicon layer 106 of first silicon nitride layer 108, can be suppressed by first silicon nitride layer 108, therefore formed floating grid oxide layer 112 can present the shape of beak at the edge.
Then please refer to Fig. 3, then deposited silicon nitride layer is covered on first silicon nitride layer 108 and the floating grid oxide layer 112, carrying out being etched back to of this silicon nitride layer again exposes till the silicon nitride layer 108, to form first clearance wall 114 between the sidewall of first silicon nitride layer 108 and the floating grid oxide layer 112, because the relation of etch-back, first clearance wall 114 only covers part floating grid oxide layer 112, the part that both sides are covered by first clearance wall 114 is the width of floating grid, be mask with first clearance wall 114 more afterwards, the floating grid oxide layer 112 that not covered by first clearance wall 114 is removed till expose polysilicon layer 106, and floating grid oxide layer 112 is divided into two parts.
Then please refer to Fig. 4 and Fig. 5, after floating grid oxide layer 112 is divided into two parts, first silicon nitride layer 108 and first clearance wall 114 are removed till the polysilicon layer 106 and the floating grid oxide layer 112 that expose under it, then forming one deck second silicon nitride layer 116 is covered on polysilicon layer 106 and the floating grid oxide layer 112, photoresist layer with one deck patterning is covered on second silicon nitride layer 116 again, and second silicon nitride layer 116 that not covered by photoresist removes, the shape of formed second silicon nitride layer 116 and position divest photoresist as shown in Figure 4 at last again.
Then please refer to Fig. 5, deposited silicon nitride layer is covered on second silicon nitride layer 116 and the floating grid oxide layer 112, carrying out being etched back to of this silicon nitride layer again exposes till second silicon nitride layer 116 and the floating grid oxide layer 112, to form second clearance wall 118a and the 108b on the sidewall of the sidewall of second silicon nitride layer 116 and floating grid oxide layer 112, wherein the second clearance wall 118a is formed on the sidewall of second silicon nitride layer 116, and the second clearance wall 108b is formed on the sidewall of floating grid oxide layer 112 inboards, as shown in Figure 5.
The thickness and the position of above-mentioned formation second silicon nitride layer 116 will directly have influence on the shallow trench isolation region whether formed second clearance wall 118a can contain part.And the floating grid side that the function of the second clearance wall 118a is to make formation is on isolation structure of shallow trench 102, with the source electrode of effectively avoiding follow-up formation, the conducting between the drain electrode.Wherein, source electrode, drain electrode and operate by the channel under floating grid, the control grid in successive process will be formed at active region between the isolation structure of shallow trench 102.In addition, also can be between two floating grids because of the little at interval pattern dimension (feature size) of the second clearance wall 118a, to reach higher integration.
Please refer to Fig. 6 and Fig. 7 at last, after forming second clearance wall 118, be mask with second clearance wall 118 again, the floating grid oxide layer 112 that not covered by the second clearance wall 118a and 108b is removed, second silicon nitride layer 116 and the second clearance wall 118a, the 118b that then will be all the silicon nitride material remove, be mask with floating grid oxide layer 112 more at last, the polysilicon layer 106 that is not subjected to floating grid oxide layer 112 overlay areas is removed till expose gate oxide 104, promptly finish the making of floating grid in the flash memory.
The above-mentioned second clearance wall 118a that is formed on second silicon nitride layer, 116 sidewalls can protect the floating grid oxide layer 112 under it not to be removed, and makes that the side of formed floating grid can be on shallow trench isolation 102.And the side of floating grid oxide layer 112 is on shallow trench isolation, not only can increase between floating grid and the control grid contact area and then increase coupling coefficient between the two, can avoid error in addition to accuracy (Align Accuracy), cause not being subjected to active region that floating grid contains after the control grid forms, form the conducting between source electrode, the drain electrode.
The side of the floating grid oxide layer that forms in known can be on shallow trench isolation, though can effectively avoid the conducting between source electrode, the drain electrode, but, cause making difficult, cost increase because the processing procedure of the clearance wall of the floating grid of this kind of formation shape and sidewall is too numerous and diverse.
In known if will obtain the floating grid that width is 3000 , then the thickness of first silicon nitride layer need be slightly larger than 3000 , because first clearance wall is formed on the sidewall of first silicon nitride layer, so the thickness of first clearance wall also can be greater than 3000 , the first so thick clearance wall not only can cause particle contamination (particle contamination) when deposition, and also has the shortcoming that divests overlong time when divesting.
The present invention proposes a kind of floating grid manufacture method of utilizing resilient coating, first clearance wall and second clearance wall, with solve above-mentioned known in the blocked up shortcoming of first clearance wall.
The present invention proposes a kind of method, is summarized as follows:
One substrate is provided, in substrate, form gate oxide, polysilicon layer and silicon nitride layer, then define the position of grid, the silicon nitride layer of grid top is removed, the polysilicon layer oxidation that will expose afterwards is to form the floating grid oxide layer, then forming resilient coating is covered on silicon nitride layer and the floating grid oxide layer, form the sidewall of first clearance wall again in resilient coating, form second clearance wall afterwards again, and be that the floating grid oxide layer that mask will not be covered by second clearance wall will remove with second clearance wall, then again with the resilient coating above polysilicon layer and the floating grid oxide layer, first clearance wall and second clearance wall divest, the polysilicon layer that not covered by the floating grid oxide layer removes, and promptly finishes the making of floating grid in the flash memory.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate institute's accompanying drawing to elaborate:
The drawing explanation:
Fig. 1 to Fig. 7 is the making flow chart for floating grid in the known flash memory.
Fig. 8 to Figure 14 is the making flow chart according to one of floating grid preferred embodiment in the flash memory of the present invention.
Description of reference numerals:
100,200 substrates
102 isolation structure of shallow trench
104,204 gate oxides
106,206 polysilicon layers
108,208 first silicon nitride layers
110,210 photoresist layers
112,212 floating grid oxide layers
114,216 first clearance walls
116 second silicon nitride layers
118a, 118b second clearance wall
202 area of isolation
214 resilient coatings
218 photoresist layers
220 second clearance walls
At first please be earlier with reference to Fig. 8, one substrate 200 is provided, this substrate 200 has active region and isolated area, form one deck gate oxide 204 in the active region in this substrate 200, on gate oxide 204, form again one deck the polysilicon layer 206 of overdoping with material as floating grid, after forming polysilicon layer 206, then forming one deck first silicon nitride layer 208 is covered on the polysilicon layer 206, last be covered on first silicon nitride layer 208 with the photoresist 210 of a patterning again, to define the position of floating grid.
Then with reference to Fig. 9, wherein substrate 200 has area of isolation 202 for example for isolation structure of shallow trench, in order to define active region.After defining the position of floating grid, first silicon nitride layer 208 that not covered by photoresist 210 is removed till the exposed polysilicon layer 206, polysilicon layer 206 oxidations that then will expose, to form floating grid oxide layer 212, because both sides are near the oxidation of the polysilicon layer 206 of first silicon nitride layer 208, can be suppressed by first silicon nitride layer 208, therefore formed floating grid oxide layer 212 can present the shape of beak in edge.
Then please refer to Figure 10, then forming a resilient coating 214 is covered on first silicon nitride layer 208 and the floating grid oxide layer 212, the material of this resilient coating 214 for example is a polysilicon, then form first clearance wall 216 again on the sidewall of resilient coating 214, the method that this first clearance wall 216 forms for example is covered on the resilient coating 214 for forming silicon nitride layer in low-pressure chemical vapor deposition (LPCVD) mode, then carry out the etch-back step of this silicon nitride layer again, the silicon nitride layer that forms is removed till expose resilient coating 214, to form first clearance wall 216.
Then please refer to Figure 11, after forming first clearance wall 214, then resilient coating 214 is removed till expose first silicon nitride layer 208 and floating grid oxide layer 212, and still have the resilient coating 214 of part above floating grid oxide layer 212 both sides with below first clearance wall 216.
Then please refer to Figure 12, then be covered on first clearance wall, resilient coating 214 and first silicon nitride layer 208 of the top of substrate 200 active regions with a patterned photoresist 218, the area that this photoresist 218 covers is less than active region, and and shallow trench isolation between a minimum distance is arranged.Not removed by first clearance wall 216, resilient coating 214 and first silicon nitride layer 208 of top, photoresist 218 overlay areas (active region of area of isolation and minimum part).
Then please refer to Figure 13, then photoresist 218 is removed, form second clearance wall 220 afterwards again in first clearance wall 216, on the sidewall of the resilient coating 214 and first silicon nitride layer 208, the method that second clearance wall 220 forms for example is covered in first clearance wall 216 for forming silicon nitride layer in low-pressure chemical vapor deposition (LPCVD) mode, on the resilient coating 214 and first silicon nitride layer 208, then carry out the etch-back step of this silicon nitride layer again, the silicon nitride layer that forms is removed till expose the floating grid oxide layer 212 and first silicon nitride layer 208, to form second clearance wall 220, after forming second clearance wall 220, with second clearance wall 220 is mask, and the floating grid oxide layer 212 that not covered by second clearance wall 220 is removed till expose polysilicon layer 206.
The purpose that above-mentioned second clearance wall 220 forms, with known in first clearance wall 114, the function of the second clearance wall 118a is identical, but second clearance wall 220 can reach simultaneously known in the effect of first clearance wall 114 and the second clearance wall 118a, the function of the wherein known second clearance wall 118a is to make the floating grid side of formation on shallow trench isolation, can effectively avoid source electrode, conducting between the drain electrode, simultaneously also can on business know the second clearance wall 118a between two floating grids and have less than between the pattern dimension every, reaching higher positive degree, and also this effect of second clearance wall 220 among the present invention.
Please refer to Figure 14 at last, then in regular turn second clearance wall 220, first silicon nitride layer 208, the resilient coating 214 of floating grid oxide layer 212 with polysilicon layer 206 tops divested, the last polysilicon layer 206 that not covered by floating grid oxide layer 216 removes till expose gate oxide 204, promptly finishes the making of floating grid in the flash memory.
Of the present invention be characterized as the idea of utilizing resilient coating will be known between the definition floating grid width crack wall thickness reduce, can cause particle contamination and clearance wall to divest the shortcoming of overlong time to reduce known intermediate gap wall when the deposition.
The purpose that second clearance wall 220 forms among the present invention, with known in the function of first clearance wall 114, the second clearance wall 118a identical, can make have between two floating grids less than between the pattern dimension every, to improve positive degree.But second clearance wall 220 among the present invention can reach simultaneously with known in first clearance wall 114 and the identical effect of the second clearance wall 118a, reduced the complexity of processing procedure.
The present invention utilizes resilient coating, first clearance wall and second clearance wall, can effectively solve the blocked up shortcoming of known first clearance wall, has also effectively improved the complexity of processing procedure simultaneously.
Though the present invention discloses with a preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this operator, without departing from the spirit and scope of the present invention; when can doing various changes and retouching, so protection scope of the present invention is as the criterion when defining with claims scope.
Claims (7)
1, the manufacture method of floating grid in a kind of flash memory, it is characterized in that: it comprises at least:
One substrate is provided, has an active region and an area of isolation in the substrate;
Form a tunnel oxide, a polysilicon layer and a silicon nitride layer in substrate;
Define an aperture position, the silicon nitride layer on the aperture position is removed, and with the polysilicon layer oxidation that exposes, to form a floating grid oxide layer;
In substrate, form a resilient coating;
Sidewall in resilient coating forms first clearance wall, and not removed by the resilient coating of first clearance wall;
First clearance wall, resilient coating and silicon nitride layer beyond the active region top are removed;
Form the sidewall of second clearance wall in first clearance wall, resilient coating and silicon nitride layer;
The floating grid oxide layer that not covered by second clearance wall is removed;
Second clearance wall and resilient coating are removed; And
The polysilicon layer that not covered by the floating grid oxide layer is removed, to form a floating grid.
2, the manufacture method of floating grid in the flash memory according to claim 1, it is characterized in that: wherein the material of resilient coating comprises polysilicon.
3, the manufacture method of floating grid in the flash memory according to claim 1, it is characterized in that: wherein the material of resilient coating comprises silicon nitride.
4, the manufacture method of floating grid in the flash memory according to claim 1, it is characterized in that: wherein the material of first clearance wall comprises silicon nitride.
5, the manufacture method of floating grid in the flash memory according to claim 1, it is characterized in that: wherein the material of second clearance wall comprises silicon nitride.
6, the manufacture method of floating grid in the flash memory according to claim 1, wherein the thickness of resilient coating is lower than 3000 .
7, the manufacture method of floating grid in the flash memory according to claim 1, wherein the thickness of first clearance wall is lower than 3000 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01109538 CN1224080C (en) | 2001-03-30 | 2001-03-30 | Method for producing floating grid in flash memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01109538 CN1224080C (en) | 2001-03-30 | 2001-03-30 | Method for producing floating grid in flash memory |
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| Publication Number | Publication Date |
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| CN1378242A CN1378242A (en) | 2002-11-06 |
| CN1224080C true CN1224080C (en) | 2005-10-19 |
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| CN 01109538 Expired - Fee Related CN1224080C (en) | 2001-03-30 | 2001-03-30 | Method for producing floating grid in flash memory |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100784083B1 (en) * | 2005-06-13 | 2007-12-10 | 주식회사 하이닉스반도체 | Method for manufacturing floating gate of flash memory device |
| CN103050380B (en) * | 2012-12-20 | 2016-09-07 | 上海华虹宏力半导体制造有限公司 | The forming method of semiconductor device |
| CN103066025B (en) * | 2012-12-26 | 2017-02-08 | 上海华虹宏力半导体制造有限公司 | Method for coupling of top source line of separating grid flash memory |
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