CN1169211C - Process for preparing flash memory - Google Patents

Abstract

The present invention relates to a flash memory preparing method. The present invention provides a basement, wherein a plurality of floating grid structures are formed on the basement; floating grids are covered by dielectric layers, spaces among the floating grids are primarily used as presetting positions of a source electrode or a drain electrode and channels of control grids; polycrystalline silicon layers are formed to cover on the dielectric layers and the floating grids, and top cover layers and cushioning layers are orderly formed to cover on the polycrystalline silicon layers. Larger spaces are formed among the floating grids, obvious concave points are generated by the covering of the layers, and the concave points can automatically align the center points of the larger spaces and make the length of channels of the reserved control grids at both sides consistent. A plurality of micro-images and etching manufacturing processes simultaneously form positions of the control grids, the drain electrode and the source electrode.

Description

Flash memory making method

Technical field

The invention relates to a kind of flash memory making method, particularly about aiming at the manufacture method of drain electrode, the flash memory that has identical control grid channel length with formation in a kind of flash memory voluntarily.

Background technology

Nonvolatile memory has been applied in the use of various electronic building bricks, as memory structure data, program data and other can repeated access data.But and on the program nonvolatile memory, emphasize especially recently and can remove and programmable read only memory (EEPROMs) by electricity, its be in the personal computer with the memory subassembly of the extensive employing of electronic equipment institute.Traditional can electricity removing and programmable read only memory system finishes with floating gate (floating gate) transistor arrangement, it has the advantage that can write, can erase and can preserve data, but the slower shortcoming of access speed is also arranged.Yet can removing and programmable read only memory by electricity of the flash memory structure of development had access speed faster recently.

With flash memory, flash memory in the access data, for example can electricity than the nonvolatile memory of any other kind remove and programmable read only memory in reading and write operation, have advanced usefulness performance.The high speed operation benefit of flash memory has been considered to be highly suitable for Portable calculation element, cellular telephone or digital stillcamera etc.In general, flash memory comprises two kinds, for example its mnemon series connection drain electrode of NAND type, and the drain electrode in parallel of its mnemon of NOR type.As called optical imaging, NOR type flash memory has more competition speed in data access, makes the NOR type more favourable in the high frequency memory system than NAND type.

Usually the flash memory cell of flash memory has two grid structures, and one is floating grid, and another is the control grid.Floating grid is used for store charge, the control grid then is used for the control data access, wherein floating grid is positioned at control grid below, it is in the state of " floating " usually, do not join with any circuit, the control grid then usually joins with character line, and can roughly be divided into two kinds of stacking-type and separable grids because of the position of control grid formation.

Generally be known in when making the separable grid flash memory, respectively with the material of two-layer polysilicon layer as floating grid and control grid, because the channel of separable grid flash memory is made up of two parts, one is that control grid channel, is the floating grid channel, wherein the length of floating grid channel is quite fixing usually, and the control grid under control grid channel length, determined the electrical performance of this flash memory and the size of the assembly of producing usually.

Fig. 1 to Fig. 7 is the making flow chart of known separable grid flash memory.

At first please be earlier with reference to Fig. 1, substrate 100 with isolation structure of shallow trench 101 (please refer to Fig. 4) is provided, in this substrate 100, form one deck lock oxide layer 102, on lock oxide layer 102, form again one deck first polysilicon layer 104 of overdoping with material as floating grid 114 (please refer to Fig. 5), after forming first polysilicon layer 104, then form one deck silicon nitride layer 106 on first polysilicon layer 104.

Then please refer to Fig. 2, is mask with photoresist layer 108, and the silicon nitride layer 106 that is not subjected to photoresist layer 108 protection is removed till expose first polysilicon layer 104.

Then please refer to Fig. 3, after silicon nitride layer 106 removes, photoresist layer 108 is divested, be mask then with silicon nitride layer 106, first polysilicon layer 104 that will expose is oxidized to polysilicon oxide layer (poly-oxide) 112, because the cause of silicon nitride layer 106, first polysilicon layer 104 can be suppressed in the oxidation of both sides, therefore causes occurring near the polysilicon oxide layer 112 of silicon nitride layer 106 both sides the shape of most advanced and sophisticated (peak).

Then please refer to Fig. 4, Fig. 4 is the IV-IV section among Fig. 3, can find out that by the IV-IV section substrate 100 has isolation structure of shallow trench 101, then the polysilicon oxide layer 112 of isolation structure of shallow trench 101 tops is removed till expose first polysilicon layer 104, make polysilicon oxide layer 112 be separated into several parts.

Then please refer to Fig. 5, silicon nitride layer 106 is removed, is mask with polysilicon oxide layer 112 again, first polysilicon layer 104 beyond polysilicon oxide layer 112 belows is removed till expose lock oxide layer 102, to form floating grid 114.

Then please refer to Fig. 6, after floating grid 114 forms, on floating grid 114, form one dielectric layer 116, one deck second polysilicon layer 118 and one deck top cover silicon nitride layer 120 in regular turn, last is being mask with a patterned photoresistance 122, define the width of second polysilicon layer 118, the width of this second polysilicon layer 118 has direct influence to the length of control grid channel.According to above-mentioned, the length of control grid channel can be subjected to the influence of component design rule (design rule).In addition, because control grid channel can be formed at the substrate 100 of second polysilicon layer 118 and lock oxide layer 102 contact positions below, therefore the mis-alignment (misalignment) of known micro-photographing process will directly have influence on the length of control grid channel.The length of control grid channel is because the mis-alignment of simultaneously limited component design rule and known micro-photographing process, so the length of control grid channel is can be because of the deviation of aiming at elongated or shorten, therefore can't reach consistent control grid channel length.

Please refer to Fig. 7 at last, is that mask carries out source electrode 124 and 126 the ion implantation step of draining with photoresistance 122 equally, carries out tempering step at last, to form the shallow junction of source electrode, drain electrode.

The influence of mis-alignment when the length of known control grid channel can be subjected to component design rule and known micro-photographing process simultaneously, therefore controlling the length of grid channel can difficultly control, under or the situation about shortening difficult and elongated in the length control of control grid channel, make that the control grid channel length of the assembly of producing is inconsistent, thereby different electrical performance is arranged.

Known because the definition of control grid has the puzzlement of mis-alignment, so make its processing procedure nargin (process window) become very little.

The general known manufacture method that other is still arranged, 126 definition together for example just will drain when definition floating grid 114, but because successive process still must be through high tempering step repeatedly, can make that the implanting ions of drain electrode 126 spreads in substrate, wherein the diffusion on the horizontal direction will cause the shortening of control grid channel length, influence the electrical performance of product, and the diffusion on the vertical direction can cause and can't form shallow junction, not meet the requirement of processing procedure now.

Summary of the invention

The present invention proposes the method that a kind of drain electrode is aimed at voluntarily, utilizes the aligning voluntarily of drain locations, and the length of control grid channel can not changed to some extent because of the mis-alignment deviation of micro-photographing process, has consistency.

A kind of method that the present invention proposes is summarized as follows: a substrate is provided, in substrate, form several floating grid structures, two floating grid substrates of below at interval, may be defined as source electrode or drain electrode and control grid channel region, wherein than the substrate of wide interval below as drain electrode and control grid channel, and the substrate of below, narrower interval is as source electrode, then form a dielectric layer on the sidewall of substrate and floating grid, forming polysilicon layer again is covered on dielectric layer and the floating grid, forming cap layer and resilient coating afterwards more in regular turn is covered on the polysilicon layer, wherein the interval that width is bigger is because the covering of above-mentioned multilayer, can above the interval, produce the less recess (recess) of first width, can be with this recess voluntarily in alignment with centre (i.e. Lou Ji precalculated position) at interval, afterwards again with several little shadow, etch process forms the control grid, promptly finishes the making of assembly.

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperation institute accompanying drawing elaborate:

Description of drawings

Fig. 1 to Fig. 7 is the making flow chart of known separable grid flash memory.

Fig. 8 to Figure 14 is the making flow chart according to the separable grid flash memory of preferred embodiment of the present invention.

Description of reference numerals:

100 substrates

101 isolation structure of shallow trench

102 lock oxide layers

104 first polysilicon layers

106 silicon nitride layers

108 photoresistances

110 openings

112 polysilicon oxide layers

114 floating grids

116 dielectric layers

118 second polysilicon layers

120 top cover silicon nitride layers

122 photoresist layers

124 source electrodes

126 drain electrodes

200 substrates

202a, 202b, 202c, 202d floating grid

204, the narrower interval of width between 202b, the 202c

206, the interval of wider width between 202a, the 202b

208 dielectric layers

210 polysilicon layers

212 cap layers

214 resilient coatings

216 recess

218 silicon nitride layers

220 polysilicon oxide layers

221 hatch frames

222 photoresist layers

224 control grids

226 predetermined drain locations

228 predetermined source electrode positions

230 expectant control grid channel length

Embodiment

Fig. 8 to Figure 14 is the making flow process profile according to the separable grid flash memory of preferred embodiment of the present invention.

At first please be earlier with reference to Fig. 8, one substrate 200 is provided, in substrate 200, form several floating grid structures 202a, 202b, 202c and 202d, wherein, between floating grid 202b, 202c, form the interval (gap) 204 of broad, and substrate 200 parts below interval 204 are predefined for follow-up formation drain electrode and the zone of controlling the grid channel.Narrower interval 206 between floating grid 202a, 202b and 202c, 202d, substrate 200 parts of its below are predefined for the zone of follow-up formation source electrode.

Please refer to Fig. 8 equally, floating grid structure 202a, 202b, 202c and 202d be by a dielectric layer 208 coat and and external insulation, this dielectric layer 208 for example is with low-pressure chemical vapor deposition mode (LPCVD) deposition layer of silicon dioxide, then forming polysilicon layer 210 again is covered on dielectric layer 208 and floating grid 202a, 202b, 202c and the 202d, forming first cap layer 212 afterwards more in regular turn is covered on the polysilicon layer 210 with resilient coating 214, the material of this first cap layer 212 is a silicon nitride for example, and the material of resilient coating 214 for example is a polysilicon.Wherein, the interval 204 that width is bigger is because the covering of above-mentioned polysilicon layer 210, first cap layer 212 and resilient coating 214, can produce a tangible recess 216 above interval 204, this recess 216 can be voluntarily in alignment with the central authorities at interval 204, the precalculated position of promptly follow-up formation drain electrode.And the depression of narrower 206 tops, interval is more not obvious.

Emphasize in the present embodiment recess 216 can be voluntarily in alignment with 204 central authorities at interval, the promptly so-called precalculated position that drains, drain electrode 226 both sides, precalculated position are then for controlling the precalculated position of grid channel, because recess 216 is the central authorities of alignment spaces 204 voluntarily, the length in reserve of the both sides that therefore drain (control grid channel length) also can be consistent.

Then please refer to Fig. 9, form one deck second cap layer 218 on resilient coating 214, the material of this second cap layer 218 for example is a silicon nitride, afterwards with second cap layer, 218 etch-back, second cap layer 218 of recess 216 parts is stayed, and other parts comprise that second cap layer 218 of 206 tops all is removed at interval.Because the depression of 206 tops is not obvious at interval, therefore, only second cap layer, 218 reservations with recess 216 parts are easy to reach.

As for second cap layer 218 of recess 216 parts shared width, only relevant with the width of follow-up formation drain electrode contact (drain contact), can't have influence on the consistency of control grid channel length in the assembly, that is to say, as long as recess 216, promptly can reach the purpose of both sides control grid channel length unanimity in alignment with the centre at interval 204.

Then please refer to Figure 10, with the recess 216 second residual cap layers 218 is mask, with resilient coating 214 oxidations that not covered by second cap layer 218, form polysilicon oxide layer 220 (poly-oxide) after resilient coating 214 oxidations, be mask with polysilicon oxide layer 220 more then, second cap layer 218 of recess 216 belows and not oxidized resilient coating 214 are removed fully, and to form a hatch frame 221, the position of this hatch frame 221 also can be in alignment with the position of drain electrode.

In above-mentioned Figure 10, with second cap layer 218 is mask, form the method for polysilicon oxide layer 220, can also replace by other method, for example in Fig. 8, do not form second cap layer 218 on resilient coating 214, and adopt the oxonium ion of wide-angle to be implanted in the resilient coating 214, because the relation of implant angle, oxonium ion also can't effectively be implanted in the sunk area 216 in the middle of the resilient coating 214, so it is follow-up when carrying out high-temperature oxydation, intermediate recess place 216 can't be oxidized, can reach drain electrode same as described above alignment result voluntarily.

Then please refer to Figure 11, be covered on expectant control grid and the drain locations through the photoresistance 222 of patterning, the polysilicon oxide layer 220 that not protected by photoresistance 222 is removed till first cap layer 212 that exposes under it with one.

Then please refer to Figure 12, after polysilicon oxide layer 220 removes, photoresistance 222 is divested, and first cap layer 212 that not covered by polysilicon oxide layer 220 removes till expose polysilicon layer 210.

Then please refer to Figure 13, after first cap layer 212 removes, polysilicon oxide layer 220 is removed, and polysilicon oxide layer 220 can expose shape after removing just like the not oxidation buffer layer 214 as the wedge angle.

Please refer to Figure 14 at last, the not oxidation buffer layer 214 that will expose removes with the polysilicon layer 210 that not covered by first cap layer 212, promptly form control grid 224, and two control grids 224 between the position that exposed be the precalculated position 226 of drain electrode, the position then is the precalculated position 228 of source electrode, length in 226 both sides, precalculated position that drain can be consistent, and this length is equivalent to control grid channel length 230.Processing procedure afterwards, for example in the precalculated position 226 of source electrode, drain electrode precalculated position 228 carries out the implantation step of source electrode, drain region, forms source electrode, drain electrode contact (S/D contact) belongs to emphasis of the present invention, do not give unnecessary details so do not add.

Therefore, the aligning voluntarily that utilizes drain locations that is characterized as of the present invention can make the control grid channel length unanimity in each assembly.

The present invention emphasizes the recess central authorities of alignment spaces voluntarily, i.e. Lou Ji precalculated position, to reach the purpose of drain electrode both sides, precalculated position length unanimity, as for recess shared width only forms drain electrode to contact the width of (drain contact) relevant with follow-up, can't have influence on the consistency of controlling the grid channel length in the assembly.

The recess central authorities of alignment spaces voluntarily among the present invention, i.e. Lou Ji precalculated position is so there is preferable processing procedure nargin.

The present invention can solve the change that known mis-alignment because of micro-photographing process causes control grid channel length effectively, and drain locations of the present invention is for aiming at voluntarily, and the length of therefore controlling the grid channel can not be subjected to the influence of micro-photographing process mis-alignment.

Though the present invention discloses as above with a preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this operator, without departing from the spirit and scope of the present invention; when can doing various changes and retouching, so protection scope of the present invention is as the criterion when defining with claims scope.

Claims (11)

1, a kind of flash memory making method, it is characterized in that: it comprises at least:

One substrate is provided, and wherein substrate has a plurality of floating grids, and between these floating grids respectively separately with first width and second width;

Form a polysilicon layer, a cap layer and a resilient coating in this substrate, wherein this resilient coating of this first width top has a tangible recess;

Carry out the oxonium ion of a wide-angle and implant,, and carry out a tempering step, beyond this recess, to form an oxidation buffer layer the resilient coating oxidation with the resilient coating of oxonium ion cloth value beyond recess;

This cap layer and resilient coating that not oxidated resilient coating is covered remove, to form a hatch frame; And

The position of definition one control grid, and oxidation buffer layer, a cap layer and the polysilicon layer that will control beyond the gate location remove, the oxidation buffer layer that will control the grid top again removes, to form the control grid simultaneously and the contact position that drains.

2, flash memory making method according to claim 1 is characterized in that: wherein the material of cap layer is a silicon nitride.

3, flash memory making method according to claim 1 is characterized in that: wherein the resilient coating material is a polysilicon.

4, flash memory making method according to claim 1 is characterized in that: wherein hatch frame is aimed at the middle position of first width interval voluntarily.

5, flash memory making method according to claim 1 is characterized in that: wherein first width is greater than second width.

6, a kind of flash memory making method, it is characterized in that: it comprises at least:

One substrate is provided, and wherein substrate has a plurality of floating grids, and between these floating grids respectively separately with first width and second width;

Form a polysilicon layer, one first cap layer and a resilient coating in this substrate, wherein the resilient coating of first width top has a tangible recess;

Form one second cap layer on this resilient coating, and carry out the etch-back of second cap layer, make residual second cap layer in the recess, and with the resilient coating oxidation beyond the recess, to form an oxidation buffer layer;

Second cap layer and the resilient coating that not covered by this oxidation buffer layer are removed, to form a hatch frame; And

The position of definition one control grid, and oxidation buffer layer, first cap layer and the polysilicon layer that will control beyond the gate location remove, this oxidation buffer layer that will control again above the grid removes, and controls grid and a contact position that drains to form one simultaneously.

7, flash memory making method according to claim 6 is characterized in that: wherein the material of first cap layer is a silicon nitride.

8, flash memory making method according to claim 6 is characterized in that: wherein the material of second cap layer is a silicon nitride.

9, flash memory making method according to claim 6 is characterized in that: wherein the resilient coating material is a polysilicon.

10, flash memory making method according to claim 6 is characterized in that: wherein hatch frame is aimed at the middle position of first width interval voluntarily.

11, flash memory making method according to claim 6 is characterized in that: wherein this hatch frame is aimed at the middle position of first width interval voluntarily.

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