CN1298026C - Method for modifying formation procedure for fabricating cumulate texture of controlling grid of flash memory - Google Patents
Method for modifying formation procedure for fabricating cumulate texture of controlling grid of flash memory Download PDFInfo
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- CN1298026C CN1298026C CNB2003101082778A CN200310108277A CN1298026C CN 1298026 C CN1298026 C CN 1298026C CN B2003101082778 A CNB2003101082778 A CN B2003101082778A CN 200310108277 A CN200310108277 A CN 200310108277A CN 1298026 C CN1298026 C CN 1298026C
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Abstract
The present invention belongs to the technical field of an integrated circuit manufacturing technology, which more specifically relates to an improving technology for manufacturing a flash memory (FLASH) control grid stacking structure. In the partial overlapped manufacturing technology of a double-gate flash memory, the technology for forming the control grid stacking structure comprises the following steps: carrying out second tunnel grid oxidation after a floating grid is formed; then respectively depositing a polysilicon layer and a tungsten silicide layer; finally depositing an oxide film layer. The technology has many disadvantages. The present invention provides a novel improving technology for forming a control grid stacking structure, and no oxide film layer is deposited after the deposition of the polysilicon and the tungsten silicide film. Only a dry etching step is required, and technology complexity and production cost are reduced. In order to improve the quality of second tunnel grid oxidation, NO gas is used to carry out high-temperature annealing, and the present invention has the advantages of yield improvement and high reliability.
Description
Technical field
The invention belongs to field of IC technique, be specifically related to a kind of flash memory (FLASH) control gate packed structures formation improved technological process that is used to make.
Background technology
Memory not only is applied to all kinds electronic digital computer, becomes one of chief component of computer, also is widely used in other electronic technology fields.For a long time, digital computer uses magnetic core as memory cell.Development along with computing technique can not adapt to various requirement at aspect magnetic cores such as performance and production efficiencys.Succeeding in developing and a large amount of production of semiconductor memory promoted the development of computer greatly.Because metal-oxide-semiconductor memory has remarkable advantage in high density, big capacity and low-power consumption, aspect low-cost, its dominate always in semiconductor memory.Along with developing rapidly of new technology, new technology, metal-oxide-semiconductor memory also improves constantly on speed, and particularly aspect the The Study of Non-Volatile Memory exploitation, metal-oxide-semiconductor memory has also been obtained remarkable progress.So metal-oxide-semiconductor memory has formed new technical field in the electronics along with its development is increasingly mature, become an importance extensive, very lagre scale integrated circuit (VLSIC).
Memory can be divided into two big classes by its function: random-access memory (ram) and nonvolatile memory (NVM).The RAM random access memory can be divided into two kinds of dynamic random access memory (DRAM) and static RAMs (SRAM).Nonvolatile memory can be divided into magnetizing mediums and light medium memory device, ferroelectric memory (FRAM), magnetic memory (MRAM) and semiconductor N VM nonvolatile memory again.
But semiconductor N VM nonvolatile memory can be divided into the read only memory (ROM), the programmable type read only memory (PROM) again the erasing type read only memory (EPROM), the electrically rewritable type read only memory (EEPROM) and flash memory (Flash) etc.Semiconductor N VM nonvolatile memory is compared with the RAM random access memory, and great advantage is to have not need can keep data for a long time under the electric consumption situation, promptly has the characteristics of energy savings.
Now, semiconductor N VM nonvolatile memory has been widely used in the extensive use of many electronic products, particularly flash memory.For example, MP3 player, digital camera, DVD ROM driver, CD-RW/DVD driver, CDROM drive, usb driver, PC BIOS, network interface unit/product, cable modem, Smart Card smart card, PDA, hard disk drive, video-game, video mobile phone, mobile phone, ADSL, Digital Television are set-top box etc.
As everybody knows, eprom memory grows up on ROM read only memory basis.
EPROM structure Transistor Cell is seen shown in Figure 1.It has two overlapped polysilicon gates, and following grid and external insulation are called floating boom, play stored charge.Top grid are connected with the X decoder, are called control gate, play device cell gating and control action, have therefore just saved a control MOS transistor and have constituted Transistor Cell.When control gate and leakage are zero potential, there is not electric charge on the floating boom.When control gate and leakage are positive potential, the channel region conducting, hot electron is injected in the floating boom by means of the potential difference between floating boom and raceway groove and goes, and floating boom forms negative electrical charge, realizes that programming promptly writes task.As seen, the electronics in the floating boom injects by " channel hot electron injection " and finishes.So-called channel hot electron injects, be exactly leak and the source between sufficiently high electric field in addition, make electronics be quickened to become hot electron, when energy surpasses silicon dioxide and silicon interface barrier height, directly be injected in the floating boom from raceway groove by means of the additional positive voltage on the control gate and go by electric field.This process is commonly referred to the channel hot electron injection programming and promptly writes.
According to the electric charge that has or not in the floating boom, cause the control gate threshold voltage to change and represent different storage data, thereby realize the reading and writing two states.We wish to be injected into the electric charge in the floating boom, can keep muchly before wiping.But electric leakage in the actual process and Fowler-Nordheim (F-N) tunnel effect can make electronics reduce gradually.
The electric charge of wiping in the floating boom must be used UV ultraviolet light method.It is to make in the floating boom electronics obtain energy from light quantum that ultraviolet light is wiped, and is to enter silicon dioxide to surpass silicon dioxide and silicon interface potential barrier, is swept to silicon substrate by electric field in the silicon dioxide then.This process is commonly referred to wipes.
The eprom memory disadvantage is to wipe with electrical method, can only memory contents once all be wiped with the UV ultraviolet light, but can not word for word wipe, and when wiping with the UV ultraviolet light, EPROM can not switch power supply.Also need two kinds of different voltage power supplies (Vdd and Vpp) in addition, the UV ultraviolet light is wiped (about 10-20 minute) for a long time.The channel hot electron injection programming needs high electric current and high voltage, so power consumption is big.Owing to need the UV ultraviolet light to wipe, in the EPROM encapsulation process, must use the suprasil window, packaging cost is improved greatly.
In order to overcome above-mentioned shortcoming, people have developed eeprom memory again, can memory contents word for word be wiped with electrical method, can word for word rewrite, and reprogramming promptly writes again.The EEPROM memory cell adopts dual-gate MOS transistor as storage usefulness, also needs common MOS transistor effective alternatively, as shown in Figure 2.EEPROM has following characteristics: can realize that programming writes and wipes by the FN tunneling electron; Can word for word realize rewriting and wipe; Only need a kind of voltage power supply (Vdd); Can realize the internal system programing function, owing to, do not need big program current by direct FN tunnel or POLYOXIDE tunnel; Fully can with other memory such as SRAM and DRAM compatibility.The disadvantage of EEPROM be two MOS transistor as memory cell, area is big, so integrated level is low.
The purpose of design Flash flash memory is to solve the scaled problem of EEPROM by balanced memory cell and function.
The Flash flash memory is divided into following several from technology: based on the dual-gate MOS single tube structure memory cell of EPROM be EPROM type flash memory, based on double grid and the conventional MOS two tubular construction memory cell of EEPROM be EEPROM type flash memory, the dual-gate MOS single tube structure of overlapping memory cell is SPLIT-GATE flash memory etc.Flash memory is divided into two big major product NOR flash memory and NAND flash memorys from function, and the NOR flash memory is mainly used to store instruction codes and the NAND flash memory is mainly used to store data.
The Flash flash memory has following characteristics: can realize all, piece, sheet and page number erase feature; Have single-power voltage (Vdd) and two two kinds of mode of operations of voltage (Vdd and Vpp).
EPROM type flash memory memory cell as shown in Figure 3.Its feature is to utilize the channel hot electron programming; The about 12V mode of operation of single-power voltage or two voltage (Vdd and Vpp); Can be used as programmable device and realize the internal system programing function; Can realize source FN tunnel erase or raceway groove FN tunnel erase function; Compare with traditional E PROM, erasing speed is fast, can use Plastic Package, and cost is low.But it has following shortcoming: cross the problem of wiping; Big program current (every unit 200-300 microampere); Be difficult to realize low-voltage and low-power consumption application; Complex circuit designsization; Need strict process control; Because local hole trap or since the relevant trap in FN tunnel cause in read procedure that electric charge gains to cause and read interference problem.
The characteristics of EEPROM type flash memory are: identical with the EEPROM unit; Whole memory arrays is wiped very fast; There was not the problem of wiping; Do not need byte to select; Can carry out the page number-, sheet-or piece-select function; Simplicity of designization; But have very large cellar area and chip size; In addition and traditional E EPROM relatively, can only carry out whole memory arrays and wipe and can not word for word wipe.
SPLIT-GATE flash memory memory cell as shown in Figure 4.Fig. 5 is adjacent two the memory cell schematic diagrames of SPLIT-GATE flash memory that non-self-registered technology technology forms.Can process a kind of novel serial SUPERFLASH flash memory integrated more highdensity memory cell in reduced size, reduce encapsulation volume.
It has following characteristics: be injected into floating boom near gutter road, source hot electron and programme; By the FN tunnel hot electron on the floating boom drift angle is injected into control gate, realizes erase feature, so erasing speed is fast; Because control gate and floating boom are overlapped, so there was not the problem of wiping; Low program current (every unit 0.1-5 microampere); Do not need negative charge pump; Be fit to low-voltage and low-power consumption work; Being fit to very little " fragment " and EEPROM uses; But this novel serial flash memory is compared with serial EEPROM, and density is bigger, and speed is faster, and size is littler; Having higher reliability, is that conventional flash memory and Fig. 7 are shown in the SPLIT-GATE flash memory erase process as Fig. 6.
In the integrated manufacture process of the preceding road of SPLIT-GATE flash memory technology, after forming, floating boom carries out the gate oxidation second time, then difference deposit one deck 150-200 nano-multicrystal silicon thin film and one deck tungsten silicide, the nano oxidized film of deposit one deck 200-300 more at present.Carry out photo-mask process afterwards: be coated with the organic ARC anti-reflecting layer of about tens nanometers of one deck earlier, apply photoresist, then expose and develop.Carry out dry etching then.At present popular dry etch step is as follows: the organic ARC anti-reflecting layer of first dry etching, carry out the nano oxidized film of etching 200-300 then, and technological process is as shown in Figure 8.Then carry out dry method and wet method and peel off the removal photoresist; As mask, carry out dry etching tungsten silicide and polysilicon membrane with the nano oxidized film of 200-300, technological process as shown in Figure 9.Carry out the side wall oxide film dielectric deposition afterwards and return etching.Carry out normal process flow then, finish until whole processing steps.There are many shortcomings in this conventional process flow, for example, and the nano oxidized film of deposit one deck 200-300 again after polysilicon membrane and tungsten silicide thin film deposit; Need different dry method etching procedures of two steps, increased process complexity and production cost, output is low, and control gate packed structures pattern is difficult to control, has therefore influenced rate of finished products and reliability.In addition, carry out tunnel gate oxidation three-decker after floating boom forms: also there are some shortcomings in the quality of heat growth silicon dioxide/HTO/ heat growth silicon dioxide, and device reliabilities such as erase-write cycles number and data maintenance life-span are had a negative impact.
Therefore, at the shortcoming of above-mentioned existence, the present invention proposes a kind of new manufacturing flash memory control gate packed structures process modification method.The nano oxidized film of deposit one deck 200-300 no longer after polysilicon membrane and tungsten silicide thin film deposit; Only need a step dry etching operation, technological process is shown in Figure 10 and 11.After floating boom forms, carry out simultaneously adopting NO gas to carry out high annealing after tunnel gate oxidation three-decker is finished, improve tunnel gate oxide quality, thereby improve device reliabilities such as erase-write cycles number and data maintenance life-span.
Summary of the invention
The objective of the invention is to propose a kind of improvement technology that is used to make flash memory (Flash) control gate packed structures that reduces process complexity, reduces production costs.
The present invention proposes is used to prepare flash memory control gate pile structure and improves technology, is in the integrated manufacture process of the preceding road of flash memory technology, after floating boom forms and before control gate (polysilicon 2) formation, adopts following operation:
Floating boom carries out the gate oxidation second time after forming, and finishes the deposit of control gate packed structures, and step is as follows:
(1) carries out the necessary tunnel gate oxidation prerinse second time;
(2) carry out the tunnel gate oxidation second time, form SiO
2/ HTO/SiO
2Three-decker;
(3) deposit polysilicon and doping thereof, its thickness can be the 150-200 nanometer;
(4) deposit tungsten silicide thin film, its thickness can be the 100-200 nanometer;
(5) carry out conventional photo-mask process;
(6) carry out dry etching, its step is as follows:
1. carry out a step dry etching:
(A) the organic ARC anti-reflecting layer of erosion;
(B) etching tungsten silicide and polysilicon membrane;
(C) stripping photoresist.
2. wet method is peeled off the removal photoresist.
Above-mentioned technology need be on tungsten silicide the nano oxidized film of deposit one deck 200-300.As long as above-mentioned dry etching carries out a step dry etching, at first carry out the etching of organic antireflection layer, then carry out tungsten silicide and polysilicon film etching.
The present invention proposes a kind of improving one's methods of flash memory (Flash) control gate packed structures that be used to make.Has following advantage: reduced process complexity, reduced production cost, shortened process and production time, promptly improved output; Extraordinary technology stability; Obtain better control gate packed structures pattern, thereby improved rate of finished products and reliability.
Description of drawings
Fig. 1 is an EPROM floating gate memory cell schematic diagram.
Fig. 2 is an EEPROM memory cell schematic diagram.
Fig. 3 is an EPROM flash memory memory cell schematic diagram.
Fig. 4 is a SPLIT-GATE flash memory memory cell schematic diagram.
Fig. 5 is adjacent two the memory cell schematic diagrames of SPLIT-GATE flash memory that non-self-registered technology technology forms.
Fig. 6 conventional flash memory erase process schematic diagram.
Fig. 7 SPLIT-GATE flash memory erase process schematic diagram.
Fig. 8 is in the common process flow process, polysilicon 2 (control gate) photo-mask process: schematic diagram before dry etching anti-reflecting layer and the silicon oxide layer, photoresist lift off.
Fig. 9 is in the common process flow process, schematic diagram after dry etching tungsten silicide and the polysilicon membrane.
After Figure 10 technological process improves, schematic diagram after polysilicon 2 (control gate) photoetching development.
After Figure 11 technological process improves, after dry etching tungsten silicide and the polysilicon membrane and photoresist lift off schematic diagram before.
Number in the figure: 1 is that control gate, 2 is that floating boom, 3 is that electronics, 4 is that hole, 5 is that N+ source region, 6 is that P type substrate, 7 is that selection grid, 8 are that (being used for the FN tunnel approaches) oxide layer, 9 is that raceway groove erase process, 10 is that source erase process, 11 is that word line, 12 is that conventional Flash structure, 13 is that Electric Field Distribution, 14 is that tungsten silicide, 15 is that anti-emitting layer, 16 is a photoresist.
Embodiment
It is as follows that concrete enforcement control gate packed structures of the present invention forms step.
Step is as follows after floating boom forms:
(1) first step is carried out tunnel gate oxidation prerinse.
(2) second step tunnel gate oxidation three-deckers form:
(A) heat growth silicon dioxide/N
2O-LPCVD HTO/ heat growth silicon dioxide;
(B) said temperature is respectively 800-950 ℃, 750-800 ℃ and 800-950 ℃;
(C) above-mentioned threeply degree is respectively 7.5-3 nanometer/200-70 nanometer/7.5-3 nanometer;
(D) three-decker forms the back and adopts the NO gas annealing, and temperature is 850-950 ℃;
(E) the above-mentioned NO gas annealing time is 2-30 minute.
(3) the 3rd step LPCVD deposit doped polycrystalline silicon and tungsten silicide thin films, its thickness is respectively 150-250nm and 100-200nm.
(4) the 4th steps were carried out photo-mask process (as shown in figure 10):
(A) be coated with the organic ARC anti-reflecting layer of one deck 30-100 nanometer;
(B) coating photoresist;
(C) exposure and development.
(5) the 5th step dry etchings (as shown in figure 11):
(A) the organic ARC anti-reflecting layer of etching;
(B) etching tungsten silicide and polysilicon membrane;
(C) stripping photoresist.
That adopts that the present invention proposes is used to make improving one's methods of flash memory (Flash) control gate packed structures, can satisfy extensive and ultra-large flash memory manufacturing process technology performance requirement fully, aspect some electrical characteristics, for example erase-write cycles number and data keep device reliabilities such as life-span, have surpassed the performance that conventional process flow is made flash memory.
In the present specification, HTO is meant high temperature thermalization layer, and MOS refers to metal-oxide semiconductor (MOS), and LPCVD refers to low-pressure chemical vapor phase deposition, and SPL1T-6ATE is meant two fissions, is the conventional term in present technique field.
Claims (6)
1, a kind ofly be used to make flash memory control gate packed structures and improve technology, it is characterized in that in the integrated manufacture process of the preceding road of flash memory technology after floating boom formed, control gate adopted following operation before forming:
(1) carries out the tunnel gate oxidation prerinse second time;
(2) carry out the tunnel gate oxidation second time, form SiO
2/ HTO/SiO
2Three-decker;
(3) deposit polysilicon and doping thereof;
(4) deposit tungsten silicide thin film;
(5) carry out conventional photo-mask process, its step is as follows; (a) coating organic antireflection layer; (b) coating photoresist; (c) exposure and development;
(6) dry etching, its step is as follows:
(a) carry out a step dry etching, its step is as follows: at first carry out the etching of organic antireflection layer, then carry out tungsten silicide and polysilicon film etching;
(b) wet method is peeled off the removal photoresist.
2, improvement technology according to claim 1 is characterized in that: the SiO that the described second time, the tunnel gate oxidation formed
2/ HTO/SiO
2Three-decker thickness is respectively 3-7.5 nanometer/70-200 nanometer/3-7.5 nanometer.
3, improvement technology according to claim 1 is characterized in that: the described SiO that the second time, gate oxidation formed
2/ HTO/SiO
2Three-decker, temperature are respectively 800-950 ℃, 750-800 ℃ and 800-950 ℃.
4, improvement technology according to claim 3, it is characterized in that: the described second time, gate oxidation three-decker in tunnel formed after silicon dioxide/HTO/ silicon dioxide is finished, adopt NO gas to carry out high annealing, temperature is 850-950 ℃, and the time is 2-30 minute.
5, improvement technology according to claim 1 is characterized in that: the thickness of described deposit polysilicon is the 150-200 nanometer.
6, improvement technology according to claim 1 is characterized in that: the thickness of described deposit tungsten silicide thin film is the 100-200 nanometer.
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| CN101079376B (en) * | 2006-05-22 | 2010-05-12 | 中芯国际集成电路制造(上海)有限公司 | Making method for semiconductor part |
| CN104157614A (en) * | 2013-05-14 | 2014-11-19 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method for separated grid type flash memory |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1143815A (en) * | 1995-04-25 | 1997-02-26 | 现代电子产业株式会社 | Flash EEPROM cell and manufacturing methods thereof |
| US5631482A (en) * | 1994-09-30 | 1997-05-20 | United Microelectronics Corporation | Flash EEPROM memory cell with polysilicon source/drain |
| US5631179A (en) * | 1995-08-03 | 1997-05-20 | Taiwan Semiconductor Manufacturing Company | Method of manufacturing metallic source line, self-aligned contact for flash memory devices |
| CN1379462A (en) * | 2001-04-10 | 2002-11-13 | 华邦电子股份有限公司 | Process for preparing flash memory |
| US6699753B2 (en) * | 1998-05-22 | 2004-03-02 | Winbond Electronics Corporation | Method of fabricating an array of non-volatile memory cells |
-
2003
- 2003-10-30 CN CNB2003101082778A patent/CN1298026C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5631482A (en) * | 1994-09-30 | 1997-05-20 | United Microelectronics Corporation | Flash EEPROM memory cell with polysilicon source/drain |
| CN1143815A (en) * | 1995-04-25 | 1997-02-26 | 现代电子产业株式会社 | Flash EEPROM cell and manufacturing methods thereof |
| US5631179A (en) * | 1995-08-03 | 1997-05-20 | Taiwan Semiconductor Manufacturing Company | Method of manufacturing metallic source line, self-aligned contact for flash memory devices |
| US6699753B2 (en) * | 1998-05-22 | 2004-03-02 | Winbond Electronics Corporation | Method of fabricating an array of non-volatile memory cells |
| CN1379462A (en) * | 2001-04-10 | 2002-11-13 | 华邦电子股份有限公司 | Process for preparing flash memory |
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