CN102983080B - Method for improving erasure and programming performances of split gate memory - Google Patents
Method for improving erasure and programming performances of split gate memory Download PDFInfo
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- CN102983080B CN102983080B CN201210577035.2A CN201210577035A CN102983080B CN 102983080 B CN102983080 B CN 102983080B CN 201210577035 A CN201210577035 A CN 201210577035A CN 102983080 B CN102983080 B CN 102983080B
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Abstract
The invention provides a method for improving erasure and programming performances of a split gate memory. The method for improving the erasure and programming performances of the split gate memory comprises the following steps of lamination forming, silicon nitride photoetching, silicon nitride etching, injection and floating gate polysilicon slope etching, wherein in the lamination forming step, a gate oxide layer, a floating gate polysilicon layer and a silicon nitride layer are formed on a substrate in sequence; in the silicon nitride photoetching step, photoresist is laid on the silicon nitride layer and photoetched; in the silicon nitride etching step, the silicon nitride layer is etched, and a floating gate tip forming zone and a middle zone of the split gate memory of the floating gate polysilicon layer are exposed; in the injection step, inclined ions are injected into the floating gate tip forming zone of the split gate memory by taking the silicon nitride layer as a mask, and the etching speed of polysilicon of the floating gate tip forming zone is higher than that of polysilicon of the middle zone; and in the floating gate polysilicon slope etching step, isotropical etching is conducted on the floating gate polysilicon.
Description
Technical field
A kind of the present invention relates to field of semiconductor manufacture, it is more particularly related to wiping improving point grid memory
Except and program performance method.
Background technology
Flash memory is convenient with it, and storage density is high, becomes the focus of research in non-volatility memorizer the advantages of good reliability.
Since the 1980s, first flash memory products came out, developing with each electronic product to storage with technology
Demand, flash memory is widely used in mobile phone, and notebook, in the movement such as palm PC and USB flash disk and communication apparatus.
Flash memory is a kind of nonvolatile memory, and its operation principles is the critical electricity by changing transistor or memory cell
Pressure controlling the purpose to reach data storage for the switch of gate pole passage, makes the storage data in memory will not be because in power supply
Break and disappear, and flash memory is a kind of special construction of electrically erasable and programmable read-only storage.Nowadays flash memory already takes up
Most of market share of non-volatile semiconductor memory, becomes non-volatile semiconductor memory with fastest developing speed.
In general, flash memory is the combination of grid dividing structure or stacking gate structure or two kinds of structures.Gate-division type flash memory is due to it
Special structure, compares stacking flash memory in grating and all embodies its unique performance advantage when programmed and erased, therefore divide grid
, due to having a high programming efficiency, the advantages of the structure of wordline can avoid " cross and wipe ", application is particularly extensive for formula structure.
With the development of electronic product, there is higher and higher requirement to memory erasing and program performance, thus wishing
A kind of preferably improvement can be provided to divide the erasing of grid memory and a method for program performance.
Content of the invention
The technical problem to be solved is that there is drawbacks described above in prior art, provides one kind can improve
Divide the erasing of grid memory and the method for program performance.
In order to realize above-mentioned technical purpose, according to the present invention, there is provided a kind of improvement divides erasing and the programming of grid memory
The method of performance, it includes：Lamination forming step, for sequentially forming gate oxide level, floating gate polysilicon layer on substrate
And silicon nitride layer；Silicon nitride lithography step, carries out photoetching for arrangement photoresist on silicon nitride layer and to photoresist；Silicon nitride
Etch step, for being performed etching to silicon nitride layer using the photoresist after photoetching, thus expose point grid of floating gate polysilicon layer
The floating boom tip forming region of memory and its zone line；Implantation step, for being stored to point grid with silicon nitride layer for mask
The floating boom tip forming region of device carries out angle-tilt ion injection, so that the polysilicon etch rate of floating boom tip forming region is big
Polysilicon in zone line；Floating gate polysilicon gradient etch step, for carrying out isotropic etching to floating gate polysilicon.
Preferably, the method for the described erasing and program performance improving point grid memory also includes：Floating boom side wall deposit step
Suddenly, for depositing floating boom side wall layer；Floating boom side wall etch step, for performing etching to floating boom side wall layer, thus in groove
Floating gate side walls are formed on the wall of side；Floating boom side wall wet etch step, for carrying out wet etching to floating boom side wall；Floating gate polysilicon
Etching step, the recess region for floating gate polysilicon layer is etched further, thus the floating boom etching away zone line is many
Crystal silicon.
Preferably, the injection of described angle-tilt ion include being formed respectively the first of the first injection region and the second injection region tilt from
Son injection and the injection of the second angle-tilt ion, and the first angle-tilt ion injects and the second angle-tilt ion is injected with respect to vertical direction
It is arranged symmetrically, so that the first injection region being formed in the floating boom tip forming region of point grid memory and the second injection region pair
Claim arrangement.
Preferably, the first angle-tilt ion injection and the second angle-tilt ion are injected all in vertical direction with suitable angle.
Preferably, the first angle-tilt ion injection A1 and the second angle-tilt ion injection A2 is all in vertical direction with 45 °.
Preferably, the first angle-tilt ion injection is identical with Implantation Energy with the injection ion of the second angle-tilt ion injection.
Preferably, the injection ion of the first angle-tilt ion injection and the injection of the second angle-tilt ion is to accelerate etch rate
Ion.
Compared with point grid memory cell made with point grid memory manufacture process of prior art, implemented according to the present invention
The most advanced and sophisticated forming region of point grid memory cell that the improvement of example divides the erasing of grid memory and the method for program performance is made
Polysilicon thickness reduces the most advanced and sophisticated height of floating boom compared with I, thus improving erasing and the program performance of point grid memory, mesozone
The thicker polysilicon in domain then can reduce the risk that substrate is etched in floating gate polysilicon etch step.
Brief description
In conjunction with accompanying drawing, and by reference to detailed description below, it will more easily have more complete understanding to the present invention
And its adjoint advantages and features are more easily understood, wherein：
Fig. 1 to Fig. 7 schematically shows each step of point grid memory manufacture process according to prior art.
Fig. 8 schematically shows improvement according to embodiments of the present invention and divides the erasing of grid memory and the side of program performance
The implantation step of method.
Fig. 9 schematically shows improvement according to embodiments of the present invention and divides the erasing of grid memory and the side of program performance
The floating gate polysilicon gradient etching step of method.
Figure 10 schematically shows point grid memory list made according to point grid memory manufacture process of prior art
Improvement first Yu according to embodiments of the present invention divides point grid memory list that the erasing of grid memory and the method for program performance are made
The contrast of unit.
It should be noted that accompanying drawing is used for the present invention is described, and the unrestricted present invention.Note, represent that the accompanying drawing of structure can
Can be not necessarily drawn to scale.And, in accompanying drawing, same or like element indicates same or like label.
Specific embodiment
In order that present disclosure is more clear and understandable, with reference to specific embodiments and the drawings in the present invention
Appearance is described in detail.
In order to clearly explain the present invention, point grid memory system according to prior art to be described with reference first to Fig. 1 to Fig. 7
Make each step of process；Specifically, following steps are executed successively：
Lamination forming step, for sequentially forming gate oxide level 2, floating gate polysilicon layer 3 and silicon nitride on substrate 1
Layer 4, as shown in Figure 1；
Silicon nitride lithography step, carries out photoetching for arrangement photoresist 5 on silicon nitride layer 4 and to photoresist 5, such as Fig. 2
Shown；
Silicon nitride etch step, for being performed etching to silicon nitride layer 4 using the photoresist 5 after photoetching, thus expose floating
The floating boom tip forming region of point grid memory of gate polysilicon layer 3 and its zone line, as shown in Figure 3；
Floating gate polysilicon gradient etching step, for gradient etching is carried out to floating gate polysilicon layer 3, thus in floating boom polycrystalline
Formed in silicon layer 3 and have acclive groove, as shown in Figure 4；
Floating boom side wall depositing step, for depositing floating boom side wall layer 6, as shown in Figure 5；
Floating boom side wall etch step, for performing etching to floating boom side wall layer 6, thus form floating boom on the side wall of groove
Side wall (as shown in the 61 and 62 of Fig. 6)；
Floating gate polysilicon etching step, the recess region for floating gate polysilicon layer 3 is etched further, thus etching
Fall the floating gate polysilicon of zone line, as shown in Figure 7.
Compare with above-mentioned prior art, improvement according to embodiments of the present invention divides erasing and the program performance of grid memory
Method include：
Lamination forming step, for sequentially forming gate oxide level 2, floating gate polysilicon layer 3 and silicon nitride on substrate 1
Layer 4, as shown in Figure 1；
Silicon nitride lithography step, carries out photoetching for arrangement photoresist 5 on silicon nitride layer 4 and to photoresist 5, such as Fig. 2
Shown；
Silicon nitride etch step, for being performed etching to silicon nitride layer 4 using the photoresist 5 after photoetching, thus expose floating
The floating boom tip forming region of point grid memory of gate polysilicon layer 3 and its zone line, as shown in Figure 3；
Implantation step, for entering line tilt for mask to the floating boom tip forming region of point grid memory with silicon nitride layer 4
Ion implanting A1 and A2, so that the polysilicon etch rate of floating boom tip forming region is more than the polysilicon of zone line；As
Shown in Fig. 8；
Wherein, described angle-tilt ion injects that A1 and A2 includes being formed respectively the first injection region B1 and the second injection region B2
One angle-tilt ion injection A1 and the second angle-tilt ion injection A2, and the first angle-tilt ion injection A1 and the injection of the second angle-tilt ion
A2 is arranged symmetrically with respect to vertical direction, so that the first injection being formed in the floating boom tip forming region of point grid memory
Area B1 and the second injection region B2 is arranged symmetrically.
Preferably, the first angle-tilt ion injection A1 and the second angle-tilt ion injection A2 is all in vertical direction with suitable angle
Degree.It is further preferred that the first angle-tilt ion injection A1 and the second angle-tilt ion injection A2 is all in vertical direction with 45 °.
Preferably, the first angle-tilt ion injects A1 and the second angle-tilt ion injects injection ion and the Implantation Energy phase of A2
With；It is further preferred that the first angle-tilt ion injects A1 and the second angle-tilt ion injects the injection ion of A2 for accelerating to etch
The ion of speed.
Floating gate polysilicon gradient etch step, for carrying out isotropic etching to floating gate polysilicon, due to most advanced and sophisticated shape
Become the etch rate in region to be more than zone line so that the polysilicon thickness of most advanced and sophisticated forming region is less, and zone line is then protected
Leave thicker polysilicon, as shown in Figure 9.
Hereafter, subsequent step can be executed as prior art, specifically, following step can be executed：
Floating boom side wall depositing step, for depositing floating boom side wall layer 6；
Floating boom side wall etch step, for performing etching to floating boom side wall layer 6, thus form floating boom on the side wall of groove
Side wall；
Floating boom side wall wet etch step, for carrying out wet etching to floating boom side wall；
Floating gate polysilicon etching step, the recess region for floating gate polysilicon layer 3 is etched further, thus etching
Fall the floating gate polysilicon of zone line.
Figure 10 schematically shows point grid memory list made according to point grid memory manufacture process of prior art
Improvement first Yu according to embodiments of the present invention divides point grid memory list that the erasing of grid memory and the method for program performance are made
The contrast of unit.Because injection ion increases etch rate, so, improvement according to embodiments of the present invention divides the wiping of grid memory
Except and program performance the tip 40 of close the wordline 10 of floating boom 20 of point grid memory cell made of method highly less.
Compared with point grid memory cell made with point grid memory manufacture process of prior art, implemented according to the present invention
The most advanced and sophisticated forming region of point grid memory cell that the improvement of example divides the erasing of grid memory and the method for program performance is made
Polysilicon thickness reduces the most advanced and sophisticated height of floating boom compared with I, thus improving erasing and the program performance of point grid memory, mesozone
The thicker polysilicon in domain then can reduce the wind that the substrate in floating gate polysilicon etch step is etched (substrate pitting)
Danger.
And, divide in improvement according to embodiments of the present invention in the erasing of grid memory and the method for program performance, except
Outside implantation step, other steps all can be integrated in original manufacturing step of point grid memory, thus not increasing new covering
Film, will not increase cost.
Furthermore, it is necessary to explanation, unless stated otherwise or point out, otherwise the term in specification " first ", " the
Two ", " 3rd " etc. describes each assembly being used only in differentiation specification, element, step etc., rather than is used for representing each
Logical relation between assembly, element, step or ordinal relation etc..
Although it is understood that the present invention is disclosed as above with preferred embodiment, but above-described embodiment being not used to
Limit the present invention.For any those of ordinary skill in the art, without departing under technical solution of the present invention ambit,
The technology contents that the disclosure above all can be utilized are made many possible variations and modification, or are revised as to technical solution of the present invention
Equivalent embodiments with change.Therefore, every content without departing from technical solution of the present invention, according to the technical spirit pair of the present invention
Any simple modification made for any of the above embodiments, equivalent variations and modification, all still fall within the scope of technical solution of the present invention protection
Interior.
Claims (6)
1. a kind of improvement divides the erasing of grid memory and the method for program performance it is characterised in that including：
Lamination forming step, for sequentially forming gate oxide level, floating gate polysilicon layer and silicon nitride layer on substrate；
Silicon nitride lithography step, carries out photoetching for arrangement photoresist on silicon nitride layer and to photoresist；
Silicon nitride etch step, for being performed etching to silicon nitride layer using the photoresist after photoetching, thus expose floating boom polycrystalline
The floating boom tip forming region of point grid memory of silicon layer and its zone line；
Implantation step, for carrying out angle-tilt ion note for mask to the floating boom tip forming region of point grid memory with silicon nitride layer
Enter, so that the polysilicon etch rate of floating boom tip forming region is more than the polysilicon of zone line；
Floating gate polysilicon gradient etch step, for carrying out isotropic etching to floating gate polysilicon.
2. the erasing of point grid memory and the method for program performance improved according to claim 1 is it is characterised in that also wrap
Include：
Floating boom side wall depositing step, for depositing floating boom side wall layer；
Floating boom side wall etch step, for performing etching to floating boom side wall layer, thus form floating gate side walls on the side wall of groove；
Floating boom side wall wet etch step, for carrying out wet etching to floating boom side wall；
Floating gate polysilicon etching step, the recess region for floating gate polysilicon layer is etched further, thus in etching away
Between region floating gate polysilicon.
3. according to claim 1 and 2 improve the erasing of point grid memory and the method for program performance it is characterised in that
Described angle-tilt ion injection includes forming the first injection region respectively and the first angle-tilt ion injection and second of the second injection region is inclined
Oblique ion injects, and the injection of the first angle-tilt ion and the injection of the second angle-tilt ion are arranged symmetrically with respect to vertical direction, thus
The first injection region being formed and the second injection region in the floating boom tip forming region of score grid memory is made to be arranged symmetrically.
4. according to claim 1 and 2 improve the erasing of point grid memory and the method for program performance it is characterised in that
First angle-tilt ion injection and the second angle-tilt ion are injected all in vertical direction with 45 °.
5. according to claim 1 and 2 improve the erasing of point grid memory and the method for program performance it is characterised in that
First angle-tilt ion injection is identical with Implantation Energy with the injection ion of the second angle-tilt ion injection.
6. according to claim 1 and 2 improve the erasing of point grid memory and the method for program performance it is characterised in that
The injection ion of the first angle-tilt ion injection and the injection of the second angle-tilt ion is the ion that can accelerate etch rate.
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| CN201210577035.2A CN102983080B (en) | 2012-12-26 | 2012-12-26 | Method for improving erasure and programming performances of split gate memory |
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