CN104269409B - NAND flash memory and manufacturing method thereof - Google Patents
NAND flash memory and manufacturing method thereof Download PDFInfo
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- CN104269409B CN104269409B CN201410550486.6A CN201410550486A CN104269409B CN 104269409 B CN104269409 B CN 104269409B CN 201410550486 A CN201410550486 A CN 201410550486A CN 104269409 B CN104269409 B CN 104269409B
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Abstract
The invention provides a two-dimensional NAND flash memory based on a Gate Last metal gate technology. A control gate of an NAND unit rather than a traditional polycrystalline silicon surrounded control gate is achieved through the metal gate technology, the NAND flash memory technology can be integrated with an advanced high-dielectric-constant metal gate CMOS technology and can be compatible with a current mainstream Gate Last CMOS technology, and the problem that an existing NAND flash memory technology can not be compatible with an advanced standard logic technology is solved. Meanwhile, a method for achieving a high-voltage DMOS device in the advanced high-dielectric-constant metal gate CMOS technology is provided, and therefore the flashable operation of the NAND flash memory can be achieved.
Description
Technical field
The present invention relates to a kind of semiconductor device fabrication processes, more particularly, to one kind are based on Gate Last metal gate process
Two-dimentional NAND-type flash memory technique.
Background technology
NAND-type flash memory has become as the non-volatile storage technologies of current main flow, is widely used in data center, personal electricity
The every field such as brain, mobile phone, intelligent terminal, consumer electronics, and still assume the ever-increasing situation of demand.NAND-type flash memory
Manufacturing process also Ying Jing has developed into 16nm, from two-dimentional manufacturing process to three-dimensional manufacturing process conversion.Samsung is
Through announcing the commercially producing of three dimensional NAND chip of 128Gb24 element stack.Company of Micron Technology then announces 16nm
The New Two Dimensional NAND chip of 128Gb, breaks through, using new two-dimensional cell structure, the restriction that conventional two-dimensional physical dimension reduces.
But the either new two-dimentional technique of traditional two-dimentional nand flash memory technique or Micron Technology, and three dimensional NAND is dodged
Deposit technique all can not realize well integrated with Advanced CMOS Process.The big factory of the nand flash memories such as Samsung, Micron Technology is all using special
Production line, but these production lines are incompatible with CMOS logic technique.Each wafer foundry based on CMOS technology is all no
Method realizes the production of nand flash memory.Although traditional two-dimentional nand flash memory technique and three dimensional NAND flash technology are to more than ten
The technique of nanometer, but this is only that its logic control circuit and artificial circuit part are still for NAND cell array
So use very backward CMOS technology, the e.g. production line based on 180nm, 130nm technique.On the one hand it is chip cost
Consideration, advanced CMOS processing procedure can increase the manufacturing cost of chip；Another aspect is that the write of nand flash memory cell needs 20V left
Right voltage, realizes the technology difficulty of high-voltage CMOS pipe and cost also than larger in advanced CMOS technology.Micron Technology new
Although two-dimentional nand flash memory technique employs the advanced CMOS work of high-dielectric constant metal grid (HKMG) in memory cell array area
Skill, but the logic control circuit of its chip and artificial circuit part still use very backward CMOS technology, Er Qieqi
The HKMG technique of nand flash memory cell uses the technology integrating method of Gate First (first grid), the elder generation with current main flow
Enter CMOS technology incompatible.
Some applications, particularly Embedded Application, need the chip processing speed of special high speed at present, but do not need again
Especially jumbo NAND-type flash memory, such as in several Gb magnitudes.This demand needs FA CMOS processing procedure, for example
The HKMGCMOS technique of 28nm/20nm, with the logic function realizing various complexity of high speed, but needs several Gb magnitudes simultaneously again
Nand flash memory as data access region.Current way is the chip independent using two, and logic function part is using first
Enter CMOS processing procedure to manufacture, nand flash memory chip comes from special manufacturer.But it is as NAND manufacturer manufacturing process
Constantly develop, the flash memory of low capacity manufactures and uneconomical in advanced technologies for economy, generally using backward several generations
The flash memory to manufacture low capacity for the technique.But these backward techniques of nand flash memory manufacturer can't retain always, eliminates
Quickly.In addition at present system compact, integrated be development trend, multiple chip functions be integrated into a chip no matter from
It is all advantageous on performance, power consumption or cost.
Content of the invention
The present invention proposes a kind of two-dimentional NAND-type flash memory work Ji Yu Gate Last (post tensioned unbonded prestressed concrete technique) metal gate process
Skill, is realized the control gate of NAND cell, rather than traditional polysilicon is around control gate using metal gate process, it is possible to achieve with
High-dielectric constant metal grid Advanced CMOS Process integrated, compatible with the Gate Last CMOS technology of current main flow, overcome
The problem that nand flash memory technique cannot be compatible with advanced standard logic process at present.How propose in high-k gold simultaneously
Belong to the method realizing high pressure DMOS device in grid Advanced CMOS Process, to realize the erasable operation of nand flash memory.
The technical solution adopted in the present invention is：
A kind of nand flash memory preparation method, wherein, comprises the steps：
One substrate being provided with isolated area and active area is provided, defined in described substrate, has cmos circuit area and memory cell
Array area；
It is sequentially depositing a dielectric layer and first grid material layer in the upper surface of described substrate, etch described first grid material
The bed of material forms floating boom, and the floating boom being located on described storage element area is located at the substrate between adjacent described isolated area；
Prepare the first insulation material layer to cover in the upper surface of described floating boom, and this first insulation material layer covers in storage
Dielectric layer upper surface between floating boom on cell array region；
Preparation one is sacrificed grid and is covered in the upper surface of the first insulation material layer, and sacrificial in memory cell array area
The zone line of two bottom sides floating boom is covered by domestic animal grid simultaneously；
Form source/drain in the substrate in described cmos circuit area；
Deposit the second insulation material layer and be polished to the upper surface sacrificing grid, remove described sacrifice grid；
Remove the first insulation material layer in described cmos circuit area and floating boom；
Deposit second grid material layer and be polished to the upper surface formation control gate of described second insulation material layer；
Form metal interconnection structure.
Above-mentioned preparation method, wherein, forms some grooves using photoetching and etching technics in described substrate, and in institute
State fill insulant in groove and form described isolated area.
Above-mentioned preparation method, wherein, forms comprising the following steps that of source/drain：
Prepare a mask material and form opening in this mask material, carry out ion implantation technology using described opening,
Form described source/drain in the substrate top surface being directed at described opening；
Wherein, the close floating boom on cmos circuit area of described source electrode, and described drain electrode is electric with positioned at described CMOS
At least provided with an isolated area between floating boom on the area of road.
Above-mentioned preparation method, wherein, when carrying out described ion implantation technology, the opening in order to form source class will be sacrificed
The part surface of grid is exposed.
Above-mentioned preparation method, wherein, after forming described source/drain, continues to carry out the second secondary ion to described drain electrode
Injection, to deepen described drain electrode depth.
Above-mentioned preparation method, wherein, adopts the first insulating barrier removing with the following method in described cmos circuit area
And floating boom：
Prepare a mask material to be covered the surface in described cmos circuit area and memory cell areas；
Carry out Patternized technique, remove the mask material positioned at cmos circuit area；
Perform etching technique afterwards and remove the first insulating barrier and floating boom in described cmos circuit area；
Remove remaining mask material.
Above-mentioned preparation method, wherein, is formed with space between adjacent floating boom in described memory cell areas.
Above-mentioned preparation method, wherein, described first grid material layer, sacrifice grid are polysilicon；
Described second grid material layer is metal.
Above-mentioned preparation method, wherein, described first grid material layer, the first insulation material layer are all by ALD (Atomic
Layer Deposition, ald) technique formed.
Above-mentioned preparation method, wherein, the step forming described metal interconnection structure is as follows：
Deposit the 3rd insulation material layer, carry out Patternized technique, be formed at described control gate and the top of described source/drain
Through hole；
Through hole is filled with and is ground forming metal interconnection structure by deposited metal material.
A kind of nand flash memory, wherein, described nand flash memory includes a substrate, and the definition of described nand flash memory has cmos circuit
Area and memory cell array area, described cmos circuit area and memory cell array area are all covered with insulating materials positioned at substrate
Layer, and in described substrate, it is provided with active area and isolated area；
Be formed with source class and drain electrode in the substrate in described cmos circuit area, the substrate positioned at described cmos circuit area it
On be formed with grid, described source class is near being provided with an isolated area between described grid, described drain electrode and described grid；
It is provided with some isolated areas in the substrate in described memory cell array area, be located between adjacent described isolated area
Substrate is provided with floating boom and control gate；Described control gate is arranged at the top of described control gate and by adjacent floating boom
Above-mentioned nand flash memory, wherein, described floating boom is polysilicon gate, and described grid and control gate are metal gate.
Above-mentioned nand flash memory, wherein, source class depth described in described drain electrode depth ratio is deep.
Above-mentioned nand flash memory, wherein, described grid and described control gate are all formed by Gate Last technique.
Above-mentioned nand flash memory, wherein, is formed with space between described floating boom.
Brief description
By reading the detailed description non-limiting example made with reference to the following drawings, the present invention and its feature, outward
Shape and advantage will become more apparent upon.Identical mark instruction identical part in whole accompanying drawings.Not deliberately proportionally
Draw accompanying drawing, it is preferred that emphasis is the purport of the present invention is shown.
A kind of nand flash memory preparation method that Fig. 1 a～Figure 11 b provides for the embodiment of the present invention one.
A kind of nand flash memory that Figure 12 a～12b provides for the embodiment of the present invention two.
Specific embodiment
Below in conjunction with the accompanying drawings the specific embodiment of the present invention is further described：
Embodiment one
A kind of two-dimentional NAND-type flash memory technique Ji Yu GateLast (post tensioned unbonded prestressed concrete) metal gate process proposed by the present invention, its
Mesohigh DMOS (Doublediffusion metal-oxide-semiconductor, double-diffused metal oxide semiconductor)
Taking N-type MOS as a example, the processing step of p-type metal-oxide-semiconductor is similar to device, and the present invention emphasizes compatible with standard metal grid CMOS technology
Property, will not be described here.Reference picture 1a～Figure 11 b show the preparation flow figure of the present invention, and wherein left hand view a is is along NAND
The sectional view in array bitline direction, right part of flg b is the sectional view along NAND array word-line direction, and specific embodiment includes following
Step.
Step S1：One substrate 1 is provided, can be selected for monocrystalline silicon wafer crystal as starting substrates 1, Silicon Wafer can be single layer structure
Or sandwich construction, such as SOI ((Silicon On Insulator, silicon-on-insulator) chip, the concrete step forming SOI wafer
Suddenly worked by this area, be will not be described here.1-A region is cmos circuit region, and 1-B is nand flash memory array region.?
Photoetching is passed through on substrate 1 and etching forms device active region and isolated groove, and deposit an insulating materials (such as oxide layer) will
Isolated groove is filled with, formed isolated area 2, eventually pass CMP be ground to substrate 1 upper surface as shown in Figure 1.Its
In, nand flash memory array region represented by 1-B can be using twice or multiexposure, multiple exposure (Double/Multiple
Exposure), autoregistration spacer (self-aligned spacer), repetition spacer method (repeated spacer
) etc. approach method increases the density of the isolated area 2 depositing array region under same lithographic equipment, and then follow-up to increase
The pattern density of memory cell, related process is well known in the art, will not be described here.
Step S2：Prepare a dielectric layer 3 in the upper surface of the substrate 1 preparing active area figure, as shown in Figure 2.At this
In inventive embodiment, this dielectric layer 3 is preferably high dielectric constant material, the dielectric material (HfSiON) of such as hafnium base.Need
Illustrate, the accompanying drawing of corresponding the present embodiment simply depicts the high dielectric constant material adopting same thickness on entire substrate 1,
In specific implementation process also dependent on the requirement to device property for the zones of different adopt different-thickness dielectric material it is also possible to
It is high dielectric constant material or the Conventional dielectric constant material such as SiO of different-thickness2, or a combination of both,
It will not go into details for this.
Step S3：Form the floating boom 4 (floating of nand flash memory on cmos circuit area and memory cell array area
Gate, FG).Comprise the following steps that：One layer of first grid material layer of deposition covers in the upper surface of dielectric layer 3, is patterned
Technique, etches this first grid material layer and forms floating boom 4.
The technique of patterning is as follows：After deposition first grid material layer, one layer of photoresist of spin coating is by first grid material layer
Covered, afterwards by a mask board to explosure developing process, formed opening in the photoresist, afterwards again to be formed with out
The photoresist of mouth carries out dry etching for etch mask to first grid material layer, and remaining first grid material layer is as floating boom
4, finally remove remaining photoresist.Meanwhile, in order to improve lithographic results further, one layer of anti-reflecting layer can be coated in advance
(BARC) in the upper surface of dielectric layer 3, carry out the coating of photoresist afterwards again, reduced using BARC and be exposed technique
When, because the refraction of light thus easily cause the phenomenon of overexposure to photoresist, and then after controlling exposure imaging further
The A/F being formed in the photoresist, thus reaching the width controlling floating boom, improves technological effect.But art technology
Personnel should be appreciated that coating BARC layer is intended merely to improve further lithographic accuracy, also may be used according to Production requirement or cost control
Directly carry out photoetching to be not coated by BARC layer, the present invention is had no effect on.
Further, after Patternized technique, it is single that the floating boom 4 on memory cell array area 1-B is located at storage
On substrate between adjacent isolation regions 2 in element array area, concrete formation can pass through selected covering in carrying out Patternized technique
Lamina membranacea is controlled, and will not be described here.Now circuit 1-A and memory cell array area 1-B region all can form floating polysilicon
The figure of grid 4, the region of this figure is exactly the region of vegetation transistor gate below, and the multi-crystal silicon floating bar 4 in 1-A region can be rear
Remove in continuous technique, hereafter have associated description.
Above-mentioned first grid material layer is using ALD (Atomic Layer Deposition, ald) technique
The polysilicon (poly) being deposited, and the thickness depositing is less than 10nm.
Step S4：Deposit the first insulation material layer 5 and cover in the upper surface of floating boom 4, simultaneously positioned at memory cell array
Also the first insulation material layer can be formed between floating boom 4 on area 1-B, and then in memory cell array area in subsequent process
Form space between floating boom 4 on 1-B, hereafter can have a detailed description.Concretely comprise the following steps：Deposit the first insulation material layer will scheme
The surface of device shown in 3 is completely covered, and carries out Patternized technique afterwards and removes the first unnecessary insulating barrier of floating boom 4 both sides, meanwhile,
Need to ensure that the first insulation material layer between the floating boom 4 on memory cell array area 1-B will not be removed, that is, in 1-B
Also insulating materials (in figure does not indicate) can be filled out in space between region bit line and bit line.Then lithographic definition is recycled to need
The region of grid to be prepared, prepares sacrificial gate of polysilicon 6, as shown in Figure 4.
This first insulation material layer 5 is SiO2Or other insulating materials (such as ONO material), using the side of ald
Prepared by method, and deposit this thickness less than 10nm.
In the top of floating boom 4 preparation one sacrifice grid 6, and the sacrifice grid 6 being located on memory cell array area 1-B is
Integrated setting, that is, this sacrifice grid 6 region between the floating boom 4 on memory cell array area 1-B is also carried out covering simultaneously
Lid.As shown in Figure 4.
Concrete first insulation material layer 5 that formed is essentially identical with the technique sacrificing grid 6, all includes a depositing operation and figure
Case metallization processes, this step is well known in the art, will not be described here.
Step S5：The source-drain electrode of the high pressure DMOS device required to nand flash memory operation carries out ion implanting, in CMOS electricity
Form source class (S) and drain electrode (D) in the substrate 1 of road area 1-A.
Specifically, prepare a mask material 7 (such as photoresist) and form opening in this mask material, will not need to note
The region entering is protected, and carries out ion implantation technology using the opening among mask material 7 afterwards, in the substrate of be aligned opening
Upper surface forms source class (S) and drain electrode (D), as shown in Figure 5.The ion implanting of this step can be shared with standard CMOS device
Or be separately injected into.
Optionally, the source electrode that the present invention is formed is near the floating boom 4 on cmos circuit area 1-A, and then makes DMOS
Source S near the control gate that ultimately forms, and then ensure that device has good on state characteristic；Drain electrode simultaneously is electric with positioned at CMOS
At least provided with an isolated area 2 between floating boom 4 on the area of road, to improve the pressure of its drain electrode, prevent drain electrode and CMOS electricity
Puncturing between the grid of road area 1-A.Preferably, can be by partial sacrifice grid in order to form the opening of source class (S) in mask material 7
The side of pole 6 is exposed, and then makes when carrying out ion implanting, in the substrate 1 upper surface formation source near floating boom 4 side
Level.Simultaneously the opening formed in mask material 7 generally by photoetching process come realizing if it is desired to precise control
The source class that end form becomes, near floating boom 4, also needs to the width of guarantee source class within the specific limits simultaneously, and the cost generation of photoetching process
Valency is sufficiently expensive, and if necessary to the above-mentioned condition of precise control it is necessary to advanced lithographic equipment, this undoubtedly improves and produces into
This.And the side sacrificing grid 6 is exposed by the opening that the present invention is formed simultaneously, not only make ion implanted formation
Source class near the metal gates that subsequently formed, be also easier to control the A/F of source class simultaneously.Further, due to sacrificial
Domestic animal grid 6 can be removed in subsequent step, even if the ion of injection can impact to sacrificing grid 6, but with subsequently sacrificial
The removal of domestic animal grid 6, thus having any impact to devices itself, thus ensure that the performance of device.
Meanwhile, on the DMOS architecture basics that step S5 prepares, further the drain region of DMOS can be carried out with
Secondary ion injects, and deepens drain electrode depth, to improve its breakdown voltage (Breakdown voltage, BV) to substrate for the drain electrode,
Other regions are protected with mask material 7, as shown in Figure 6.
Step S6：The mask material 7 of removal step S5, and deposit the second insulation material layer 8, carry out flat chemical industry afterwards
Skill, it is preferred to use CMP polishing the second insulation material layer 8 to the upper surface sacrificing grid 6, as shown in Figure 7.Wherein, heavy
After amassing the second insulation material layer 8 and grinding, positioned at the insulating materials sacrificed between grid 6 on memory cell array area 1-B
Space 9 can be formed with, this is because the first insulating materials 5 depositing in step s 4 is not by memory cell array area 1-B
On floating boom 4 between groove be filled up completely with, simply the bottom in the region between floating boom 4 is covered, therefore in deposition second
After insulation material layer 8, because the gate pitch on memory cell array area 1-B is less, space can be produced in the filling process
9, the isolation between wordline and wordline can be improved, as shown in Figure 7b.
Step S7：Remove sacrifice grid 6, specifically can sacrifice grid 6 is removed using dry etch process, enter one
Step, the etching gas that dry etching is adopted have larger etching ratio to polysilicon, and for the first insulation material layer 5 then
There is less etching ratio, therefore during going to remove sacrifice grid 6, the first insulation material layer 5 will not be caused larger
Damage；First insulation material layer 5 serves the protective effect to floating boom 4 simultaneously, is also unaffected.Therefore this step completes
Afterwards, the sacrifice grid 6 of cmos circuit area 1-A and memory cell array area 1-B all can be removed, simultaneously because the first insulating materials
The presence of layer 5, multi-crystal silicon floating bar 4 can be retained, as shown in Figure 8.
Step S8：Remove the first insulation material layer 5 and floating boom 4 in cmos circuit area 1-A.Comprise the following steps that：
Preparing a mask material 7 will need to protect the locality protection of multi-crystal silicon floating bar, is removed using etching technics afterwards and is exposed to
The first outer insulation material layer 5 and floating boom 4, and it is located at the first insulation material layer 5 and floating boom on memory cell array area 1-B
4 can remain, and form the structure shown in Fig. 9.
Step S9：Remove mask material 7, deposit second grid material layer and be polished to the upper table of the second insulation material layer 8
Face forms control gate (control gate, CG) 10.Specifically, using ALD process deposits layer of metal layer by the surface of device
After being covered and being carried out planarization process, and then form metal control gate 10, as shown in Figure 10.1-A and 1-B region, no matter
It is CMOS, DMOS or the transistor gate in nand flash memory storage array region all using identical metal gate process.
Step S10：Form metal interconnection structure.Comprise the following steps that：On the architecture basics that step S9 prepares, deposition
3rd insulation material layer, carries out Patternized technique, is formed and is located on cmos circuit area 1-A and memory cell array area 1-B
The through hole of the top of control gate 10 and source/drain；Deposited metal material through hole is filled with and be ground formed metal mutual
Connection structure 11.Optionally, through hole is filled with form metal interconnection structure 11 using tungsten, using as contact electrode.Above-mentioned step
Suddenly form the structure shown in Figure 11 after being fully completed.
Hereafter processing step is the preparation of the metal level realizing transistor interconnection, using this area standard CMOS process,
Will not be described here.
Embodiment two
Simultaneously present invention also offers a kind of nand flash memory 1000, as shown in figures 12 a and 12b, Figure 12 a is along NAND array
The sectional view of bit line direction, Figure 12 b is the sectional view along NAND array word-line direction.
Nand flash memory 1000 includes a substrate 100, and the upper surface of substrate 100 is coated with a floor height dielectric constant material layer
102.It is provided with active area (AA) and isolated area in the substrate 100 of cmos circuit area 1-A and memory cell array area 1-B
101；
It is formed with source class (S) and drain electrode (D) in the substrate in cmos circuit area, positioned at the substrate of cmos circuit area 1-A
It is formed with grid 108 on 100.Wherein, source class is near grid 108, and then ensures that device has good on state characteristic；And drain
It is provided with an isolated area 101 and grid 108 between, to improve the pressure of its drain electrode, prevent the puncturing and grid between that drain；With
When drain electrode depth deeper than source class depth, and then be conducive to improving the voltage endurance capability of its drain electrode, prevent drain electrode and cmos circuit
Puncturing between the grid 108 of area 1-A.
Further, grid 108 is metal gates, and by prepared by gate last technique.
It is provided with some isolated areas 101 in the substrate 100 of memory cell array area 1-B, between adjacent isolation regions 101
It is provided with floating boom 103 and control gate 105 on substrate 100, and this integrated setting of control gate 105, and then by both sides
The plane in the region between floating boom 103 is covered.It is additionally provided with an insulation material layer between floating boom 103 and control gate 105
104.
Further, floating boom 103 is polysilicon gate, and control gate 105 is metal gate, and this control gate is by Gate
The prepared and above-mentioned grid of Last technique 108 is synchronous to be formed.
It is also covered with an insulating materials 106 on the substrate 100 of cmos circuit area 1-A and memory cell array area 1-B,
And be formed with space 200 between the grid of memory cell areas, and then isolation and wordline between for the wordline (WL) can be improved.
Be formed with metal interconnection structure 107 in insulating materials 106, this metal interconnection structure 107 be located at grid 108,
Control gate 105 and the top of source-drain electrode, using as contact electrode.
In sum, due to present invention employs as above technical scheme, by two based on Gate Last metal gate process
Dimension NAND-type flash memory technique, is realized the control gate of NAND cell, rather than traditional polysilicon is around control using metal gate process
Grid processed, it is possible to achieve integrated with high-dielectric constant metal grid Advanced CMOS Process；Gate Last with current main flow simultaneously
CMOS technology is compatible, overcomes the problem that current nand flash memory technique cannot be compatible with advanced standard logic process.Propose simultaneously
The method how to realize high pressure DMOS device in high-dielectric constant metal grid Advanced CMOS Process, to realize nand flash memory
Erasable operation.
Above presently preferred embodiments of the present invention is described.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment describing in detail and structure are not construed as giving reality with the common mode in this area to the greatest extent
Apply；Any those of ordinary skill in the art, without departing under technical solution of the present invention ambit, can be utilized the disclosure above
Methods and techniques content technical solution of the present invention is made with many possible variations and modification, or be revised as equivalent variations etc.
Effect embodiment, this has no effect on the flesh and blood of the present invention.Therefore, every content without departing from technical solution of the present invention, foundation
The technical spirit of the present invention, to any simple modification made for any of the above embodiments, equivalent variations and modification, all still falls within the present invention
In the range of technical scheme protection.
Claims (15)
1. a kind of nand flash memory preparation method is it is characterised in that comprise the steps：
One substrate being provided with isolated area and active area is provided, defined in described substrate, has cmos circuit area and memory cell array
Area；
It is sequentially depositing a dielectric layer and first grid material layer in the upper surface of described substrate, etch described first grid material layer
Form floating boom, and the floating boom being located on described memory cell array area is located at the substrate between adjacent described isolated area；
Prepare the first insulation material layer to cover in the upper surface of described floating boom, and this first insulation material layer covers in memory cell
Dielectric layer upper surface between floating boom on array area；
Preparation one is sacrificed grid and is covered in the upper surface of the first insulation material layer, and is located at the sacrificial gate in memory cell array area
The zone line of two bottom sides floating boom is covered by pole simultaneously；
Form source/drain in the substrate in described cmos circuit area；
Deposit the second insulation material layer and be polished to the upper surface sacrificing grid, remove described sacrifice grid；
Remove the first insulation material layer in described cmos circuit area and floating boom；
Deposit second grid material layer and be polished to the upper surface formation control gate of described second insulation material layer；
Form metal interconnection structure.
2. preparation method as claimed in claim 1 is it is characterised in that formed in described substrate using photoetching and etching technics
Some grooves, and fill insulant forms described isolated area in described groove.
3. preparation method as claimed in claim 1 is it is characterised in that form comprising the following steps that of source/drain：
Prepare a mask material and form opening in this mask material, carry out ion implantation technology using described opening, right
The substrate top surface of accurate described opening forms described source/drain；
Wherein, described source electrode is near floating boom on cmos circuit area, and described drain electrode with positioned at described cmos circuit area
On floating boom between at least provided with an isolated area.
4. preparation method as claimed in claim 3 is it is characterised in that when carrying out described ion implantation technology, in order to be formed
The part surface sacrificing grid is exposed by the opening of source class.
5. preparation method as claimed in claim 3 is it is characterised in that after forming described source/drain, continue to described drain electrode
Carry out second ion implanting, to deepen described drain electrode depth.
6. preparation method as claimed in claim 1 removes positioned at described cmos circuit area with the following method it is characterised in that adopting
In the first insulating barrier and floating boom：
Prepare a mask material to be covered the surface in described cmos circuit area and memory cell array area；
Carry out Patternized technique, remove the mask material positioned at cmos circuit area；
Perform etching technique afterwards and remove the first insulating barrier and floating boom in described cmos circuit area；
Remove remaining mask material.
7. preparation method as claimed in claim 1 is it is characterised in that be located at adjacent floating boom in described memory cell array area
Between be formed with space.
8. preparation method as claimed in claim 1 it is characterised in that described first grid material layer, sacrifice grid be many
Crystal silicon；
Described second grid material layer is metal.
9. preparation method as claimed in claim 8 is it is characterised in that described first grid material layer, the first insulation material layer
All formed by ALD technique.
10. preparation method as claimed in claim 1 is it is characterised in that the step forming described metal interconnection structure is as follows：
Deposit the 3rd insulation material layer, carry out Patternized technique, be formed at described control gate and described source/drain top logical
Hole；
Through hole is filled with and is ground forming metal interconnection structure by deposited metal material.
11. nand flash memories as claimed in claim 1 are it is characterised in that include a substrate, and the definition of described semiconductor devices has
It is provided with active area and isolated area in cmos circuit area and memory cell array area, and described substrate；
It is formed with source class and drain electrode in the substrate in described cmos circuit area, positioned at the substrate shape in described cmos circuit area
Become to have grid, described source class is near being provided with an isolated area between described grid, described drain electrode and described grid；
It is provided with some isolated areas in the substrate in described memory cell array area, between adjacent described isolated area, be located at substrate
On be provided with floating boom and control gate；
Described cmos circuit area and memory cell array area are all covered by an insulation material layer, and are located at described insulation material layer
In be provided with metal interconnection structure.
12. nand flash memories as claimed in claim 11 are it is characterised in that described floating boom is polysilicon gate, described grid and control
Grid processed are metal gate.
13. nand flash memories as claimed in claim 11 are it is characterised in that source class depth described in described drain electrode depth ratio is deep.
14. nand flash memories as claimed in claim 11 are it is characterised in that described grid and described control gate are all by Gate
Last post tensioned unbonded prestressed concrete technique is prepared and synchronous to be formed.
15. nand flash memories as claimed in claim 11 are it is characterised in that be formed with space between described floating boom.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410550486.6A CN104269409B (en) | 2014-10-16 | 2014-10-16 | NAND flash memory and manufacturing method thereof |
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| CN201410550486.6A CN104269409B (en) | 2014-10-16 | 2014-10-16 | NAND flash memory and manufacturing method thereof |
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| Publication Number | Publication Date |
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| CN104269409A CN104269409A (en) | 2015-01-07 |
| CN104269409B true CN104269409B (en) | 2017-02-15 |
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| US5514889A (en) * | 1992-08-18 | 1996-05-07 | Samsung Electronics Co., Ltd. | Non-volatile semiconductor memory device and method for manufacturing the same |
| CN101471250A (en) * | 2007-12-28 | 2009-07-01 | 海力士半导体有限公司 | Flash memory device and method of fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5514889A (en) * | 1992-08-18 | 1996-05-07 | Samsung Electronics Co., Ltd. | Non-volatile semiconductor memory device and method for manufacturing the same |
| CN101471250A (en) * | 2007-12-28 | 2009-07-01 | 海力士半导体有限公司 | Flash memory device and method of fabricating the same |
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