CN105990359B - Separate grating flush memory device and preparation method - Google Patents
Separate grating flush memory device and preparation method Download PDFInfo
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- CN105990359B CN105990359B CN201510059303.5A CN201510059303A CN105990359B CN 105990359 B CN105990359 B CN 105990359B CN 201510059303 A CN201510059303 A CN 201510059303A CN 105990359 B CN105990359 B CN 105990359B
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Abstract
The present invention provides a kind of separation grating flush memory device and preparation methods, Flash technique is integrated with CMOS technology, floating gate and control gate are prepared using self aligned technique, technique is easier to control for the traditional technology that compares, and then can further reduce the critical size of device；The present invention so that the carrier in substrate is easier to penetrate oxide layer and enters floating gate, improves carrier mobility, and effectively inhibit the leakage current of channel, and then promote the performance of device by the way that in substrate, this is conducive to improve channel length by floating gate preparation.
Description
Technical field
The present invention relates to reservoir preparation fields, and in particular to a kind of separation grating flush memory device and preparation method.
Background technique
With the continuous development of science and technology, the equipment such as mobile phone, digital camera, PSP due to it is easy to carry, recreational more by force by
The favor of people, these mobile electronic equipments require reading and storage that data are carried out by memory, therefore companion
As people are continuously increased electronic equipment demand, the important of information technology research is become to the research of memory technology
Direction, in order to preferably improve the reliability of storage density and data storage, Research Emphasis is gradually concentrated mainly on non-volatile
Memory (NVM, non-volatile memory).Flash (flash memory) is the nonvolatile memory of long-life a kind of, disconnected
Stored data information is still able to maintain after electricity, simultaneously because small in size and be widely used.
A kind of advanced separate gate flash memory is developed at present, is as shown in Figure 1 the signal of separate gate flash memory in the prior art
Figure, the separate gate flash memory include floating gate (floating gate, FG), control gate (control gate, CG), erasing grid
(erase gate, EG), wordline (word line, WL), while active line (source line, SL) and position are set in substrate
Line (bit line, BL).Since the structure provides the power of programming using novel source injection mode, compared to more traditional
The used drain side channel hot electron programmed method of technology, greatly reduces power consumption.To sum up, separate gate flash memory is due to having brilliance
Reliability, many advantages, such as operating power consumption is lower, and manufacturability is stronger, gradually manufactured and used extensively.
Fig. 2 a~2k is the flow chart of prior art 70nm~120nm technology node preparative separation gate flash memory device, tool
Steps are as follows for body: etching forms the control gate 2 on floating gate 1, forms structure shown in Fig. 2 a；One layer is sequentially prepared then at side wall
Oxide layer 3 and nitride film 4, as shown in Figure 2 b；Prepare the side wall that an offset oxide layer side wall 5 is covered on film 4 again later,
As shown in Figure 2 c；Photoetching process is carried out later to cover the region among control gate 2, then carries out an ion implanting work
Skill, as shown in Figure 2 d；The offset oxide layer side wall 5 of wordline side is removed simultaneously, then etches and to form storage unit, forms Fig. 2 e
Shown structure；An oxide layer side wall 6 is prepared then at storage unit two sides, as shown in figure 2f；Carry out photoetching and source (source)
Ion implantation technology forms source electrode in the substrate between storage unit, as shown in Figure 2 g；It removes between storage unit again later
Offset oxide layer side wall 5 and oxide layer side wall 6, form structure as shown in fig. 2h；A tunnel oxide 7 is prepared by the table of device
After face is covered, then etches removal storage unit and the tunnel oxide in wordline area (is removed with the tunnel oxide of exterior domain
Layer), form structure shown in Fig. 2 i；Layer of oxide layer (WL oxide) 8 is deposited again in wordline area, later redeposited polysilicon layer
And ground and etched and to form erasing grid (EG) 9 and wordline (WL) 10, and carry out drain terminal (drain) doping process, form leakage
Pole, finally formed structure is as shown in Fig. 2 k.
But the flush memory device prepared using method made above is due to needing using multiple photoetching process, and photoetching work
The cost of skill is very expensive, and especially when technology node reduces to a certain extent, the cost of photoetching is ramped, the essence of photoetching
Degree also will receive influence；It is formed simultaneously floating gate and control gate according to a lithography and etching technique simultaneously, due to etching one
As to pass through etching barrier layer, control gate, dielectric layer, floating gate and tunnel oxide, etching difficulty is larger, while with etching
Continuous progress, need to coat the photoresist of larger thickness in advance, therefore unavoidably increase production cost.Meanwhile according to
The flush memory device of prior art preparation is generally the semiconductor devices of plane, due to technics comparing complexity, the isolation of device
It is poor；Simultaneously because each position of grid is respectively positioned on substrate, therefore cause the whole height of storage unit higher, this increasing
The big size of device.
Therefore, how further to improve what the performance of separate gate flash memory device was studied by those skilled in the art always
Direction.
Summary of the invention
The invention discloses a kind of methods of preparative separation gate flash memory device, wherein the following steps are included:
Step A: a substrate is provided, surface is successively covered with cushion oxide layer according to sequence from low to uper part over the substrate
And dielectric layer；
Patterned process is carried out, several groups opening pair is formed in the dielectric layer and the cushion oxide layer, utilizes institute
Opening is stated to the substrate is etched, to form several groups groove pair in the substrate；
Step B: floating gate is prepared in the groove groove to be filled；
According to being sequentially sequentially prepared insulating layer and control gate from bottom to up at the top of the floating gate；
Step C: the first ion implantation technology is carried out, forms source in the substrate between two grooves of each group of groove pair
Pole doped region；
Step D: the gap preparation erasing grid between the control gate of two the top of the groove of each group of groove pair, Yi Ji
Each control gate forms word line structure away from the other side of the erasing grid, prepares later in the side wall of the word line structure
Side wall；
Step E: carrying out the second ion implantation technology, in other side substrate of the groove away from the source doping region
Form drain doping region.
Above-mentioned method, wherein in stepb, the step of preparing the floating gate includes:
Step B1: one layer of floating gate oxide layers are prepared on the surface of groove exposure；
Step B2: the first polysilicon layer of deposition is covered on dielectric layer and is filled each groove and opening, to the
One polysilicon layer is etched back, and retains the first polysilicon layer being located in groove as floating gate.
Above-mentioned method, wherein in stepb, the step of preparing the control gate includes:
Step B3: one insulating layer of deposition is covered at the top of the floating gate and table on the opening sidewalls and the dielectric layer
Continue the second polysilicon layer of deposition and be covered on the insulating layer upper surface, and the opening is filled in face；
Step B4: the second polysilicon layer, which is thinned, to be made to flush at the top of its top and the dielectric layer；
Step B5: removal medium layer, cushion oxide layer and partial insulative layer, and retain and be located at the second polysilicon layer bottom
Insulating layer.
Above-mentioned method, wherein the insulating layer is the ONO comprising oxidenitride oxide sandwich structure
Layer.
Above-mentioned method, wherein further include implementing a high temperature to repair after removing insulating layer described in part in step B5
Multiple step, and then repair when removing the insulating layer to second polysilicon layer and positioned at the second polysilicon layer bottom
It is damaged caused by insulating layer.
Above-mentioned method, wherein the specific steps of step D are as follows:
Step D1: deposition tunnel oxide is covered the surface of substrate and control gate exposure, and deviates from institute in groove
The ion implantation technology that wordline threshold voltage adjustments are carried out in the other side substrate of source doping region is stated, to adjust wordline threshold value electricity
Pressure；
Step D2: removing each groove away from the tunnel oxide of the other side substrate surface of the source doping region, and
In substrate, the surface of exposure forms wordline oxide layer due to removing tunnel oxide；
Step D3: deposition third polysilicon layer is covered on wordline oxide layer and remaining tunnel oxide, is thinned the
Three polysilicon layers make its top with flushed at the top of the control gate；
Third polysilicon layer is retained in the gap because being thinned and is spaced apart due to the isolated part that is formed, as institute
State erasing grid；
Step D4: the part third polysilicon layer and wordline oxide layer on the outside of control gate are removed, the control is formed
Word line structure of the grid away from the other side of the erasing grid；
Step D5: side wall is prepared in the side wall of the word line structure.
Above-mentioned method, wherein before the ion implantation technology for carrying out wordline threshold voltage adjustments, first carry out photoetching work
Skill is covered the source doping region and control gate positioned at source doping region two sides using photoresist.
Above-mentioned method, wherein forming the control gate away from the step of the word line structure of the other side of the erasing grid
In rapid, using patterned photoresist overlay in exposing one on the outside of control gate on third polysilicon layer, and in the photoresist
Part third polysilicon layer, and be that etch mask is sequentially etched a part removed on the outside of control gate using patterned photoresist
The third polysilicon layer and wordline oxide layer below.
Above-mentioned method, wherein the method also includes: after forming drain doping region, mixed in source doping region, drain electrode
Metal silicide is prepared at the top of miscellaneous area, word line structure, control gate and erasing grid.
The present invention also provides a kind of separation grating flush memory devices simultaneously, wherein includes:
Substrate has several groups groove pair in the substrate；
Floating gate and control gate, the floating gate are located in the groove, and the control gate is located on the floating gate and passes through
One insulating layer is isolated with the floating gate, and the insulating layer is located on the upper surface of substrate；
Gap between the control gate of two the top of the groove of each group of groove pair is formed with erasing grid, and each described
Control gate is provided with word line structure away from the other side of the erasing grid；
It is formed with source doping region in substrate between two grooves of each group of groove pair, and deviates from institute in the groove
It states in the other side substrate of source doping region and is formed with drain doping region.
Above-mentioned separation grating flush memory device, wherein carried out between the floating gate and the substrate by floating gate oxide layers
Isolation.
Above-mentioned separation grating flush memory device, wherein the insulating layer is to include oxidenitride oxide Sanming City
Control the ONO layer of structure.
Above-mentioned separation grating flush memory device, wherein pass through tunnelling oxygen between the erasing grid and the substrate, control gate
Change layer to be isolated, and the word line structure is isolated with the substrate, control gate by wordline oxide layer.
Above-mentioned separation grating flush memory device, wherein the source doping region, drain doping region, erasing grid, word line structure
With metal silicide is provided at the top of control gate.
The present invention forms floating gate and control gate by self aligned method, for the traditional technology that compares, reduces life
Cost is produced, entire process flow is also easier to control；Floating gate prepared by the present invention is provided in substrate, and in floating gate two sides
Side wall in form source doping region and drain doping region, therefore form between source doping region and drain doping region vertical
Channel region in floating gate two sides, this improves channel length to a certain extent, so that the carrier in substrate is easier to penetrate
Oxide layer enters floating gate, improves carrier mobility, and effectively inhibits the leakage current of channel；And it is further, due to
By floating gate preparation in substrate, therefore for the traditional technology that compares, the whole height of storage unit is effectively reduced, from
And its compatibility with logic process is improved, and provide foundation to further decrease device area.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, the present invention and its feature, outer
Shape and advantage will become more apparent upon.Identical label indicates identical part in all the attached drawings.Not deliberately proportionally
Draw attached drawing, it is preferred that emphasis is show the gist of the present invention.
Fig. 1 is the structure chart of separate gate flash memory in the prior art；
Fig. 2 a-2k is the flow chart of preparative separation flash memory in grating in the prior art；
Fig. 3 a~3o is a kind of flow chart of preparative separation gate flash memory device provided by the invention.
Specific embodiment
Further exemplary explanation is made to a specific embodiment of the invention with reference to the accompanying drawing, it is notable that
The listed grade examples should be understood as not that uniquely these embodiments are only used without constituting specifically limit as illustrating
System.
In one alternate embodiment, according to spirit of that invention, in self aligned method, to prepare depositing with separate gate
Memory device, the specific steps are as follows:
It executes step A: a semiconductor substrate 100 being provided, is sequentially depositing liner oxygen from bottom to top in 100 upper surface of substrate
Change layer 101 and dielectric layer 102, to have the lithography and etching technology that the usual skill in this field understands, to cushion oxide layer 101
Patterned process is carried out with dielectric layer 102, is sequentially etched dielectric layer 102 and cushion oxide layer 101, in dielectric layer 102 and liner
In oxide layer 101 formed several groups opening pair, and using with patterns of openings cushion oxide layer 101 and dielectric layer 102 as quarter
Exposure mask is lost, further etched substrate 100 is wherein forming at least one set of or greater number group groove pair, such as Fig. 3 a-3b institute
Show.Each group of groove is to should include two adjacent but spaced apart grooves.
Preferably, which is silicon substrate but is not limited to simple silicon substrate, in some other embodiments
In, which can be SOI wafer.Dielectric layer 102 is silicon nitride (SiN), and 101 He of cushion oxide layer is prepared on substrate 100
The associated process steps of dielectric layer 102 are well known in the art, and it will not be described here.
The specific steps of above-mentioned patterned process are as follows: in one layer photoresist of upper surface spin coating (PR) of dielectric layer 102, it
It is exposed developing process by a mask plate afterwards, forms patterns of openings in the photoresist, then utilizing has patterns of openings
Photoresist is that etch mask performs etching downwards into substrate 100, and then several grooves pair are formed in substrate 100.Exist simultaneously
It, can also be in advance in the upper table of dielectric layer 102 in order to further ensure the precision and inhibition reflection of photoetching in the embodiment of the present invention
Face coats one layer of bottom anti-reflection layer (BARC), later spin coating photoresist again, and then reduces in exposure process due to light
The phenomenon that reflection is to cause to photoresist overexposure, it should be appreciated to those skilled in the art that coating bottom anti-reflective
The step of layer is optional way, in practical applications can also directly spin coating photoresist overlay in the upper surface of dielectric layer 102, it is right
The present invention has no effect on.Patterned process described below and the patterned process in this step are essentially identical, therefore under
Text is no longer described in detail.
It executes step B: preparing floating gate 104 ' in the trench groove to be filled, later in 104 ' top of floating gate floating gate
According to being sequentially sequentially prepared insulating layer 105 and control gate 106 ' from bottom to up.As shown in Fig. 3 c-3h.
Specifically, in stepb, the step of preparing floating gate 104 ', includes:
Step B1: one layer of floating gate oxide layers 103 are prepared on the surface of groove exposure.Preferably, in the embodiment of the present invention
In, optional high-temperature furnace tube process to form floating gate oxide layers 103 on the surface of groove exposure.Under the high temperature conditions, it is passed through
Oxygen reacts and then generates floating gate oxide layers 103 with the silicon generation of flute surfaces exposure in substrate 100, floating for what is be subsequently formed
Being isolated between grid 104 ' and substrate 100.
Step B2: the first polysilicon layer 104 of deposition is covered on dielectric layer 102 and fills out each groove and opening
It fills, the first polysilicon layer 104 is etched back later, retain the first polysilicon layer 104 being located in groove and be used as floating gate 104 ',
As shown in Fig. 3 c- Fig. 3 d.One optional but simultaneously embodiment is without limiting, and the present invention is formed by floating gate 104 ' completely will lining
Groove in bottom 100 is filled completely, and the top of floating gate 104 ' is not higher than the upper surface of substrate 100.
Specifically, in stepb, the step of preparing control gate 106 ', is as follows:
Step B3: one insulating layer 105 of deposition is covered on the upper table of 104 ' top of floating gate and opening sidewalls and dielectric layer 102
Face continues to deposit the upper surface that the second polysilicon layer 106 is covered on insulating layer 105 later, while second polysilicon layer 106 will
Opening in dielectric layer 102 and cushion oxide layer 101 is filled.Above-mentioned insulating layer 105 is IPD (Inter-poly
Dielectric, dielectric between polycrystalline) layer, it is further preferred that the insulating layer 105 is to include oxidenitride oxide
ONO (oxide-nitride-oxide) layer of sandwich structure.Select ONO three-decker as floating gate 104 ' and control herein
Insulating layer between grid 106 ', this is because the combination of oxide layer and base crystalline substance is good compared with nitration case, and nitration case is placed in the middle, so three layers
Structure complementary can lack, and be conducive to promote device performance.Simultaneously it will be appreciated by those skilled in the art that in the present invention, floating gate
It is only a kind of preferable mode that ono dielectric layer is selected between 104 ' and control gate 106 ', also be can be selected according to production requirement common
Oxide layer or other isolation materials floating gate 104 ' and control gate 106 ' are isolated, it will not be described here.
Step B4: be thinned the second polysilicon layer 106 make its top with flushed at the top of dielectric layer 102.In the present invention, it can adopt
With polysilicon etch back (poly recess) or CMP (Chemical Mechanical Polishing, chemically mechanical polishing) work
Skill come to the second polysilicon layer 106 carry out reduction processing, can specifically carry out according to the actual situation selection using which kind of technique come pair
Second polysilicon layer 106 carries out thinned, and processing mode is not limited only to above-mentioned polysilicon etch back and CMP processing,
It will not go into details for this.
Step B5: removal medium layer 102, cushion oxide layer 101 and partial insulative layer 105, and retain and be located at more than second
The insulating layer 105 of 106 bottom of crystal silicon layer, the side wall of the second polysilicon layer 106 is exposed completely, remaining insulating layer
105, to the isolation between floating gate 104 ' and control gate 106 ', form structure shown in Fig. 3 h.
In addition, after the side wall of the second polysilicon layer 106 to be carried out to exposure, further including execution one can in step B5
Selection of land for example high-temperature oxydation repair process technique (re-oxidation), such as can repair and remove the second polysilicon layer 106
When the insulating layer 105 of two sides, process is easy the insulating layer to 106 bottom of the second polysilicon layer 106 and the second polysilicon layer
It is damaged caused by 105, especially exposed surface.
It executes step C: carrying out the first ion implantation technology, the substrate 100 between two grooves of each group of groove pair
Interior formation source doping region (source).Specifically, one layer photoresist 107 of coating is covered on the surface of device, exposed later
Photo development processes remove part photoresist 107,100 surface of substrate between two grooves of each group of groove pair are exposed,
Ion implantation technology, and then source doping region in the substrate between two grooves in each group of groove pair are carried out later, such as
Shown in Fig. 3 i, photoresist is removed later.
Execute step D: the gap preparation erasing grid between the control gate of two the top of the groove of each group of groove pair
109 ', and word line structure 109 " is formed away from the other side of erasing grid 109 ' in each control gate, later in word line structure
109 " side wall prepares side wall 110.As shown in Fig. 3 j-3n.
Specifically, in the step D following steps need to be executed:
Step D1: deposition tunnel oxide 108 is covered the surface of substrate 100 and the exposure of control gate 106 ', and
Groove carries out the ion implantation technology of wordline threshold voltage adjustments in the other side substrate 100 of source doping region, with adjustment
Threshold voltage (the threshold voltage, V of word line devicet)。
During depositing tunnel oxide, due to forming source doped with ion in the substrate in each group of groove pair
Pole doped region, therefore 108 thickness of tunnel oxide deposited above source doping region compares that other regions are higher, this has
Conducive to high voltage bearing erasing operation, the breakdown characteristics of tunnel oxide are improved.
When carrying out the ion implantation technology of wordline threshold voltage adjustments, photoetching process is first carried out, using photoresist by source
Pole doped region and control gate 106 ' positioned at source doping region two sides are covered, and carry out ion implanting later.Art technology
Personnel should be appreciated that the ion implantation technology of the wordline threshold voltage adjustments is optional technical solution, according to actual needs
Subsequent step can be directly carried out, the present invention is had no effect on after depositing tunnel oxide 108 without ion implanting.
Simultaneously as shown in Fig. 3 j.
Step D2: removing the tunnel oxide 108 that each groove deviates from 100 surface of other side substrate of source doping region,
And wordline oxide layer 108 ' is formed on the surface of exposure due to removing tunnel oxide in substrate.In the process, using step
It is covered on the photoresist at the top of control gate 106 ' in rapid D1 as etch mask, part tunnel oxide 108 is removed with etching,
And then it reduces production cost and shortens process cycle.
Step D3: deposition third polysilicon layer 109 is covered on 108 on wordline oxide layer 108 ' and tunnel oxide, is subtracted
Thin third polysilicon layer 109 make its top with flushed at the top of control gate 106 '；Third polysilicon layer 109 is because being thinned in gap
Retained and spaced apart and formation isolated part, as erasing grid 109 '.As shown in Fig. 3 k-3l.
Step D4: the part third polysilicon layer 109 and wordline oxide layer 108 ' on the outside of control gate 106 ' are removed, control is formed
Word line structure 109 " of the grid 106 ' processed away from the other side of erasing grid 109 '.In this step, it is covered using patterned photoresist
It is placed on third polysilicon layer 109, and is that etch mask is sequentially etched removal control gate 106 ' outside using patterned photoresist
A part of third polysilicon layer of side and wordline oxide layer below form word line structure 109 ", as shown in figure 3m.Meanwhile
It will be appreciated by those skilled in the art that being performed etching using patterned photoresist for etch mask and defining word line structure
While 109 ", the source-end region (in combination with shown in Fig. 1) that certain specific needs are drawn can be also opened, i.e. removal part source electrode is mixed
A part erasing grid 109 ' in miscellaneous area and it is located at the tunnel oxide 108 being removed below erasing grid 109 ', and then by source
Pole doped region gives exposed, forms metal interconnection structure in the subsequent process, although do not showed that in figure by source doping region into
Row exposure, but the technical characteristic is known to those skilled in the art, therefore has no effect on protection scope of the present invention.
Step D5: side wall 110 is prepared in the outside side wall of word line structure 109 ".One of them optional technical solution is,
Before the formation of side wall 110, a LDD (Lightly Doped Drain, lightly doped drain) injection work is also optionally carried out
Skill, to weaken drain region electric field and improve thermoelectron degradation effect.After the completion of above-mentioned steps, structure shown in Fig. 3 n is formed.
It executes step E: carrying out the second ion implantation technology, in other side substrate 100 of the groove away from source doping region
It is formed drain doping region (drain).
After the completion of above-mentioned steps, continue self-registered technology and metal interconnection technique and back-end process (BEOL).
Specifically, carrying out self-registered technology includes: to deposit one layer of SAB (metal silicide barrier layer) layer first and carry out pattern
Change processing removes part SAB layers to expose source doping region, drain doping region, word line structure 109 ", control gate 106 ' and wipe
Except the top of grid 109 '；Continue to deposit one layer of metal layer and be made annealing treatment, makes the metal layer of deposition and the polysilicon of contact
Reaction is generated, in source doping region, drain doping region, word line structure 109 ", control gate 106 ' and the top shape for wiping grid 109 '
At metal silicide (Salicide), remaining metal layer and SAB (salicide block, silicide barrier layer) are removed later
Layer.In this step, it is preferred that the metal layer of deposition is preferably Ti or Ni, and removes residue by wet-cleaning after annealing
Metal layer and SAB layers.
Specifically, carrying out metal interconnection technique includes: deposition ILD (Interlayer dielectric layer, interlayer
Dielectric layer) layer 115, patterned process is carried out, forms several through-holes 116 in ILD layer 115 to expose metal silicide, into
Row is electroplated and fills metal in each through-hole 116, as metal interconnection structure.
Since present invention employs methods produced above, by the way that floating gate to be placed in substrate, and source-drain electrode is then located at floating gate
Two sides, therefore constitute the channel perpendicular to floating gate two sides, the length of channel effectively increased, so that the current-carrying in substrate
Son, which is easier to penetrate oxide layer, enters floating gate, improves carrier mobility, and effectively inhibit the leakage current of channel；Simultaneously
The present invention etches in the substrate form groove after, directly by depositing and grinding and can be formed among floating gate, control gate and the two
Insulating layer, realized without photoetching process, reduce technology difficulty, while reducing production cost.
Simultaneously the present invention provides a kind of separation grating flush memory device, can refer to shown in Fig. 3 o, the separation grating flash memories
Part includes: substrate 100, has several groups groove pair in substrate 100.Floating gate 104 ', floating gate are filled in each groove
It is isolated between 104 ' and substrate 100 by a floating gate oxide layers 103, a control gate is provided on floating gate 104 '
106 ', and be isolated between floating gate 104 ' and control gate 106 ' by insulating layer 105, insulating layer 105 is located at the upper of substrate 100
On surface.Floating gate 104 ' provided by the present invention be located at substrate 100 in, and control gate 106 ' then be located at substrate 100 it
On.
Preferably, above-mentioned insulating layer 105 is the ONO layer comprising oxidenitride oxide sandwich structure.Together
When select the ono dielectric layer to be only it will be appreciated by those skilled in the art that in the present invention, between floating gate 104 ' and control gate 106 '
A kind of preferable mode, also can be selected according to production requirement common oxide layer cross other isolation materials come by floating gate 104 ' and control
Grid 106 ' processed are isolated, and it will not be described here.
It is formed with source doping region in substrate 100 between two grooves of each group of groove pair, and deviates from source in groove
Drain doping region is formed in the other side substrate 100 of pole doped region.
Gap between the control gate 106 ' of two the top of the groove of each group of groove pair is formed with erasing grid 109 ', and
The side of erasing grid 109 ' is provided with word line structure 109 " in each control gate 106 ', word line structure 109 " is away from erasing grid
The side wall of the 109 ' other side is covered with side wall 110.In the present invention, above-mentioned erasing grid 109 ' and substrate 100, control gate
It is isolated between 106 ' by tunnel oxide 108, and word line structure 109 " and substrate 100, control gate 106 ' pass through wordline
Oxide layer 108 ' is isolated.Herein it is required that wordline oxide layer 108 ' is to remove each groove by etching away from source electrode
After the tunnel oxide on 100 surface of other side substrate of doped region, and in substrate due to removing tunnel oxide the surface of exposure
Upper redeposited layer of oxide layer.
Further, device surface provided by the present invention is also covered with an interlayer dielectric layer 115, in the interlayer dielectric layer
It is provided with several through-holes 116 in 115, is interconnected filled with copper as metal in each through-hole 116, the bottom of through-hole 116 is located at source electrode
On doped region, drain doping region, erasing grid 109 ', word line structure 109 " and control gate 106 ', and the bottom of each through-hole 116 is equal
It is provided with metal silicide.
In conclusion being had the advantages that due to present invention employs technical solution as above
1, self aligned thought is utilized by integrating Flash framework and traditional CMOS technology in the present invention
Floating gate and control gate are formed, i.e., without forming floating gate and control gate by etching, passes through deposition, flatening process, Ji Keshi
The formation of existing floating gate and control gate, compatible traditional CMOS technology, the traditional technology that compares reduce technology difficulty, can be further
Reduce the critical size of device (unit component), and reduces production cost.
2, since the floating gate that flush memory device prepared by the present invention is included is to be set in substrate, and floating gate two sides are divided
Not Xing Cheng source doping region and drain doping region, therefore the channel region between source doping region and drain doping region is perpendicular to lining
Floating gate two sides in bottom, this is conducive to improve channel length so that the carrier in substrate be easier to penetrate oxide layer enter it is floating
Grid improve carrier mobility, and effectively inhibit the leakage current of channel；Anti-interference is also relatively strong simultaneously.
3, it due to the application prepared by floating gate in groove in the substrate, floating gate, the control gate for the traditional flash that compares are equal
Be arranged in substrate, therefore the whole height of storage unit prepared by the present invention can decrease, thus improve its with
The compatibility of logic process.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, devices and structures not described in detail herein should be understood as gives reality with the common mode in this field
It applies；Anyone skilled in the art, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this is not affected the essence of the present invention.Therefore, anything that does not depart from the technical scheme of the invention, foundation
Technical spirit of the invention any simple modifications, equivalents, and modifications made to the above embodiment, still fall within the present invention
In the range of technical solution protection.
Claims (13)
1. a kind of method of preparative separation gate flash memory device, which comprises the following steps:
Step A: a substrate is provided, surface is successively covered with cushion oxide layer and Jie according to sequence from low to uper part over the substrate
Matter layer；
Patterned process is carried out, several groups opening pair is formed in the dielectric layer and the cushion oxide layer, is opened using described
Mouth is to the substrate is etched, to form several groups groove pair in the substrate；
Step B: floating gate is prepared in the groove groove to be filled；
According to being sequentially sequentially prepared insulating layer and control gate from bottom to up at the top of the floating gate；
Step C: the first ion implantation technology is carried out, source electrode is formed in the substrate between two grooves of each group of groove pair and mixes
Miscellaneous area；
Step D: the gap preparation erasing grid between the control gate of two the top of the groove of each group of groove pair, and each
The control gate forms word line structure away from the other side of the erasing grid, prepares side in the side wall of the word line structure later
Wall；
Step E: carrying out the second ion implantation technology, is formed in other side substrate of the groove away from the source doping region
Drain doping region.
2. the method as described in claim 1, which is characterized in that in stepb, the step of preparing the floating gate includes:
Step B1: one layer of floating gate oxide layers are prepared on the surface of groove exposure；
Step B2: the first polysilicon layer of deposition is covered on dielectric layer and is filled each groove and opening, more than first
Crystal silicon layer is etched back, and retains the first polysilicon layer being located in groove as floating gate.
3. the method as described in claim 1, which is characterized in that in stepb, the step of preparing the control gate includes:
Step B3: one insulating layer of deposition is covered on the floating gate top and the opening sidewalls and the dielectric layer upper surface,
Continue the second polysilicon layer of deposition and be covered on the insulating layer upper surface, and the opening is filled；
Step B4: the second polysilicon layer, which is thinned, to be made to flush at the top of its top and the dielectric layer；
Step B5: removal medium layer, cushion oxide layer and partial insulative layer, and retain and be located at the exhausted of the second polysilicon layer bottom
Edge layer.
4. method as claimed in claim 3, which is characterized in that the insulating layer is to include oxidenitride oxide three
The ONO layer of Mingzhi's structure.
5. method as claimed in claim 3, which is characterized in that in step B5, after removing insulating layer described in part, also wrap
It includes and implements a step of high temperature is repaired, and then repair when removing the insulating layer to second polysilicon layer and positioned at second
It is damaged caused by the insulating layer of polysilicon layer bottom.
6. the method as described in claim 1, which is characterized in that the specific steps of step D are as follows:
Step D1: deposition tunnel oxide is covered the surface of substrate and control gate exposure, and deviates from the source in groove
The ion implantation technology of wordline threshold voltage adjustments is carried out in the other side substrate of pole doped region, to adjust wordline threshold voltage；
Step D2: each groove is removed away from the tunnel oxide of the other side substrate surface of the source doping region, and is being served as a contrast
Bottom surface of exposure due to removing tunnel oxide forms wordline oxide layer；
Step D3: deposition third polysilicon layer is covered on wordline oxide layer and remaining tunnel oxide, and it is more that third is thinned
Crystal silicon layer make its top with flushed at the top of the control gate；
Third polysilicon layer is retained in the gap because being thinned and is spaced apart due to the isolated part that is formed, as the wiping
Except grid；
Step D4: removing the part third polysilicon layer and wordline oxide layer on the outside of control gate, forms the control gate back
The word line structure of the other side from the erasing grid；
Step D5: side wall is prepared in the side wall of the word line structure.
7. method as claimed in claim 6, which is characterized in that in the ion implantation technology for carrying out wordline threshold voltage adjustments
Before, photoetching process is first carried out, using photoresist by the source doping region and positioned at the control gate progress of source doping region two sides
Covering.
8. method as claimed in claim 6, which is characterized in that forming the control gate away from the other side of the erasing grid
Word line structure the step of in, using patterned photoresist overlay on third polysilicon layer, and exposed in the photoresist
A part of third polysilicon layer on the outside of control gate, and be that etch mask is sequentially etched removal control using patterned photoresist
A part of third polysilicon layer on the outside of grid and wordline oxide layer below.
9. method according to claim 8, which is characterized in that the method also includes: after forming drain doping region, in source
Metal silicide is prepared at the top of pole doped region, drain doping region, word line structure, control gate and erasing grid.
10. a kind of separation grating flush memory device characterized by comprising
Substrate has several groups groove pair in the substrate；
Floating gate and control gate, the floating gate are located in the groove, and the control gate is located on the floating gate and passes through one absolutely
Edge layer is isolated with the floating gate, and the insulating layer is located on the upper surface of substrate；
Gap between the control gate of two the top of the groove of each group of groove pair is formed with erasing grid, and in each control
Grid are provided with word line structure away from the other side of the erasing grid；
It is formed with source doping region in substrate between two grooves of each group of groove pair, and deviates from the source in the groove
Drain doping region is formed in the other side substrate of pole doped region；
The erasing grid are isolated between the substrate, control gate by tunnel oxide, and the word line structure and institute
State substrate, control gate is isolated by wordline oxide layer.
11. separation grating flush memory device as claimed in claim 10, which is characterized in that lead between the floating gate and the substrate
Floating gate oxide layers are crossed to be isolated.
12. separation grating flush memory device as claimed in claim 10, which is characterized in that the insulating layer is to include oxide-
The ONO layer of Nitride Oxide sandwich structure.
13. separation grating flush memory device as claimed in claim 10, which is characterized in that the source doping region, drain implants
Metal silicide is provided at the top of area, erasing grid, word line structure and control gate.
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| CN108735751B (en) * | 2018-04-26 | 2020-11-03 | 上海华力集成电路制造有限公司 | Floating gate memory cell and preparation method thereof |
| CN110112132B (en) * | 2019-04-28 | 2021-05-07 | 上海华虹宏力半导体制造有限公司 | Split-gate memory and manufacturing method thereof |
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