TW587282B - Method for improving the performance of flash memory by using microcrystalline polysilicon film as a floating gate - Google Patents

Abstract

This invention provides a method for forming polysilicon by using silane with introducing hydrogen, such that polysilicon is microcrystalline. This microcrystal polysilicon can be applied to floating gate of flash memory to improve the character of flash memory.

Description

587282 V. Description of the invention (1) 5 _ 1 Field of invention: One method that can be used in the Fangguan is the special recollection of the gender, the flash of the remembering style, the flashing of the quick style, and the rapid advancement of the USul BhJ- the gate is placed in the floating barrier There are film-type shattered crystal hair micro-costs. 1PC- Species back bright hair 2 1 5 The row of the power block and the effect area are always idle, and the block and the floating area are included in the memory for a while. The package group records a group of cells, including a regular package, a single cell, a cell, and a crystal, which is equal to 0. The number of storage types recorded by the crystal charge flash memory electric memory is multiplexed into a series of crystals. The floating data stored in the gate are removed from the electric fixed-gate decisive process that is charged by CLP's cell, and the wiper wipes or wipes the crystals that can be stored in the area. The float operation of each gate is floating. The first figure shows a cross-sectional view of a typical memory cell 5 as if it is used in flash memory. The memory cell 5 includes a source 60 area and a drain 70 area, and the source 60 and the end 70 are separated by a channel area 80. The memory cell 5 further includes a floating gate 30 formed by a first polycrystalline silicon layer, a control gate 50 formed by a second polycrystalline silicon layer, and the floating gate 30 and the control gate 50 are formed by a The inner polycrystalline dielectric layer 40 is isolated, and the area between the floating gate 30 and the channel 80 is separated by a thin oxide layer (passage oxide layer) 20 with a thickness of about 100 angstroms. The second figure shows a floating gate formed by using a polycrystalline silicon layer 84.

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587282 V. Description of the invention (2) Material 8 2 Cross-section view on the oxide layer. The polycrystalline silicon layer 8 4 is formed by depositing polycrystalline silicon on the surface of the substrate 8 2 by using a low pressure chemical vapor deposition method at a temperature of about 600 ° C and using silane (S i Η 4) as a material. The surface irregularity of the polycrystalline silicon layer 84 is caused by large columnar crystals. At the same time, it is difficult to obtain a good pattern transfer pattern on this surface irregularity, which causes the interior of the photoresist layer to be caused by the graininess of the polycrystalline silicon layer 84 Significant deformation and non-uniform reflection during the pattern transfer process, non-uniform reflection of the photoresist layer result in poor etching patterns, and the residue of the polycrystalline silicon layer 25 is easily generated. The third figure shows a cross-sectional view of another polycrystalline silicon layer 88 formed as a floating gate on a substrate 86 such as a tunnel oxide layer. The polycrystalline silicon layer 88 is formed on the surface of the substrate 86 by using an i-pressure chemical vapor deposition method at a temperature of about 550 ° C. Depositing silicon at this low temperature produces amorphous silicon because grains cannot form at this low temperature. This amorphous silicon is then recrystallized by exposure to a temperature of about 600 ° C. The final recrystallized structure is shown in the third figure, which has large crystal grain formation. However, the polycrystalline silicon layer 88 of the third figure also has the disadvantage of surface irregularities as shown in the second figure. The large grain size in the polycrystalline silicon layer 88 may reduce the grain boundary density in the film. In addition, because the polycrystalline silicon layer 88 is deposited at a low temperature, the deposition rate is relatively reduced, resulting in a slow output cycle. The flash memory ’s N 0 r d h e i π mode, such as the layer ’s tunneling oxide interlayer, is usually 100 Angstroms thick.

F The thinning of the oxygen oxidative wear is removed by the regular wear and tear formula, and the storage or storage of a storage capacitor is faster than the method of reconciliation. Body memory

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V. Description of the invention (3) The hot carrier is penetrated to% through the channel. The flash memory uses hot carriers to write 'pre-alarm', and stores the positive charge in the floating gate, the source is connected to the ground Y to enter the action, and the control gate and the drain are connected to the gate. The erasing action often uses F 0w 1 er-erasing program. ^: High voltage is occasionally applied to complete the erasing of the memory cell. It means that a higher current passes through the cell for a shorter period of erasing speed. When the silicon floats on the gate, it will cause ^ Gadolinium oxide layer. . When large over-erased areas with large grains are used, the starting voltage (Vt) of the / ^ range is distributed. If there is a tail-like distribution and a large f-start voltage distribution range, the distribution of the initial charge 1 will be related to the large crystal: more than 1;:;, and the other-the 1-wide erasure of the silicon. In the traditional flash-style recording of # 恃 #, the use of large-crystalline polycrystalline work π as a floating gate in the process of the U.S. system has a lot of shortcomings. Disadvantages of the membrane, such as causing too fast erasing action (p

Erase) or overwrite (Fast pr0gram), a wide starting voltage st with tail-like distribution, reduced performance of the tunneling oxide layer, more polysilicon, and poor etching appearance, resulting in polysilicon residues, etc. . In view of the above-mentioned background of the invention, the present invention provides a number of shortcomings for improving the traditional flash memory system by using a floating gate of a microcrystalline silicon memory cell. raw

Page 6 587282 V. Description of the invention (4) Another object of the present invention is to use a microcrystalline silicon floating gate to improve the wider erased initial voltage distribution of the memory cell and the problem of having tail-like distribution. Another object of the present invention is to improve the erasure of memory cells by using a microcrystalline silicon floating gate. · Another object of the present invention is to use a microcrystalline silicon floating gate to promote the performance of a tunneling oxide layer of a memory cell. Another object of the present invention is to use a microcrystalline silicon floating gate to promote the usability of a flash memory. Another object of the present invention is to improve the etching appearance of a floating gate by using microcrystalline silicon. Another object of the present invention is to reduce the resistance of a floating gate by using microcrystalline silicon. The present invention discloses that a memory cell uses microcrystalline silicon as the material of the floating gate. The low electronic affinity is used in flash memory. Characteristics, the microcrystals are more prominent with low electron affinity. The use of a low electron affinity material as a floating gate provides a lower barrier to the tunneling oxide interface, and lowering the tunneling distance generally increases the feasibility of electron tunneling. Use a low electron affinity floating gate to solve

Page 7 587282 V. Description of the invention (5) These problems are solved. Therefore, low barriers promote the escape of electrons or removal by penetration. The lower voltage required for low barriers, similar to the tunneling distance, acts as an electronic wipe, which results in faster wipe time and reduced damage. In the present invention, a microcrystalline silicon floating gate is used to improve the performance of a flash memory. The method is to provide a substrate, wherein the substrate includes a source region and a drain region, and is separated by a channel region. A tunneling oxide layer is formed on the substrate. A microcrystalline silicon layer is formed on the tunneling oxide layer as a floating gate. The microcrystalline silicon film is formed by using a low pressure chemical vapor deposition method, selecting silane or disilane, and introducing hydrogen gas at the same time. An inner polycrystalline dielectric layer is formed on the microcrystalline silicon layer. A polycrystalline silicon layer is formed on the inner polycrystalline dielectric layer as a control gate. Finally, the polycrystalline silicon layer, the inner polycrystalline dielectric layer, the microcrystalline silicon layer, and the tunneling oxide layer are etched to form a gate to form a memory cell. 5-4 Detailed description of the invention: The present invention will be disclosed in detail with the illustrations as follows. In this embodiment, a microcrystalline stone evening film (micr 〇crysta 1 1 ine ρ ο 1 ysi 1 ic ο η fi 1 m ) As a floating gate to promote the performance of flash memory. A cross-sectional view of the memory cell 100 shown in the fourth figure, wherein the floating gate 120 formed by a microcrystalline silicon film replaces the floating gate of the polycrystalline silicon film of the prior art. The memory cell 100 includes a source region 150 and a drain region 160, and the source 150 and the drain region 160 are separated by a channel 170 region. Memory cell 1 0 0 more pack

587282 V. Description of the invention (6) Including a floating gate 1 2 0 formed by a microcrystalline silicon film, a control gate 1 4 0 formed by a polycrystalline silicon layer, a floating gate 1 2 0 and a control gate 1 4 0 An internal polycrystalline dielectric layer 130 such as an oxygen-nitrogen-oxygen layer (ONO layer) is used for isolation, and the area of the floating gate 120 and the channel 170 is separated by a gate dielectric layer 110 such as silicon oxide. The inner polycrystalline dielectric layer 130 and the gate dielectric layer 110 are insulating layers, and the gate dielectric layer functions as an electron tunneling oxide layer. · The fifth figure shows an enlarged view of the cross section of the floating gate using the microcrystalline silicon film 1 7 4 in this embodiment. The microcrystalline silicon film 1 7 4 is formed on a substrate 1 7 2 and the microcrystalline silicon film 1 7 4 Control the film formation by introducing hydrogen into the silicon deposition reaction chamber. In this embodiment, a crystalline silicon film is deposited by using silane as a material and hydrogen is introduced simultaneously, and another embodiment is used to deposit a microcrystalline silicon film by using silane as a material and simultaneously introduced hydrogen. The average grain size of microcrystalline silicon film 174 is about 500 angstroms to 100 angstroms. The grain size of microcrystalline broken film 174 is defined by the average diameter of the crystal grains. It cannot have a uniform shape, but has an average diameter of about 500 Angstroms to 100 Angstroms. Low pressure chemical vapor deposition methods or other deposition methods can be applied to this technology to deposit thin films. In this embodiment, the parameters using the low-pressure chemical vapor deposition method are: pressure control of about 200 ~ 4 0 0 Torr, temperature control of about 7 0 ~ 7 5 0 ° C, and the flow ratio of hydrogen and nitrogen is about 5 ~ 60% (5 ~ 60% hydrogen / 1 0% (hydrogen + nitrogen)). The floating gate can be formed by a process such as pattern transfer and etching in the method for forming a polycrystalline silicon floating gate similar to a conventional device.

587282 V. Description of the invention (7) The main reaction equation is SiH4_5 polycrystalline silicon film, the surface area of which is high with silicon atoms is 1 2 + 2H2. This leads to large grains and growth rates. For two, the rate is better than the mysterious nucleation rate. Therefore, when the nucleation rate = growth rate, 』: two sized grains are formed. The Trent diffusion rate will result in a noticeable reduction in grain size in the Shi Xi film " 4 of this embodiment and the second figure. Doping: =: =, the grain boundary density of column M is significantly higher than that of polycrystalline silicon. The grain boundary density of polycrystalline silicon film is doped with two, and the dispersion can be improved. The surface close to the microcrystalline silicon film 1 74 can easily penetrate the microcrystalline silicon film 17 4 along the high-density grain boundaries. As a result, the dopant concentration of the microcrystalline silicon film 1 74 promotes the conductivity of the microcrystalline silicon film 1 74 and has more electric field uniformity than the recrystallized amorphous silicon film shown in the second figure. On the other hand, compared with the conventional polycrystalline silicon film shown in the second figure, the microcrystalline silicon film 1 74 reduces the average grain size and promotes the flattening of the surface of the microcrystalline film 1 74. The miniaturization of the grain size of the microcrystalline silicon film 174 is apparent in the present invention, and the effect on the film surface is obvious. In addition, when the microcrystalline silicon film 174 process is adjusted to increase or decrease the average grain size, the surface irregularities of the film also increase or decrease, respectively. By flattening the surface of the microcrystalline silicon film i 74, p. 10 587282 V. Description of the invention (8) The deviation of the internal thickness of the photoresist in the lithography process is also relatively reduced, which is similar to the traditional polycrystalline silicon shown in the second figure Compared with the film, its reflection achieves more uniformity, improving the resolution of the gate edge. Finally, it can be described in the tunneling oxide layers 180 and 180A by "oxidation gap" (ο X ideva 1 1 ey), as shown in Figures 6A and 6B. In the traditional process, high-concentration phosphorus is doped Miscellaneous in the silicon oxide region, the oxidation gap 194 is formed at the interface of the polycrystalline silicon grains 192. All polycrystalline silicon grains 192 are relative to the total length of the oxidized gaps 192. When using polycrystalline silicon with large grain sizes, Only a few grains exist in one erasing unit. For example, when there are only five polycrystalline silicon grains in one erasing unit, each of the polycrystalline silicon grains 192 accounts for 20% of the erasing action, so one The polycrystalline silicon grain 1 9 2 has a large error value in the erasing speed, and has a wide erase starting voltage distribution. Second, in this embodiment, as shown in FIG. 6B, a large number of oxidation gaps 1 9 4 A can indeed achieve the same erasure speed in the unit cell of each memory array. On the other hand, using microcrystalline silicon with small grains of 192 A, there are many grains of 192 A in one erasure. In the unit, for example, when fifty microcrystalline silicon grains 1 9 2 A exist one In the erasing unit, the erasing action of each microcrystalline silicon grain 192 A is only 2%. Therefore, each grain of 192 A has the same erasing speed and can achieve a narrow erasing. The erasing area with a large starting voltage distribution range contains a large number of microcrystalline silicon grains 192 A, and a uniform erasing speed and a narrow-range erasing starting voltage distribution can be obtained.

587282 V. Description of the invention (9) The gate voltage directly determines the strength of the gate current, and this gate current is the most important factor that affects the breakdown of the dielectric value of the tunneling oxide layer in the program and causes collapse. In this embodiment, a microcrystalline silicon floating gate and a prior art polycrystalline silicon floating gate are respectively used to test charge-to breakdown (Qbd) and electron trapping rate. As shown in Table 1, the thickness of the tunneling oxide layer using microcrystalline silicon and polycrystalline silicon is the same as measured by the CV method and the FV method, and each data in the table is an average value obtained by testing three times per wafer. As shown in the seventh figure, the pillar A is a tunneling oxide layer using a microcrystalline silicon floating gate, and the pillar B is a tunneling oxide layer using a polycrystalline silicon floating gate. As can be seen in the figure, the present invention uses a microcrystalline silicon floating gate. The gate tunneling oxide layer has a higher electron injection efficiency and a larger breakdown voltage value. In addition, as shown in the eighth figure, the C pillar is a tunneling oxide layer using a microcrystalline silicon floating gate, and the D pillar is a tunneling oxide layer using a polycrystalline silicon floating gate. It can be seen in the figure that the present invention uses a microcrystalline silicon The floating gate has a lower electron capture rate for its tunneling oxide layer, which can obtain better reliability of the flash memory device. The use of smaller-sized microcrystalline silicon has most of the grains present in the floating gate. Using the floating gate of small-sized grains can reduce the electron capture rate of the tunneling oxide layer, so it can promote the function of flash memory Sex. The above are only the preferred embodiments of the present invention, and are not intended to limit the scope of patent application of the present invention; all others do not depart from the disclosure of the present invention.

Page 12 587282 V. Description of the invention (10) Equivalent changes or modifications under the spirit of the invention shall be included in the scope of the patent application as described below. -Table ^ 1 shows the test data of the thickness, breakdown voltage, and electron capture rate of the oxidized oxide layer of the microcrystalline and polycrystalline floating gates. Membrane thickness (CV) Thickness (FV) Electron capture rate of breakdown voltage 104.6 103,6 22.04 0.033 4 104,6 103.6 21.66 0,027 11 104.8 103.6 13.82 0.028 12 104,6 103.6 14,14 0.031 13 use 104,6 103.6 14.74 0.031 14 use 104,8 103.6 14.94 0.032 15 more 104,6 103.6 14.47 0.031 16 Crystal 104.4 103.6 15.12 0,035 17 Shi Xi 104,8 103.6 16.34 0.037 18 Film 104,4 103.6 13.70 0.036 19 104.8 103,6 16.10 0.036 20 104.4 103,6 16,02 0,035 21 104.4 103.6 15.79 0.035

Page 587 282 Brief description of the diagram The first picture shows a cross-sectional view of a memory cell of the prior art; the second picture shows an enlarged cross-sectional view of a polysilicon film floating gate on a substrate; the third picture shows Shown is an enlarged cross-sectional view of a floating gate using a recrystallized silicon film on a substrate; the fourth figure is a cross-sectional view of a memory cell of the present invention, in which a microcrystalline silicon film is used as the floating gate.

The fifth figure is an enlarged cross-sectional view of the present invention using a microcrystalline silicon film as a floating gate on a substrate; the sixth diagram A shows a schematic diagram of an oxidation gap, showing large grains and less oxidation. Gap formation exists in a memory cell; Figure 6B shows a schematic diagram of an oxidation gap, with small grains shown in the figure and multiple oxidation gaps formed in a memory cell;

Figure 7 shows a comparison of the breakdown voltage of the tunneling oxide layer using microcrystalline and polycrystalline silicon floating gates. The eighth figure shows the use of microcrystalline and polycrystalline silicon floating gates.

Page 14 587282 The figure briefly illustrates the comparison diagram of the electron capture rate of the chemical layer. Representative symbols of main parts: 5 memory cell 10 substrate 2 0 tunneling oxide layer 3 0 polycrystalline silicon floating gate 4 0 polycrystalline dielectric layer 5 0 control gate 6 0 source 7 0 drain 8 0 channel 8 2 Substrate 8 4 Cylindrical polycrystalline silicon 8 6 Substrate 8 8 Recrystallized silicon 1 0 0 Memory cell I 0 5 Substrate II 0 Passive oxide layer 1 2 0 Microcrystalline silicon floating gate 1 3 0 Polycrystalline dielectric inside Layer 1 4 0 Control gate 1 5 0 Source 1 6 0 Drain

Page 15 587282 Simple illustration of the drawing 17 0 channel 1 7 2 substrate 1 7 4 microcrystalline silicon 1 7 6 substrate 1 7 8 source / drain 18 0 tunneling oxide layer «190 polycrystalline silicon

192 polycrystalline grains 1 9 4 oxidation gaps 176A substrate 1 7 8 A source / drain 1 8 0A tunneling oxide layer 1 9 0 A microcrystalline silicon 1 9 2 A microcrystalline grains 194A oxidation gaps A The column uses microcrystalline silicon floating gate breakdown oxide breakdown voltage B column uses polycrystalline silicon floating gate breakdown oxide breakdown voltage C pillar uses microcrystalline silicon floating gate penetration oxide electron capture rate D pillar uses polycrystalline silicon Electron capture rate of the through oxide layer of the floating gate

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Claims (1)

587282 Case No. 91114467 _ Case No. 91114467_year > Amendment on the qth of the month _ 6. Application for patent scope 1. A method for forming a microcrystalline silicon layer as a floating gate, comprising: providing a substrate with a gate An electric layer is formed on the substrate; the microcrystalline silicon layer is formed on the gate dielectric layer by decomposing silane and introducing argon gas, and the microcrystalline silicon layer is used as the floating gate. 2. A method of forming a microcrystalline silicon layer as a floating gate as described in the first patent application scope, wherein the method includes a low pressure chemical vapor deposition method. 3. The method of forming a microcrystalline silicon layer as a floating gate as described in item 2 of the scope of patent application, wherein the method includes temperature control of about 700 ~ 750 ° C. 4. The method of forming a microcrystalline silicon layer as a floating gate as described in item 2 of the patent application scope, wherein the method includes pressure control of about 200 Torr to 400 Torr. 5. The method of forming a microcrystalline silicon layer as a floating gate according to item 1 of the patent application scope, wherein the method includes a gas flow rate of hydrogen / (hydrogen + nitrogen) ratio of 5 to 60%. 6. The method of forming a microcrystalline silicon layer as a floating gate according to item 1 of the scope of the patent application, wherein the microcrystalline silicon substance may optionally include silane and ethane. 7. A method for promoting flash memory performance, comprising: forming a substrate, wherein the substrate includes a source region and a drain region and is isolated by a channel region; Page 17 587282 _Case No. 91114467_Amended in January _ Sixth, the scope of the patent application forms a tunneling oxide layer on the substrate; decomposes silane and introduces hydrogen to the tunneling oxide layer to form a microcrystalline silicon layer Forming an inner polycrystalline dielectric layer on the microcrystalline silicon layer; forming a polycrystalline silicon layer on the inner polycrystalline dielectric layer; and etching the polycrystalline silicon layer, the inner polycrystalline dielectric layer, and the microcrystalline silicon Layer and the tunneling oxide layer to form a gate structure. 8. The method for promoting flash memory performance according to item 7 of the scope of patent application, wherein the crystallite size of the microcrystalline silicon is about 500 angstroms to 100 angstroms. 9. The method for promoting flash memory performance according to item 7 of the patent application, wherein the microcrystalline silicon layer is formed by a low pressure chemical vapor deposition method. 10. The method for promoting the performance of flash memory according to item 9 of the scope of patent application, wherein the temperature of the method is about 700 to 75 ° C. 1 1. The method for promoting the performance of flash memory according to item 9 of the scope of patent application, wherein the method described above is pressure-controlled from about 200 Torr to 400 Torr. 1 2. The method for promoting flash memory performance according to item 9 of the scope of patent application, wherein the method includes a gas flow rate of hydrogen / (hydrogen + nitrogen) ratio of 5 to 60%. Page 18 587282 _ Case No. 91114467 _ month and month amend _ six, the scope of the patent application 1 3, such as the scope of the patent application for the seventh method to promote flash memory performance, wherein the microcrystalline silicon material can optionally contain silane and Ethylsilane. 1 4. The method for promoting flash memory performance according to item 7 of the scope of patent application, wherein the microcrystalline silicon layer is a floating gate. ~ 1 5. The method for promoting flash memory performance according to item 7 of the scope of the patent application, wherein the polycrystalline silicon layer is a control gate. Page 19