CN111403476B - Trench gate MOS power device and gate manufacturing method thereof - Google Patents
Trench gate MOS power device and gate manufacturing method thereof Download PDFInfo
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- CN111403476B CN111403476B CN201910002574.5A CN201910002574A CN111403476B CN 111403476 B CN111403476 B CN 111403476B CN 201910002574 A CN201910002574 A CN 201910002574A CN 111403476 B CN111403476 B CN 111403476B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 16
- 230000003647 oxidation Effects 0.000 claims abstract description 12
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 40
- 238000005530 etching Methods 0.000 claims description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 238000002347 injection Methods 0.000 claims description 17
- 239000007924 injection Substances 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 4
- 239000013590 bulk material Substances 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
According to the trench gate MOS power device and the gate manufacturing method thereof, two gate oxide layers with different thicknesses are formed at different positions through the twice thermal oxidation process, the threshold voltage can meet the normal working requirements of the trench gate MOS power device through the arrangement of the thin oxide layers, the normal switching action of the MOS power device is ensured, the miller capacitance can be reduced through the thick oxide layer, the problem that the switching action is difficult to regulate and control is solved, the switching loss is reduced, the carrier bombardment resistance of the thick oxide layer is high, and the long-range reliability of the whole device is improved. The invention reduces the Miller capacitance while ensuring the normal switching action of the MOS power device, solves the problem that the switching action is difficult to regulate and control, reduces the switching loss, improves the long-range reliability and is not limited by the threshold voltage.
Description
Technical Field
The invention belongs to the field of semiconductors, and particularly relates to a trench gate MOS power device and a gate manufacturing method thereof.
Background
Conventional trench gate MOS (Metal Oxide Semiconductor metal oxide semiconductor) power deviceThe gate oxide layer of the device is formed by single thermal oxidation. Due to threshold voltage limitations, the thickness of the thermal oxide layer is typically not too thick, i.e., the gate oxide capacitance C OX Larger. The miller capacitance of a device can be expressed by:
gate oxide capacitance C OX Larger Miller capacitance C Miller And the switching behavior is difficult to regulate and control, and the switching loss is difficult to reduce. Meanwhile, since the bottom of the trench is usually a high electric field region, carriers are constantly bombarded and injected into the gate oxide layer at the bottom of the trench in the transportation process, thereby affecting the long-range reliability of the gate and the whole device. The structure of the gate oxide layer of the conventional MOS power device is shown in FIG. 1, the whole gate oxide layer is a thin oxide layer 111 formed by single thermal oxidation, the gate body is formed by polysilicon 12, the gate body is arranged in the trench, and an equivalent series capacitance C is arranged between the polysilicon 12 and the collector 13 OX And C S 。
Disclosure of Invention
In order to solve the problems that in the prior art, the Miller capacitance of a trench gate MOS power device is high, so that the switching behavior is difficult to regulate and control, and the switching loss is difficult to reduce; the invention provides a trench gate MOS power device and a gate manufacturing method thereof, which have the following specific scheme that the gate and the long-range reliability of the whole device are affected by a carrier bombarding a gate oxide layer:
a method for manufacturing a grid of a trench gate MOS power device comprises the following steps:
step S1: forming a channel region and a trench;
step S2: performing primary oxidation, and forming a thick oxide layer in the groove;
step S3: removing the unnecessary thick oxide layer;
step S4: secondary oxidation, forming a thin oxide layer above the thick oxide layer;
step S5: a gate body is formed.
Further, in the step S3, the photoresist is used as a mask to control the final etching position of the thick oxide layer.
Further, in the step S2, the thick oxide layer is formed on top of the bulk material;
the step S3 includes the steps of:
step S301: filling the groove with the photoresist, and arranging the photoresist on the upper surface of the thick oxide layer;
step S302: exposing the photoresist and controlling the exposure depth of the photoresist;
step S303: removing the exposed photoresist;
step S304: etching the thick oxide layer by taking the residual photoresist as a mask;
step S305: and removing the residual photoresist in the groove.
Further, in the step S302, a bottom surface of the exposed photoresist is close to and higher than a bottom surface of the channel region.
Further, in the step S1, a carrier injection region is further formed, and in the step S302, a bottom surface of the exposed photoresist is close to and higher than a bottom surface of the carrier injection region.
Further, in the step S304, the thick oxide layer is etched by means of over-etching.
Further, in the step S304, the over etching amount of the thick oxide layer is controlled by etching time.
Further, in the step S5, polysilicon is deposited in the trench and on the upper surface of the gate oxide layer, so that the trench is filled with polysilicon, and then the polysilicon is etched so that the upper surface of the polysilicon is lower than the upper surface of the thin oxide layer.
The trench gate MOS power device manufactured by the gate manufacturing method is characterized by comprising a channel region, wherein a gate oxide layer corresponding to the channel region is a thin oxide layer, and a gate oxide layer below the thin oxide layer is a thick oxide layer.
Further, a carrier injection region is arranged below the channel region and is adjacent to the channel region, and a gate oxide layer corresponding to the carrier injection region is the thin oxide layer.
Compared with the prior art, the trench gate MOS power device and the gate manufacturing method thereof form two gate oxide layers with different thicknesses at different positions through twice thermal oxidation processes, the setting of the thin oxide layers enables the threshold voltage to meet the normal working requirements of the trench gate MOS power device, the normal switching action of the MOS power device is ensured, the thick oxide layers can reduce the Miller capacitance, the problem that the switching action is difficult to regulate and control is solved, the switching loss is reduced, the carrier bombardment resistance of the thick oxide layers is high, and the long-range reliability of the whole device is improved. The invention reduces the Miller capacitance while ensuring the normal switching action of the MOS power device, solves the problem that the switching action is difficult to regulate and control, reduces the switching loss, improves the long-range reliability and is not limited by the threshold voltage.
Drawings
The invention will be described in more detail hereinafter on the basis of embodiments and with reference to the accompanying drawings. Wherein:
fig. 1 is a schematic diagram of an IGBT structure in the prior art;
fig. 2 is a schematic diagram of an IGBT structure in an embodiment of the invention;
FIG. 3 is a schematic diagram of a structure formed after step S1 is performed in an embodiment of the present invention;
FIG. 4 is a schematic diagram of a thick oxide layer formed after a single thermal oxidation in an embodiment of the present invention;
FIG. 5 is a schematic diagram of a structure formed after adding photoresist in an embodiment of the present invention;
FIG. 6 is a schematic diagram of a structure of a photoresist after exposure according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a structure after removing the exposed photoresist according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a structure of a thick oxide etched using the remaining photoresist as a mask in an embodiment of the present invention;
FIG. 9 is a schematic diagram of a structure for removing residual photoresist according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of a structure of forming a thin oxide layer over a thick oxide layer by a secondary oxidation in the embodiment of the invention in FIG. 7;
FIG. 11 is a schematic diagram of a structure after depositing polysilicon according to an embodiment of the present invention;
fig. 12 is a schematic diagram of a structure of etching polysilicon to form a gate body in an embodiment of the invention.
In the drawings, like elements are designated with like reference numerals and the drawings are not drawn to scale.
Detailed Description
The invention will be further described with reference to the accompanying drawings.
The channel region in the invention refers to a well region capable of forming an inversion layer under the action of gate voltage;
the grid electrode comprises a grid electrode main body and a grid electrode oxide layer.
The thickness and thinness of the gate oxide layer in the present invention are relative concepts, and the thickness of the thick oxide layer is thicker than the thickness of the thin oxide layer.
Embodiment one:
as shown in fig. 2, the present embodiment provides a trench gate MOS power device, which includes a channel region, specifically, the channel region of the trench gate IGBT in the present embodiment is a P-well region 15, taking a trench gate IGBT (Insulated Gate Bipolar Transistor) as an example. In general, to form a complete trench gate IGBT structure, an n+ source region (not shown) contacting the emitter electrode is further disposed above the P well region 15, which is a common general knowledge and will not be discussed in detail.
In this embodiment, a carrier injection region adjacent to the P-well region 15 is further disposed below the P-well region 15, specifically, the carrier injection region in this embodiment is an N-well region 14, and when the N-well region 14 works in the trench gate IGBT, the injection level of carriers can be improved. The gate oxide layers corresponding to the P-well region 15 and the N-well region 14 are thin oxide layers 111 like the gate oxide layers of the conventional trench gate MOS power device, so that the threshold voltage of the conventional trench gate MOS power device can meet the working requirements of the P-well region 15 and the N-well region 14, so that under the action of the gate voltage, the P-well region 15 forms an inversion layer, and the N-well region 14 forms a depletion layer. The gate oxide layer below the thin oxide layer 111 is a thick oxide layer 112, the position of the P-well region 15 and the N-well region 14 is avoided due to the arrangement of the thick oxide layer 112, the problem that the gate oxide layer cannot be too thick due to the limitation of threshold voltage is avoided, meanwhile, as known from a calculation formula of the Miller capacitance, the Miller capacitance is reduced due to the arrangement of the thick oxide layer 112 below the thin oxide layer 111, namely, at the bottom of the groove 16, so that the problem that the switching behavior is difficult to regulate is solved, and the switching loss is reduced; the thick oxide layer 112 has strong carrier bombardment resistance and improves the long-range reliability of the whole device.
Preferably, the bottom surface of the thin oxide layer 111 is lower than the bottom surface of the N-well region 14, and the top surface of the thin oxide layer 111 is higher than the top surface of the P-well region 15, so as to ensure that both the P-well region 15 and the N-well region 14 can completely correspond to the thin oxide layer 111. The P-well region 15 and the N-well region 14 are symmetrically disposed on both sides of the trench 16 in this embodiment.
As shown in fig. 3-12, the present embodiment further provides a method for manufacturing a gate of a trench gate IGBT, the method including the steps of:
step S1: a P-well region 15 as a channel region and an N-well region 14 as a carrier injection region are formed, and a trench 16 is etched. Preferably, the P-well region 15 and the N-well region 14 may be formed first, and then the trench 16 may be etched according to the depth of the bottom surface of the N-well region 14, where the bottom surface of the trench 16 is lower than the bottom surface of the N-well region 14. Depth d of bottom surface of N well 14 2 From 1.5 μm to 5. Mu.m, preferably 2.5. Mu.m in this example. Depth d of bottom surface of etched trench 16 1 From 2 μm to 6. Mu.m, the preferred embodiment is 3.5. Mu.m. The initial references for each depth in this embodiment are the same.
Step S2: the thick oxide layer 112 is formed in the trench 16 by a thermal oxidation process for one time, and the thick oxide layer 112 may also be formed on top of the bulk material, the thick oxide layer 112 having a thickness of 100nm to 300nm, preferably 200nm.
Step S3: the unwanted thick oxide layer 112 is removed.
The method comprises the following specific steps:
step S301: the trench 16 is filled with a photoresist 17, and the photoresist 17 is disposed on the upper surface of the thick oxide layer 112, and the thickness of the photoresist above the upper surface of the thick oxide layer 112 is 0.5 μm to 2 μm, and in this embodiment, 1 μm is preferable.
Step S302: the exposure of the photoresist 17 to the front side and the precise control of the exposure depth of the photoresist 17 by controlling the exposure parameters, in particular how to control the exposure depth of the photoresist 17 by controlling the exposure parameters, is well known in the art and is not expanded. The exposure depth refers to the depth of the bottom surface of the exposed photoresist 171, and the bottom surface of the exposed photoresist 171 may be located near the bottom surface of the N-well region 14, may be slightly higher than the bottom surface of the N-well region 14, may be slightly lower than the bottom surface of the N-well region 14, or may be flush with the bottom surface of the N-well region, for example, the exposure depth may be 2.5 μm. The bottom surface of the exposed photoresist 171 is slightly higher than the bottom surface of the N-well region 14, which is more favorable for controlling the final etching position of the thick oxide layer 112 by over-etching, i.e. the position of the upper surface of the thick oxide layer 112 relative to the bottom surface of the N-well region 14, and the position of the upper surface of the thick oxide layer 112 is the position of the bottom surface of the thin oxide layer 111.
Step S303: the exposed photoresist 171 is removed by development.
Step S304: the remaining photoresist 172 is not exposed and the thick oxide layer 112 is wet etched over the entire surface of the remaining photoresist 172 as a mask to remove the unwanted thick oxide layer 112. Specifically, the thick oxide layer 112 on top of the bulk material and the thick oxide layer 112 on top of the trench are removed. The over etching is performed on the thick oxide layer 112 in an over etching manner, and the over etching amount of the thick oxide layer 112 is controlled by the etching time, and after the over etching is performed on the thick oxide layer 112 until the upper surface of the thick oxide layer is flush with the upper surface of the residual photoresist 172 which is not exposed, the thick oxide layer 112 is continuously etched, and finally the upper surface of the etched thick oxide layer 112 is slightly lower than the bottom surface of the N-well region 14, for example, the depth of the upper surface of the thick oxide layer 112 is 2.8 μm.
Step S305: the photoresist 172 remaining in the trench 16 is removed.
After step S3 is completed, step S4 is performed: a second oxidation, forming a thin oxide layer 111 over the thick oxide layer 112, the thickness of the thin oxide layer being 50nm-150nm, preferably 100nm;
step S5: polysilicon 12 is deposited on the upper surface of the thin oxide layer 111 and within the trench 16 such that the trench is filled with polysilicon 12, and the polysilicon 12 is etched across such that the upper surface of the polysilicon 12 is slightly below the upper surface of the thin oxide layer, thereby forming a gate body comprised of polysilicon 12.
The body material forming the trench gate IGBT in this embodiment may be one of Si, siC, gaN, or the like, and each well region is doped based on the body material. The material of the gate body is not limited to polysilicon, and other materials of the prior art for fabricating the gate body may be used in the present invention.
Embodiment two:
the N-well region 14 only serves to raise the carrier injection level, and removal of the N-well region 14 does not affect the basic function of the trench gate IGBT. The trench gate IGBT provided in this embodiment does not provide a carrier injection region, i.e., the N well region 14 is removed. When the gate of the trench gate IGBT device is manufactured, the N well region 14 is not formed in the step S1, and the bottom surface of the trench 16 is lower than the bottom surface of the P well region 15; in step S302, the bottom surface of the exposed photoresist 171 is located near the bottom surface of the P-well region 15, and may be slightly higher or lower or flush than the bottom surface of the P-well region 15. In step S304, the top surface of the finally etched thick oxide layer 112 is slightly lower than the bottom surface of the P-well region 15. The remainder is the same as in embodiment one.
The trench gate IGBT in the above two embodiments is an N-channel, and the present invention is applicable to any trench gate MOS power device such as a P-channel trench gate IGBT and a VDMOS (vertical double diffusion metal-oxide semiconductor).
In other embodiments, the gate oxide layer corresponding to the region above the channel region may be a thin oxide layer or a thick oxide layer, which is not limited in the present invention. For the gate oxide layer corresponding to the region above the channel region, a thick oxide layer is formed, and steps of etching the oxide layer and oxidizing for multiple times can be added between the step S4 and the step S5.
In other embodiments, the channel region may be disposed only on one side of the trench, the channel region is not disposed on the other side of the trench, and the gate oxide layer on the side where the channel region is not disposed may be entirely a thick oxide layer.
While the invention has been described with reference to a preferred embodiment, various modifications may be made and equivalents may be substituted for some or all of the features thereof without departing from the scope of the invention. In particular, the technical features mentioned in the various embodiments may be combined in any manner as long as there is no logical or structural conflict. The present invention is not limited to the specific embodiments disclosed herein, but encompasses all technical solutions falling within the scope of the claims.
Claims (9)
1. The method for manufacturing the grid of the trench gate MOS power device is characterized by comprising the following steps of:
step S1: forming a channel region, a trench, and a carrier injection region, the carrier injection region disposed below and immediately adjacent to the channel region, the channel region having an opposite polarity to the carrier injection region;
step S2: performing primary oxidation, and forming a thick oxide layer in the groove;
step S3: removing the unnecessary thick oxide layer; the method comprises the following substeps:
s301: filling photoresist in the groove, and arranging the photoresist on the upper surface of the thick oxide layer;
s302: exposing the photoresist and controlling the exposure depth of the photoresist; the bottom surface of the exposed photoresist is close to and higher than the bottom surface of the carrier injection region;
s303: removing the exposed photoresist;
s304: etching the thick oxide layer by taking the residual photoresist as a mask;
s305: removing the residual photoresist in the groove;
step S4: secondary oxidation, forming a thin oxide layer above the thick oxide layer; the bottom surface of the thin oxide layer is lower than the bottom surface of the carrier injection region, and the top surface of the thin oxide layer is higher than the top surface of the channel region;
step S5: a gate body is formed.
2. The method according to claim 1, wherein in the step S3, the final etching position of the thick oxide layer is controlled using photoresist as a mask.
3. The method according to claim 2, wherein in the step S2, the thick oxide layer is formed on top of the gate body material.
4. A gate fabrication method according to any one of claims 1 to 3, wherein in the step S302, a bottom surface of the exposed photoresist is close to and higher than a bottom surface of the channel region.
5. A gate fabrication method according to any one of claims 1 to 3, wherein in step S304, the thick oxide layer is etched by means of over-etching.
6. The method according to claim 5, wherein in step S304, the over etching amount of the thick oxide layer is controlled by etching time.
7. A method of fabricating a gate electrode according to any one of claims 1 to 3, wherein in step S5 polysilicon is deposited in the trench and on the upper surface of the gate oxide layer such that the trench is filled with polysilicon, and then the polysilicon is etched such that the upper surface of the polysilicon is below the upper surface of the thin oxide layer.
8. A trench gate MOS power device fabricated by the method of any of claims 1 to 7, comprising a channel region, wherein the gate oxide layer corresponding to the channel region is a thin oxide layer, and the gate oxide layer below the thin oxide layer is a thick oxide layer.
9. The trench-gate MOS power device of claim 8, wherein a carrier injection region is disposed below the channel region and immediately adjacent to the channel region, and wherein a gate oxide layer corresponding to the carrier injection region is the thin oxide layer.
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