WO2019007319A1 - Trench type power device and method for manufacturing same - Google Patents

Trench type power device and method for manufacturing same Download PDF

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Publication number
WO2019007319A1
WO2019007319A1 PCT/CN2018/094220 CN2018094220W WO2019007319A1 WO 2019007319 A1 WO2019007319 A1 WO 2019007319A1 CN 2018094220 W CN2018094220 W CN 2018094220W WO 2019007319 A1 WO2019007319 A1 WO 2019007319A1
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WIPO (PCT)
Prior art keywords
trench
conductivity type
gate
control gate
well region
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PCT/CN2018/094220
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French (fr)
Chinese (zh)
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卞诤
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无锡华润上华科技有限公司
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Publication of WO2019007319A1 publication Critical patent/WO2019007319A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to a trench type power device and a method of fabricating the same.
  • Trench type power devices such as VDMOS tubes introduce field depletion techniques, and the split gate device structure is a form that is relatively easy to implement based on current processes.
  • the voltage at the bottom of the trench needs to be increased, resulting in a sharp increase in the thickness of the outer polysilicon oxide layer at the bottom of the device, which ultimately leads to a rapid increase in the cell area of the trench region.
  • the effective conduction area is reduced and the on-resistance is increased.
  • a trench type power device includes a termination area and a cell area surrounded by the termination area; the cell area includes a plurality of cells; and the cell includes:
  • a first conductive type lightly doped silicon epitaxial layer being formed on a surface of the silicon substrate
  • a first trench extending through the second conductivity type well region and extending to the silicon epitaxial layer; a shielding gate and a main control gate are formed in the first trench; the main control gate is located in the shielding gate a side of the shielding gate; an oxide layer formed between the shielding gate and the sidewall and the bottom of the first trench; the main control gate and the shielding gate, the first trench a gate oxide layer is formed between the sidewalls;
  • the cell also includes:
  • a second trench penetrating the second conductivity type well region the second trench is in communication with the first trench; a width of the second trench is smaller than a width of the first trench;
  • An auxiliary control gate is formed in the second trench; the auxiliary control gate is connected to the main control gate; and a gate oxide layer is formed between sidewalls of the auxiliary control gate and the second trench;
  • a first conductivity type heavily doped source region is formed on a surface region of the second conductivity type well region and surrounded by the first trench and the second trench.
  • a method for preparing a trench type power device comprising:
  • Etching to form a first trench and a second trench a width of the first trench is greater than a width of the second trench; and the second trench is in communication with the first trench; a trench penetrating the second conductivity type well region and extending to the silicon epitaxial layer; the second trench penetrating the second conductivity type well region;
  • the oxide layer covers sidewalls of the first trench and fills the second trench;
  • the polysilicon is etched back to obtain a shield grid
  • a source region of a first conductivity type heavily doped is formed on a surface of the second conductivity type well region.
  • FIG. 1 is a schematic diagram showing a cell layout of a trench type power device in an embodiment
  • Figure 2 is a schematic cross-sectional view of the first trench of Figure 1;
  • Figure 3 is a schematic cross-sectional view of the second trench of Figure 1;
  • FIG. 4 is a flow chart showing a method of fabricating a trench type power device in an embodiment
  • FIG. 5a is a schematic structural diagram of a device completing step S406; FIG.
  • FIG. 5b is a schematic structural diagram of the device of step S408; FIG.
  • FIG. 5c is a schematic structural diagram of the device completing step S410;
  • Figure 5d is a schematic structural view of the device of step S412;
  • Figure 5e is a schematic structural view of the device in which step S414 is completed;
  • Figure 5f is a schematic structural view of the device in which step S416 is completed.
  • Figure 5g is a schematic structural diagram of the device in which step S418 is completed.
  • FIG. 5h is a schematic structural diagram of a device after gate polysilicon filling is completed in step S420;
  • Figure 5i is a schematic structural view of the device of step S420;
  • FIG. 6 is a flow chart showing a method of fabricating a trench type power device in another embodiment.
  • reference numerals N and P assigned to layers or regions mean that the layers or regions respectively include a large number of electrons or holes. Further, the reference marks + and - assigned to N or P indicate that the concentration of the dopant is higher or lower than the concentration in the layer which is not thus assigned to the mark. In the following description of the preferred embodiments and the drawings, like components are assigned like reference numerals and their redundant description is omitted.
  • a trench type power device in an embodiment includes a termination region and a cell region (which may also be an active region) surrounded by the termination region. There are multiple cells in the cell area. The cells in the cell area can be arranged according to preset rules. In this embodiment, the cell layout in the cell area is as shown in FIG. The cells in the cell are arranged in a matrix. Referring to Figure 1, wherein 112 represents the source region, 108 represents the first trench, and 110 represents the second trench. 2 is a schematic cross-sectional view of the first trench 108, and FIG. 3 is a schematic cross-sectional view of the second trench 110.
  • the trench type power device in this embodiment will be described in detail below with reference to FIGS. 1 to 3.
  • the cell includes a first conductivity type heavily doped silicon substrate 102, a first conductivity type lightly doped silicon epitaxial layer 104, a second conductivity type well region 106, a first trench 108, a second trench 110, and a source Area 112.
  • one side of the silicon substrate 102 is the front side, and the opposite side is the back side.
  • the front and back sides are merely for convenience of presentation and do not constitute a limitation on the technical solution itself.
  • a silicon epitaxial layer 104 is formed on the front side of the silicon substrate 102.
  • the second conductivity type well region 106 is formed on the surface of the silicon epitaxial layer 104.
  • the trench type power device is an N type device, so the first conductivity type is N type, and the second conductivity type is P type. That is, the silicon substrate 102 is an N+ layer, and the silicon epitaxial layer 104 is an N-layer.
  • the second conductivity type well region 106 is a P-type well region. In an embodiment, the second conductivity type well region 106 may be a P-type well region. In other embodiments, the trench type power device may be a P type device, so the first conductivity type is P type and the second conductivity type is N type.
  • the first trench 108 extends through the second conductivity type well region 106 and into the silicon epitaxial layer 104.
  • the depth of the first trench 108 can be adjusted by adjusting its width.
  • the first trench 108 extends to a region of the silicon epitaxial layer 104 that is adjacent to the silicon substrate 102, but is not in contact with the silicon substrate 102.
  • a shield gate 202 and a main control gate 204 are formed in the first trench 108.
  • the shield gate 202 is located in the intermediate portion of the first trench 108 and also extends through the second conductive type well region 106 and extends into the silicon epitaxial layer 104 to ensure that the shield gate 202 can operate normally.
  • the main control gate 204 is located on both sides of the shield gate 202 and at the upper portion of the shield gate 202. In an embodiment, the main control gate 204 extends through the second conductivity type well region 106 such that the main control gate 204 can control the channel. Further, the depth of the main control gate 204 may be slightly deeper than the depth of the second conductivity type well region 106 (ie, the effective doping depth of the second conductivity type well region 106), thereby ensuring that the main control gate 204 can completely control the channel. . In one embodiment, the shield gate 202 has a depth of at least 2 microns and the main control gate 204 has a depth of greater than or equal to 1 micron.
  • the depth of the main control gate 204 is typically set to be slightly deeper than 1 micron.
  • the upper surface of the shield grid 202 is between the upper surface of the source region 112 and the upper surface of the second conductivity type well region 106.
  • An oxide layer 206 is formed between the shield gate 202, the main control gate 204, and the sidewalls of the first trench 108.
  • a gate oxide layer 208 is formed between the main control gate 204 and the sidewall of the first trench 108 and the shield gate 202. Therefore, the gate oxide layer 208 and the main control gate 204 constitute a main control gate structure, and the oxide layer 206 and the shield gate 202 constitute a shield gate structure (which may also be referred to as a split gate structure). Since the main control gate structure is formed on both sides of the shield gate structure, that is, the control gate structure in the first trench 108 is a surrounding structure.
  • the second trench 110 extends through the second conductivity type well region 106.
  • the second trench 110 extends slightly into the silicon epitaxial layer 104.
  • the width of the second trench 110 is smaller than the width of the first trench 108.
  • the width of the second trench 110 is upper than the maximum trench which can ensure that the trench oxide layer can be closed, and the width of the second trench 110 is not lower than the minimum trench width of the required depth of the control gate.
  • the depth of the second trench 110 coincides with the depth of the main control gate 204.
  • the depth of the second trench 110 is related to the width of the second trench 110. To make the depth of the second trench 110 correspond to the depth of the main control gate 204, it is necessary to strictly control the width of the second trench 110. By strictly controlling the depth of the second trench 110, it is possible to avoid an excess oxide layer at the bottom of the second trench 110, thereby contributing to an increase in the withstand voltage of the device.
  • the second trench 110 is in communication with the first trench 108.
  • the second trench 110 is perpendicular to the first trench 108, and the second trench 110 and the first trench 108 are connected in a “#” character grid (as shown in FIG. 1), thereby making the cell composition.
  • the square cells help to improve the conduction efficiency.
  • the second trench 110 and the first trench 108 are in a "T" shape, so that three adjacent cells are arranged in a "good” character, three adjacent The lines between the cells are in a triangle. It can be understood that the second trench 110 and the first trench 108 may be in various forms after being in communication with each other, and is not limited to the above implementation.
  • An auxiliary control gate 210 is formed in the second trench 110.
  • the auxiliary control gate 210 is isolated from the sidewalls of the second trench 110 by a gate oxide layer 208.
  • the auxiliary control gate 210 is connected to the main control gate 204.
  • the auxiliary control gate 210 and the gate oxide layer 208 form an auxiliary control gate structure.
  • the auxiliary control gate 210 extends slightly into the silicon epitaxial layer 104 while penetrating the second conductivity type well region 106, thereby ensuring that the depth of the auxiliary control gate 210 is slightly greater than the depth of the second conductivity type well region 106. In turn, it is ensured that the auxiliary control gate 210 can completely control the channel.
  • the depth of the auxiliary control gate 210 is the same as the depth of the main control gate 204, and is about 1 micrometer.
  • the control of the depth of the second trench 110 can be achieved by strictly controlling the width of the second trench 110, that is, the first trench 108 can be made by controlling the width ratio of the first trench 108 and the second trench 110. And the depth of the second trench 110 meets the design requirements. Further, the thickness of the gate oxide layer 208 throughout the second trench 110 is uniform or nearly uniform.
  • the auxiliary control gate 210 in the second trench 110 is connected to the main control gate 204 in the first trench 108 such that all of the control gates can be connected together through one electrode.
  • the separation gate structure of the conventional surrounding structure is also the separation gate structure in the first trench 108. Since the main control gate 204 is isolated by the intermediate shield gate 202, generally, it can only be arranged as a strip cell to facilitate electrode extraction; If it is necessary to set it as a checkered cell, the main control gate 204 in each cell will form an independent ring structure, which is inconvenient for electrode introduction. Unless each main control gate 204 is taken out through the electrodes, this is not operability.
  • auxiliary control gate 210 is disposed in the second trench 110, so that the auxiliary control gate 210 is not blocked by other structures. Therefore, when the auxiliary control gate 210 is connected to the main control gate 204, the control gates in the cell region can be connected together and taken out through one electrode, thereby simplifying the electrode extraction process.
  • the source region 112 is a heavily doped region of the first conductivity type.
  • the source region 112 is formed on a surface region of the second conductivity type well region 106 and is surrounded by the first trench 108 and the second trench 110.
  • the first trench 108 and the second trench 110 are formed in the cell.
  • a shield structure of a conventional surrounding structure is formed in the first trench 108, that is, the main control gate 204 is located on both sides of the shield gate 202 and located at an upper portion of the shield gate 202.
  • Only the auxiliary control gate 210 is disposed in the second trench 110.
  • the withstand voltage of the cell is achieved by the electric field depletion in the direction of the first trench 108, regardless of the second trench 110.
  • the second trench 110 can provide additional conductive trenches, thereby reducing the on-resistance of the device.
  • the trench type power device may further include an interlayer insulating dielectric layer 114, a source metal layer 116, and a drain metal layer (not shown).
  • An interlayer insulating dielectric layer 114 covers the surfaces of the first trench 108, the second trench 110, and the source region 112.
  • the interlayer insulating dielectric layer 114 may be silicon glass (USG), borophosphosilicate glass (BPSG), or phosphosilicate glass (PSG).
  • a contact hole 118 is provided in the interlayer insulating dielectric layer 114 at the location of the source region 112. The contact hole is filled with a metal layer.
  • the filled metal layer can be a tungsten layer.
  • a source metal layer 116 is formed on the surface of the interlayer insulating dielectric layer 114 as a source of the device.
  • a drain metal layer is formed on the back side of the silicon substrate 102, that is, on the side opposite to the silicon epitaxial layer 104, as the drain of the device.
  • the above trench type power device can be applied to power devices of similar structure of all surface types, such as vertical conductive field depletion power devices.
  • the power device can be a VDMOS transistor, a MOS transistor, a DMOS transistor, or an IGBT device. It will be appreciated that power devices include, but are not limited to, the devices mentioned above.
  • An embodiment of the present application further provides a method of fabricating a trench type power device for fabricating the trench type power device described in any of the foregoing embodiments.
  • 4 is a flow chart showing a method of fabricating a trench type power device in an embodiment. The method includes the following steps:
  • Step S402 providing a first conductive type heavily doped silicon substrate.
  • Step S404 forming a first conductive type lightly doped silicon epitaxial layer on the surface of the silicon substrate.
  • Step S406 forming a second conductivity type well region on the surface of the silicon epitaxial layer.
  • Fig. 5a is a schematic view after completion of step S406.
  • one side of the silicon substrate 102 is the front side, and the opposite side is the back side.
  • the front and back sides are merely convenient for subsequent presentation and do not constitute a limitation on the technical solution itself.
  • a silicon epitaxial layer 104 is formed on the front side of the silicon substrate 102.
  • a second conductivity type well region 106 is formed on the surface of the silicon epitaxial layer 104.
  • the trench type power device is an N type device, so the first conductivity type is N type, and the second conductivity type is P type. That is, the silicon substrate 102 is an N+ layer, and the silicon epitaxial layer 104 is an N-layer.
  • the second conductivity type well region 106 is a P-type well region.
  • the second conductivity type well region 106 may be a P-type well region.
  • the trench type power device may be a P type device, so the first conductivity type is P type and the second conductivity type is N type.
  • Step S408, etching forms the first trench and the second trench.
  • FIG. 5b is a schematic diagram after completion of step S408.
  • the width of the second trench 110 is smaller than the width of the first trench 108.
  • the width of the second trench 110 is upper than the maximum trench which can ensure that the trench oxide layer can be closed, and the width of the second trench 110 is not lower than the minimum trench width of the required depth of the control gate.
  • the first trench 108 extends through the second conductivity type well region 106 and into the silicon epitaxial layer 104.
  • the first trench 108 extends to a region of the silicon epitaxial layer 104 that is adjacent to the silicon substrate 102, but is not in contact with the silicon substrate 102.
  • the depth of the second trench 110 coincides with the depth of the main control gate 204.
  • the depth of the second trench 110 is related to the width of the second trench 110. To make the depth of the second trench 110 correspond to the depth of the main control gate 204, it is necessary to strictly control the width of the second trench 110. By strictly controlling the depth of the second trench 110, it is possible to avoid an excess oxide layer at the bottom of the second trench 110, thereby contributing to an increase in the withstand voltage of the device.
  • the second trench 110 extends through the second conductivity type well region 106 and extends slightly into the silicon epitaxial layer 104.
  • the second trench 110 is in communication with the first trench 108.
  • the second trench 110 is disposed perpendicular to the first trench 108, and the second trench 110 and the first trench 108 are connected in a “#” character grid (as shown in FIG. 1), thereby making the cell Forming a lattice cell helps to improve the conduction efficiency.
  • the second trench 110 and the first trench 108 are in a "T" shape, so that three adjacent cells are arranged in a "good” character, three adjacent The lines between the cells are in a triangle. It can be understood that the second trench 110 and the first trench 108 may be in various forms after being in communication with each other, and is not limited to the above implementation.
  • step S410 trench oxidation is performed to obtain an oxide layer.
  • FIG. 5c is a schematic diagram after completion of step S410.
  • the prepared oxide layer 206 covers the sidewalls of the first trench 108 and fills the second trench 110. That is, in the process of performing trench oxidation, it is necessary to make the oxide layers on both sides of the second trench 110 contact each other, the second trench 110 is filled with the oxide layer, and the trench is formed in the first trench 108. .
  • the polysilicon in step S412 can be prevented from filling into the second trench 110, ensuring that no shield gate structure is formed in the second trench 110.
  • Step S412 filling the first trench with polysilicon.
  • Fig. 5d is a schematic view after completion of step S412.
  • step S414 the polysilicon is etched back to obtain a shielded grid.
  • Fig. 5e is a schematic view after completion of step S414.
  • the height of the upper surface of the etched shield gate is greater than the height of the surface of the second conductivity type well region 106.
  • the shield grid 202 has a depth of at least 2 microns.
  • Step S416 etching the oxide layer to remove the oxide layer in the second trench and removing the oxide layer on both sides of the upper portion of the shield gate.
  • Fig. 5f is a schematic view after completion of step S416.
  • only the oxide layer in the region of the second conductivity type well region 106 on both sides of the upper portion of the shield gate is etched to form a cavity, and the oxide layer in the second trench region 110 is etched away.
  • the oxide layer can be etched by wet etching.
  • the cavities in the first trench 108 and the second trench 110 both extend through the second conductivity type well region 106. Still further, the depth of the cavity is slightly greater than the depth of the second conductivity type well region 106.
  • Fig. 5g is a schematic view after completion of step S418.
  • Step S420 performing gate polysilicon filling and etching back, obtaining a main control gate in the first trench and obtaining an auxiliary control gate in the second trench.
  • auxiliary control gate 210 in the obtained second trench 110 is connected to the main control gate 204 in the first trench 108, so that all the control gates can be connected together and led out through one electrode.
  • Both the main control gate 204 and the auxiliary control gate 210 penetrate the second conductivity type well region 106 such that the main control gate 204 can control the channel.
  • the depth of the main control gate 204 may be slightly deeper than the depth of the second conductivity type well region 106 (ie, the effective doping depth of the second conductivity type well region 106), thereby ensuring that the main control gate 204 can completely control the channel. .
  • the depth of the main control gate 204 is greater than or equal to 1 micron.
  • the depth of the main control gate 204 is typically set to be slightly deeper than 1 micron.
  • the depth of the auxiliary control gate 210 is the same as the depth of the main control gate 204, and is about 1 micrometer.
  • Step S422 forming a source region of a first conductivity type heavily doped on a surface of the second conductivity type well region.
  • the upper surface of the prepared shield gate 202 is interposed between the upper surface of the source region 112 and the upper surface of the second conductivity type well region 106.
  • the trench type power device prepared by the above method has a first trench 108 and a second trench 110 formed in the cell.
  • a shielding gate structure of a conventional surrounding structure is formed in the first trench 108, that is, the main control gate 204 is located on both sides of the shielding gate 202 and located at an upper portion of the shielding gate 202. Only the auxiliary control gate 210 is disposed in the second trench 110.
  • the withstand voltage of the cell is achieved by the electric field depletion in the direction of the first trench 108, regardless of the second trench 110.
  • the second trench 110 can provide additional conductive trenches, thereby reducing the on-resistance of the device.
  • the foregoing method further includes the following steps on the basis of the foregoing embodiment, as shown in FIG. 6.
  • Step S502 forming an interlayer insulating dielectric layer on the surfaces of the first trench, the second trench, and the source region.
  • Step S504 a contact hole is disposed in the interlayer insulating dielectric layer at the source region position.
  • step S506 metal filling is performed, and a metal layer is formed by filling a metal in the contact hole.
  • Step S508 forming a source composed of a metal layer on the surface of the interlayer insulating dielectric layer.
  • Step S510 forming a drain composed of a metal layer on a side of the substrate opposite to the silicon epitaxial layer.
  • FIG. 2 A cross-sectional view of the device after preparation is shown in Figures 2 and 3.

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Abstract

A trench type power device, comprising a terminal region and a cell region surrounded by the terminal region. Multiple cells are comprised in the cell region. Each cell comprises: a heavily doped silicon substrate (102) of a first conductivity type; a lightly doped silicon epitaxial layer (104) of the first conductivity type; a well region (106) of a second conductivity type; a first trench (108) passing through the well region (106) of the second conductivity type and extending to the silicon epitaxial layer (104), main control gates (204) in the first trench (108) being located on both sides of the upper parts of shield gates (202), and gate oxide layers (208) being formed between the main control gates (204) and the shield gates (202) as well as sidewalls of the first trench (108); a second trench (110) passing though the well region (106) of the second conductivity type, the second trench (110) intersecting and being in communication with the first trench (108), the width of the second trench (110) being less than that of the first trench (108), gate oxide layers (208) being formed between auxiliary control gates (210) in the second trench (110) and sidewalls of the second trench (110), and the auxiliary control gates (210) being connected to the main control gates (204); and a source region (112).

Description

沟槽型功率器件及其制备方法Trench type power device and preparation method thereof 技术领域Technical field
本申请涉及半导体技术领域，特别是涉及一种沟槽型功率器件及其制备方法。The present application relates to the field of semiconductor technology, and in particular to a trench type power device and a method of fabricating the same.
背景技术Background technique
沟槽型功率器件如VDMOS管引入了场耗尽技术，分离栅器件结构是基于现行工艺较为容易实现的一种形式。但是采用分离栅技术，由于采用了双栅设计，沟槽(trench)底部需要承受的电压提高，导致器件的底部多晶硅外包氧化层厚度急剧增加，最终导致沟槽区所占元胞面积比重快速提升，有效导通面积降低，导通电阻增大。Trench type power devices such as VDMOS tubes introduce field depletion techniques, and the split gate device structure is a form that is relatively easy to implement based on current processes. However, with the split gate technology, due to the double-gate design, the voltage at the bottom of the trench needs to be increased, resulting in a sharp increase in the thickness of the outer polysilicon oxide layer at the bottom of the device, which ultimately leads to a rapid increase in the cell area of the trench region. The effective conduction area is reduced and the on-resistance is increased.
发明内容Summary of the invention
基于此，有必要提供一种沟槽型功率器件及其制备方法。Based on this, it is necessary to provide a trench type power device and a method of fabricating the same.
一种沟槽型功率器件，包括终端区和被所述终端区包围的元胞区；所述元胞区内包括多个元胞；所述元胞包括：A trench type power device includes a termination area and a cell area surrounded by the termination area; the cell area includes a plurality of cells; and the cell includes:
第一导电类型重掺杂的硅衬底；a first conductivity type heavily doped silicon substrate;
第一导电类型轻掺杂的硅外延层，所述硅外延层形成于所述硅衬底表面；a first conductive type lightly doped silicon epitaxial layer, the silicon epitaxial layer being formed on a surface of the silicon substrate;
第二导电类型阱区，形成于所述硅外延层的表面；a second conductivity type well region formed on a surface of the silicon epitaxial layer;
第一沟槽，贯穿所述第二导电类型阱区且延伸至所述硅外延层；所述第一沟槽内形成有屏蔽栅和主控制栅；所述主控制栅位于所述屏蔽栅两侧且位于所述屏蔽栅的上部；所述屏蔽栅和所述第一沟槽的侧壁及底部之间形成有氧化层；所述主控制栅和所述屏蔽栅、所述第一沟槽的侧壁之间形成有栅氧化层；a first trench extending through the second conductivity type well region and extending to the silicon epitaxial layer; a shielding gate and a main control gate are formed in the first trench; the main control gate is located in the shielding gate a side of the shielding gate; an oxide layer formed between the shielding gate and the sidewall and the bottom of the first trench; the main control gate and the shielding gate, the first trench a gate oxide layer is formed between the sidewalls;
所述元胞还包括：The cell also includes:
第二沟槽，贯穿所述第二导电类型阱区；所述第二沟槽与所述第一沟槽相交连通；所述第二沟槽的宽度小于所述第一沟槽的宽度；所述第二沟槽内形成有辅助控制栅；所述辅助控制栅与所述主控制栅相连；所述辅助控制栅和第二沟槽的侧壁之间形成有栅氧化层；以及a second trench penetrating the second conductivity type well region; the second trench is in communication with the first trench; a width of the second trench is smaller than a width of the first trench; An auxiliary control gate is formed in the second trench; the auxiliary control gate is connected to the main control gate; and a gate oxide layer is formed between sidewalls of the auxiliary control gate and the second trench;
第一导电类型重掺杂的源区，形成于所述第二导电类型阱区的表面区域上且被所述第一沟槽和所述第二沟槽包围。A first conductivity type heavily doped source region is formed on a surface region of the second conductivity type well region and surrounded by the first trench and the second trench.
一种沟槽型功率器件的制备方法，包括：A method for preparing a trench type power device, comprising:
提供第一导电类型重掺杂的硅衬底；Providing a first conductive type heavily doped silicon substrate;
在所述硅衬底表面形成第一导电类型轻掺杂的硅外延层；Forming a first conductive type lightly doped silicon epitaxial layer on the surface of the silicon substrate;
在所述硅外延层表面形成第二导电类型阱区；Forming a second conductivity type well region on the surface of the silicon epitaxial layer;
刻蚀形成第一沟槽和第二沟槽；所述第一沟槽的宽度大于所述第二沟道的宽度；所述第二沟槽与所述第一沟槽相交连通；所述第一沟槽贯穿所述第二导电类型阱区且延伸至所述硅外延层；所述第二沟槽贯穿所述第二导电类型阱区；Etching to form a first trench and a second trench; a width of the first trench is greater than a width of the second trench; and the second trench is in communication with the first trench; a trench penetrating the second conductivity type well region and extending to the silicon epitaxial layer; the second trench penetrating the second conductivity type well region;
进行沟槽氧化制备得到氧化层；所述氧化层覆盖所述第一沟槽的侧壁且将所述第二沟槽填充满；Performing trench oxidation to obtain an oxide layer; the oxide layer covers sidewalls of the first trench and fills the second trench;
对所述第一沟槽进行多晶硅填充；Performing polysilicon filling on the first trench;
对多晶硅进行回刻制备得到屏蔽栅；The polysilicon is etched back to obtain a shield grid;
对所述氧化层进行腐蚀以将所述第二沟槽内的氧化层去除且将屏蔽栅上部两侧的氧化层去除；Etching the oxide layer to remove the oxide layer in the second trench and removing the oxide layer on both sides of the upper portion of the shield gate;
在器件表面制备栅氧化层；Preparing a gate oxide layer on the surface of the device;
进行栅多晶硅填充并回刻，在第一沟槽内得到主控制栅并在第二沟槽内得到辅助控制栅；所述辅助控制栅与所述主控制栅相连；以及Performing gate polysilicon filling and etching back, obtaining a main control gate in the first trench and obtaining an auxiliary control gate in the second trench; the auxiliary control gate is connected to the main control gate;
在所述第二导电类型阱区的表面形成第一导电类型重掺杂的源区。A source region of a first conductivity type heavily doped is formed on a surface of the second conductivity type well region.
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请 的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。Details of one or more embodiments of the present application are set forth in the accompanying drawings and description below. Other features, objects, and advantages of the invention will be apparent from the description and appended claims.
附图说明DRAWINGS
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。To better describe and illustrate the embodiments and/or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the figures are not to be construed as limiting the scope of any of the disclosed inventions, the presently described embodiments and/or examples, and the best mode of the invention.
图1为一实施例中的沟槽型功率器件的元胞区版图示意图；1 is a schematic diagram showing a cell layout of a trench type power device in an embodiment;
图2为图1中的第一沟槽的截面示意图；Figure 2 is a schematic cross-sectional view of the first trench of Figure 1;
图3为图1中的第二沟槽的截面示意图；Figure 3 is a schematic cross-sectional view of the second trench of Figure 1;
图4为一实施例中的沟槽型功率器件的制备方法的流程图；4 is a flow chart showing a method of fabricating a trench type power device in an embodiment;
图5a为完成步骤S406的器件结构示意图；FIG. 5a is a schematic structural diagram of a device completing step S406; FIG.
图5b为完成步骤S408的器件结构示意图；FIG. 5b is a schematic structural diagram of the device of step S408; FIG.
图5c为完成步骤S410的器件结构示意图；FIG. 5c is a schematic structural diagram of the device completing step S410;
图5d为完成步骤S412的器件结构示意图；Figure 5d is a schematic structural view of the device of step S412;
图5e为完成步骤S414的器件结构示意图；Figure 5e is a schematic structural view of the device in which step S414 is completed;
图5f为完成步骤S416的器件结构示意图；Figure 5f is a schematic structural view of the device in which step S416 is completed;
图5g为完成步骤S418的器件结构示意图；Figure 5g is a schematic structural diagram of the device in which step S418 is completed;
图5h为步骤S420中完成栅多晶硅填充后的器件结构示意图；FIG. 5h is a schematic structural diagram of a device after gate polysilicon filling is completed in step S420;
图5i为完成步骤S420的器件结构示意图；Figure 5i is a schematic structural view of the device of step S420;
图6为另一实施例中的沟槽型功率器件的制备方法的流程图。6 is a flow chart showing a method of fabricating a trench type power device in another embodiment.
具体实施方式Detailed ways
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。In order to make the objects, technical solutions, and advantages of the present application more comprehensible, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the application and are not intended to be limiting.
在本说明书和附图中，分配给层或区域的参考标记N和P表示这些层或 区域分别包括大量电子或空穴。进一步地，分配给N或P的参考标记+和－表示掺杂剂的浓度高于或低于没有这样分配到标记的层中的浓度。在下文的优选实施例的描述和附图中，类似的组件分配有类似的参考标记且该处省略其冗余说明。In the present specification and the drawings, reference numerals N and P assigned to layers or regions mean that the layers or regions respectively include a large number of electrons or holes. Further, the reference marks + and - assigned to N or P indicate that the concentration of the dopant is higher or lower than the concentration in the layer which is not thus assigned to the mark. In the following description of the preferred embodiments and the drawings, like components are assigned like reference numerals and their redundant description is omitted.
一实施例中的沟槽型功率器件，包括终端区和被终端区包围的元胞区(也可成为有源区)。元胞区内包含有多个元胞。元胞区内的元胞可以根据预设规则进行排布。在本实施例中，元胞区内的元胞版图如图1所示。元胞内的元胞成矩阵排布。参见图1，其中，112表示源区、108表示第一沟槽，110则表示第二沟槽。图2为第一沟槽108的截面示意图，图3为第二沟槽110的截面示意图。下面结合图1～图3对本实施例中的沟槽型功率器件做详细说明。A trench type power device in an embodiment includes a termination region and a cell region (which may also be an active region) surrounded by the termination region. There are multiple cells in the cell area. The cells in the cell area can be arranged according to preset rules. In this embodiment, the cell layout in the cell area is as shown in FIG. The cells in the cell are arranged in a matrix. Referring to Figure 1, wherein 112 represents the source region, 108 represents the first trench, and 110 represents the second trench. 2 is a schematic cross-sectional view of the first trench 108, and FIG. 3 is a schematic cross-sectional view of the second trench 110. The trench type power device in this embodiment will be described in detail below with reference to FIGS. 1 to 3.
元胞包括第一导电类型重掺杂的硅衬底102、第一导电类型轻掺杂的硅外延层104、第二导电类型阱区106、第一沟槽108、第二沟槽110以及源区112。在本实施例中，以硅衬底102的一面为正面，而相对面则为背面。正面和背面仅仅为方便后续表述，并不构成对技术方案本身的限定。硅外延层104形成于硅衬底102的正面。第二导电类型阱区106形成于硅外延层104的表面。也即，硅衬底102的正面依次层叠设置有硅外延层104和第二导电类型阱区106。在本实施例中，沟槽型功率器件为N型器件，故第一导电类型为N型，第二导电类型为P型。也即硅衬底102为N+层，硅外延层104为N-层。第二导电类型阱区106为P型阱区。在一实施例中，第二导电类型阱区106可以为P-型阱区。在其他的实施例中，沟槽型功率器件可以为P型器件，故第一导电类型为P型，第二导电类型为N型。The cell includes a first conductivity type heavily doped silicon substrate 102, a first conductivity type lightly doped silicon epitaxial layer 104, a second conductivity type well region 106, a first trench 108, a second trench 110, and a source Area 112. In the present embodiment, one side of the silicon substrate 102 is the front side, and the opposite side is the back side. The front and back sides are merely for convenience of presentation and do not constitute a limitation on the technical solution itself. A silicon epitaxial layer 104 is formed on the front side of the silicon substrate 102. The second conductivity type well region 106 is formed on the surface of the silicon epitaxial layer 104. That is, the front surface of the silicon substrate 102 is sequentially laminated with a silicon epitaxial layer 104 and a second conductivity type well region 106. In this embodiment, the trench type power device is an N type device, so the first conductivity type is N type, and the second conductivity type is P type. That is, the silicon substrate 102 is an N+ layer, and the silicon epitaxial layer 104 is an N-layer. The second conductivity type well region 106 is a P-type well region. In an embodiment, the second conductivity type well region 106 may be a P-type well region. In other embodiments, the trench type power device may be a P type device, so the first conductivity type is P type and the second conductivity type is N type.
第一沟槽108贯穿第二导电类型阱区106且延伸至硅外延层104中。第一沟槽108的深度可以通过对其宽度的调整来进行调整。在本实施例中，第一沟槽108延伸至硅外延层104中靠近硅衬底102的区域，但是并不与硅衬底102接触。第一沟槽108内形成有屏蔽栅202和主控制栅204。其中，屏蔽栅202位于第一沟槽108的中间位置区域且同样贯穿第二导电类型阱区106 并延伸至硅外延层104中，以确保屏蔽栅202能够正常工作。主控制栅204位于屏蔽栅202的两侧且位于屏蔽栅202的上部。在一实施例中，主控制栅204贯穿第二导电类型阱区106，以使得主控制栅204可以对沟道进行控制。进一步地，主控制栅204的深度可以比第二导电类型阱区106的深度(也即第二导电类型阱区106的有效掺杂深度)略深，从而确保主控制栅204可以完全控制沟道。在一实施例中，屏蔽栅202的深度至少为2微米，主控制栅204的深度大于等于1微米。通常将主控制栅204的深度设置为比1微米略深。屏蔽栅202的上表面介于源区112的上表面和第二导电类型阱区106的上表面之间。屏蔽栅202、主控制栅204和第一沟槽108的侧壁之间形成有氧化层206。主控制栅204和第一沟槽108的侧壁、屏蔽栅202之间形成有栅氧化层208。因此，栅氧化层208和主控制栅204构成主控制栅结构，氧化层206和屏蔽栅202则构成屏蔽栅结构(也可以称为分离栅结构)。由于主控制栅结构形成于屏蔽栅结构的两侧，也即第一沟槽108内的控制栅结构为包围结构。The first trench 108 extends through the second conductivity type well region 106 and into the silicon epitaxial layer 104. The depth of the first trench 108 can be adjusted by adjusting its width. In the present embodiment, the first trench 108 extends to a region of the silicon epitaxial layer 104 that is adjacent to the silicon substrate 102, but is not in contact with the silicon substrate 102. A shield gate 202 and a main control gate 204 are formed in the first trench 108. The shield gate 202 is located in the intermediate portion of the first trench 108 and also extends through the second conductive type well region 106 and extends into the silicon epitaxial layer 104 to ensure that the shield gate 202 can operate normally. The main control gate 204 is located on both sides of the shield gate 202 and at the upper portion of the shield gate 202. In an embodiment, the main control gate 204 extends through the second conductivity type well region 106 such that the main control gate 204 can control the channel. Further, the depth of the main control gate 204 may be slightly deeper than the depth of the second conductivity type well region 106 (ie, the effective doping depth of the second conductivity type well region 106), thereby ensuring that the main control gate 204 can completely control the channel. . In one embodiment, the shield gate 202 has a depth of at least 2 microns and the main control gate 204 has a depth of greater than or equal to 1 micron. The depth of the main control gate 204 is typically set to be slightly deeper than 1 micron. The upper surface of the shield grid 202 is between the upper surface of the source region 112 and the upper surface of the second conductivity type well region 106. An oxide layer 206 is formed between the shield gate 202, the main control gate 204, and the sidewalls of the first trench 108. A gate oxide layer 208 is formed between the main control gate 204 and the sidewall of the first trench 108 and the shield gate 202. Therefore, the gate oxide layer 208 and the main control gate 204 constitute a main control gate structure, and the oxide layer 206 and the shield gate 202 constitute a shield gate structure (which may also be referred to as a split gate structure). Since the main control gate structure is formed on both sides of the shield gate structure, that is, the control gate structure in the first trench 108 is a surrounding structure.
第二沟槽110贯穿第二导电类型阱区106。在一实施例中，第二沟槽110略微延伸至硅外延层104内。在本实施例中，第二沟槽110的宽度小于第一沟槽108的宽度。第二沟槽110的宽度以其能够确保沟槽氧化层可以合拢的最大沟槽为上限，且第二沟槽110的宽度不低于控制栅要求深度的最小沟槽宽度。第二沟槽110的深度与主控制栅204的深度一致。第二沟槽110的深度与第二沟槽110的宽度相关，要使得第二沟槽110的深度与主控制栅204的深度相当，则需要严格控制第二沟槽110的宽度。通过对第二沟槽110的深度进行严格控制，可以避免第二沟槽110底部还有多余氧化层，从而有利于提高器件的耐压值。The second trench 110 extends through the second conductivity type well region 106. In an embodiment, the second trench 110 extends slightly into the silicon epitaxial layer 104. In the present embodiment, the width of the second trench 110 is smaller than the width of the first trench 108. The width of the second trench 110 is upper than the maximum trench which can ensure that the trench oxide layer can be closed, and the width of the second trench 110 is not lower than the minimum trench width of the required depth of the control gate. The depth of the second trench 110 coincides with the depth of the main control gate 204. The depth of the second trench 110 is related to the width of the second trench 110. To make the depth of the second trench 110 correspond to the depth of the main control gate 204, it is necessary to strictly control the width of the second trench 110. By strictly controlling the depth of the second trench 110, it is possible to avoid an excess oxide layer at the bottom of the second trench 110, thereby contributing to an increase in the withstand voltage of the device.
第二沟槽110与第一沟槽108相交连通。在本实施例中，第二沟槽110垂直于第一沟槽108，第二沟槽110和第一沟槽108连通呈“#”字格(如图1所示)，从而使得元胞构成方格状元胞，有利于提高导通效率。在其他的实施例中，第二沟槽110与第一沟槽108相交连通呈“T”字型，从而使得三个相邻 的元胞之间呈“品”字格排列、三个相邻的元胞之间的连线成三角形。可以理解，第二沟槽110和第一沟槽108相交连通后可以构成多种形式，并不限于上述实现方式。第二沟槽110内形成有辅助控制栅210。辅助控制栅210与第二沟槽110的侧壁之间通过栅氧化层208进行隔离。辅助控制栅210与主控制栅204相连。辅助控制栅210与栅氧化层208构成辅助控制栅结构。在一实施例中，辅助控制栅210在贯穿第二导电类型阱区106的同时还略微延伸至硅外延层104内，从而确保辅助控制栅210的深度略微大于第二导电类型阱区106的深度，进而确保辅助控制栅210可以完全控制沟道。辅助控制栅210的深度和主控制栅204的深度相同，均为1微米左右。对第二沟槽110的深度的控制可以通过严格控制第二沟槽110的宽度来实现，也即可以通过控制第一沟槽108和第二沟槽110的宽度比例来使得第一沟槽108和第二沟槽110的深度均满足设计需求。进一步地，第二沟槽110内各处的栅氧化层208的厚度一致或者几乎一致。The second trench 110 is in communication with the first trench 108. In this embodiment, the second trench 110 is perpendicular to the first trench 108, and the second trench 110 and the first trench 108 are connected in a “#” character grid (as shown in FIG. 1), thereby making the cell composition. The square cells help to improve the conduction efficiency. In other embodiments, the second trench 110 and the first trench 108 are in a "T" shape, so that three adjacent cells are arranged in a "good" character, three adjacent The lines between the cells are in a triangle. It can be understood that the second trench 110 and the first trench 108 may be in various forms after being in communication with each other, and is not limited to the above implementation. An auxiliary control gate 210 is formed in the second trench 110. The auxiliary control gate 210 is isolated from the sidewalls of the second trench 110 by a gate oxide layer 208. The auxiliary control gate 210 is connected to the main control gate 204. The auxiliary control gate 210 and the gate oxide layer 208 form an auxiliary control gate structure. In an embodiment, the auxiliary control gate 210 extends slightly into the silicon epitaxial layer 104 while penetrating the second conductivity type well region 106, thereby ensuring that the depth of the auxiliary control gate 210 is slightly greater than the depth of the second conductivity type well region 106. In turn, it is ensured that the auxiliary control gate 210 can completely control the channel. The depth of the auxiliary control gate 210 is the same as the depth of the main control gate 204, and is about 1 micrometer. The control of the depth of the second trench 110 can be achieved by strictly controlling the width of the second trench 110, that is, the first trench 108 can be made by controlling the width ratio of the first trench 108 and the second trench 110. And the depth of the second trench 110 meets the design requirements. Further, the thickness of the gate oxide layer 208 throughout the second trench 110 is uniform or nearly uniform.
第二沟槽110内的辅助控制栅210与第一沟槽108内的主控制栅204相连接，从而使得所有的控制栅可以连接在一起通过一个电极引出即可。传统的包围结构的分离栅结构也即第一沟槽108内的分离栅结构，由于主控制栅204被中间的屏蔽栅202隔离，所以一般只能设置成条状元胞，以方便电极引出；如果非要将其设置成方格状元胞，则每个元胞内的主控制栅204会形成一个个独立的环形结构，从而不方便电极导入。除非是将每个主控制栅204都通过电极引出，而这并不具备可操作性。因此，本实施例中，通过增加第二沟槽110，第二沟槽110中仅仅设置辅助控制栅210，从而使得辅助控制栅210并不会被其他结构隔断。因此，当辅助控制栅210与主控制栅204连接后，可以将元胞区内的控制栅均连接在一起，通过一个电极引出即可，从而简化了电极引出处理过程。The auxiliary control gate 210 in the second trench 110 is connected to the main control gate 204 in the first trench 108 such that all of the control gates can be connected together through one electrode. The separation gate structure of the conventional surrounding structure is also the separation gate structure in the first trench 108. Since the main control gate 204 is isolated by the intermediate shield gate 202, generally, it can only be arranged as a strip cell to facilitate electrode extraction; If it is necessary to set it as a checkered cell, the main control gate 204 in each cell will form an independent ring structure, which is inconvenient for electrode introduction. Unless each main control gate 204 is taken out through the electrodes, this is not operability. Therefore, in the present embodiment, by adding the second trench 110, only the auxiliary control gate 210 is disposed in the second trench 110, so that the auxiliary control gate 210 is not blocked by other structures. Therefore, when the auxiliary control gate 210 is connected to the main control gate 204, the control gates in the cell region can be connected together and taken out through one electrode, thereby simplifying the electrode extraction process.
源区112为第一导电类型重掺杂区。源区112形成于第二导电类型阱区106的表面区域上且被第一沟槽108和第二沟槽110包围。The source region 112 is a heavily doped region of the first conductivity type. The source region 112 is formed on a surface region of the second conductivity type well region 106 and is surrounded by the first trench 108 and the second trench 110.
上述沟槽型功率器件，元胞内形成有第一沟槽108和第二沟槽110。其 中第一沟槽108内形成有传统的包围结构的屏蔽栅结构，也即主控制栅204位于屏蔽栅202两侧且位于屏蔽栅202的上部。第二沟槽110内则仅仅设置辅助控制栅210。元胞的耐压通过第一沟槽108方向的电场耗尽来实现，与第二沟槽110无关。但是在器件导通时，第二沟槽110却可以提供额外的导电沟槽，从而降低了器件的导通电阻。In the above trench type power device, the first trench 108 and the second trench 110 are formed in the cell. A shield structure of a conventional surrounding structure is formed in the first trench 108, that is, the main control gate 204 is located on both sides of the shield gate 202 and located at an upper portion of the shield gate 202. Only the auxiliary control gate 210 is disposed in the second trench 110. The withstand voltage of the cell is achieved by the electric field depletion in the direction of the first trench 108, regardless of the second trench 110. However, when the device is turned on, the second trench 110 can provide additional conductive trenches, thereby reducing the on-resistance of the device.
在一实施例中，上述沟槽型功率器件还可以包括层间绝缘介质层114、源极金属层116和漏极金属层(图中未示)。层间绝缘介质层114覆盖于第一沟槽108、第二沟槽110和源区112表面。层间绝缘介质层114可以为硅玻璃(USG)、硼磷硅玻璃(BPSG)或者磷硅玻璃(PSG)。源区112位置处的层间绝缘介质层114中设置有接触孔118。接触孔内填充有金属层。填充的金属层可以为钨层。源极金属层116形成于层间绝缘介质层114的表面，作为器件的源极。漏极金属层则形成于硅衬底102的背面，也即与硅外延层104相对的一面上，作为器件的漏极。In an embodiment, the trench type power device may further include an interlayer insulating dielectric layer 114, a source metal layer 116, and a drain metal layer (not shown). An interlayer insulating dielectric layer 114 covers the surfaces of the first trench 108, the second trench 110, and the source region 112. The interlayer insulating dielectric layer 114 may be silicon glass (USG), borophosphosilicate glass (BPSG), or phosphosilicate glass (PSG). A contact hole 118 is provided in the interlayer insulating dielectric layer 114 at the location of the source region 112. The contact hole is filled with a metal layer. The filled metal layer can be a tungsten layer. A source metal layer 116 is formed on the surface of the interlayer insulating dielectric layer 114 as a source of the device. A drain metal layer is formed on the back side of the silicon substrate 102, that is, on the side opposite to the silicon epitaxial layer 104, as the drain of the device.
上述沟槽型功率器件可以适用于所有表面类型结构相似的功率器件，如垂直导电的场耗尽型功率器件。功率器件可以为VDMOS管、MOS管、DMOS管或者IGBT等器件。可以理解，功率器件包括但并不限于上述提及的器件。The above trench type power device can be applied to power devices of similar structure of all surface types, such as vertical conductive field depletion power devices. The power device can be a VDMOS transistor, a MOS transistor, a DMOS transistor, or an IGBT device. It will be appreciated that power devices include, but are not limited to, the devices mentioned above.
本申请一实施例还提供一种沟槽型功率器件的制备方法，其用于制备前述任一实施例中所介绍的沟槽型功率器件。图4为一实施例中的沟槽型功率器件的制备方法的流程图。该方法包括以下步骤：An embodiment of the present application further provides a method of fabricating a trench type power device for fabricating the trench type power device described in any of the foregoing embodiments. 4 is a flow chart showing a method of fabricating a trench type power device in an embodiment. The method includes the following steps:
步骤S402，提供第一导电类型重掺杂的硅衬底。Step S402, providing a first conductive type heavily doped silicon substrate.
步骤S404，在硅衬底表面形成第一导电类型轻掺杂的硅外延层。Step S404, forming a first conductive type lightly doped silicon epitaxial layer on the surface of the silicon substrate.
步骤S406，在硅外延层表面形成第二导电类型阱区。Step S406, forming a second conductivity type well region on the surface of the silicon epitaxial layer.
图5a为完成步骤S406后的示意图。在本实施例中，以硅衬底102的一面为正面，而相对面则为背面。正面和背面仅仅是方便后续表述，并不构成对技术方案本身的限定。硅外延层104形成于硅衬底102的正面。第二导电类型阱区106形成于硅外延层104表面。在本实施例中，沟槽型功率器件为N型器件，故第一导电类型为N型，第二导电类型为P型。也即硅衬底102 为N+层，硅外延层104为N-层。第二导电类型阱区106为P型阱区。在一实施例中，第二导电类型阱区106可以为P-型阱区。在其他的实施例中，沟槽型功率器件可以为P型器件，故第一导电类型为P型，第二导电类型为N型。Fig. 5a is a schematic view after completion of step S406. In the present embodiment, one side of the silicon substrate 102 is the front side, and the opposite side is the back side. The front and back sides are merely convenient for subsequent presentation and do not constitute a limitation on the technical solution itself. A silicon epitaxial layer 104 is formed on the front side of the silicon substrate 102. A second conductivity type well region 106 is formed on the surface of the silicon epitaxial layer 104. In this embodiment, the trench type power device is an N type device, so the first conductivity type is N type, and the second conductivity type is P type. That is, the silicon substrate 102 is an N+ layer, and the silicon epitaxial layer 104 is an N-layer. The second conductivity type well region 106 is a P-type well region. In an embodiment, the second conductivity type well region 106 may be a P-type well region. In other embodiments, the trench type power device may be a P type device, so the first conductivity type is P type and the second conductivity type is N type.
步骤S408，刻蚀形成第一沟槽和第二沟槽。Step S408, etching forms the first trench and the second trench.
图5b为完成步骤S408后的示意图。在本实施例中，通过调整第一沟槽108和第二沟槽110的宽度比例，可以实现对第一沟槽108和第二沟槽110的深度的控制，进而确保第一沟槽108和第二沟槽110的深度均满足设计要求。在本实施例中，第二沟槽110的宽度小于第一沟槽108的宽度。第二沟槽110的宽度以其能够确保沟槽氧化层可以合拢的最大沟槽为上限，且第二沟槽110的宽度不低于控制栅要求深度的最小沟槽宽度。第一沟槽108贯穿第二导电类型阱区106且延伸至硅外延层104中。第一沟槽108延伸至硅外延层104中靠近硅衬底102的区域，但是并不与硅衬底102接触。第二沟槽110的深度与主控制栅204的深度一致。第二沟槽110的深度与第二沟槽110的宽度相关，要使得第二沟槽110的深度与主控制栅204的深度相当，则需要严格控制第二沟槽110的宽度。通过对第二沟槽110的深度进行严格控制，可以避免第二沟槽110底部还有多余氧化层，从而有利于提高器件的耐压值。在一实施例中，第二沟槽110贯穿第二导电类型阱区106且略微延伸至硅外延层104内。FIG. 5b is a schematic diagram after completion of step S408. In the embodiment, by adjusting the width ratio of the first trench 108 and the second trench 110, the control of the depths of the first trench 108 and the second trench 110 can be realized, thereby ensuring the first trench 108 and The depth of the second trench 110 meets the design requirements. In the present embodiment, the width of the second trench 110 is smaller than the width of the first trench 108. The width of the second trench 110 is upper than the maximum trench which can ensure that the trench oxide layer can be closed, and the width of the second trench 110 is not lower than the minimum trench width of the required depth of the control gate. The first trench 108 extends through the second conductivity type well region 106 and into the silicon epitaxial layer 104. The first trench 108 extends to a region of the silicon epitaxial layer 104 that is adjacent to the silicon substrate 102, but is not in contact with the silicon substrate 102. The depth of the second trench 110 coincides with the depth of the main control gate 204. The depth of the second trench 110 is related to the width of the second trench 110. To make the depth of the second trench 110 correspond to the depth of the main control gate 204, it is necessary to strictly control the width of the second trench 110. By strictly controlling the depth of the second trench 110, it is possible to avoid an excess oxide layer at the bottom of the second trench 110, thereby contributing to an increase in the withstand voltage of the device. In an embodiment, the second trench 110 extends through the second conductivity type well region 106 and extends slightly into the silicon epitaxial layer 104.
第二沟槽110与第一沟槽108相交连通。在本实施例中，第二沟槽110垂直于第一沟槽108设置，第二沟槽110和第一沟槽108连通呈“#”字格(如图1所示)，从而使得元胞构成方格状元胞，有利于提高导通效率。在其他的实施例中，第二沟槽110与第一沟槽108相交连通呈“T”字型，从而使得三个相邻的元胞之间呈“品”字格排列、三个相邻的元胞之间的连线成三角形。可以理解，第二沟槽110和第一沟槽108相交连通后可以构成多种形式，并不限于上述实现方式。The second trench 110 is in communication with the first trench 108. In this embodiment, the second trench 110 is disposed perpendicular to the first trench 108, and the second trench 110 and the first trench 108 are connected in a “#” character grid (as shown in FIG. 1), thereby making the cell Forming a lattice cell helps to improve the conduction efficiency. In other embodiments, the second trench 110 and the first trench 108 are in a "T" shape, so that three adjacent cells are arranged in a "good" character, three adjacent The lines between the cells are in a triangle. It can be understood that the second trench 110 and the first trench 108 may be in various forms after being in communication with each other, and is not limited to the above implementation.
步骤S410，进行沟槽氧化制备得到氧化层。In step S410, trench oxidation is performed to obtain an oxide layer.
图5c为完成步骤S410后的示意图。制备得到的氧化层206覆盖第一沟槽108的侧壁且将第二沟槽110填充满。也即，在进行沟槽氧化的过程中，需要使得第二沟槽110内两侧的氧化层相互接触，第二沟槽110被氧化层填充满，而在第一沟槽108内形成沟槽。通过在第二沟槽110内填充满氧化层，可以防止步骤S412中的多晶硅填充到第二沟槽110中去，确保第二沟槽110内不形成屏蔽栅结构。FIG. 5c is a schematic diagram after completion of step S410. The prepared oxide layer 206 covers the sidewalls of the first trench 108 and fills the second trench 110. That is, in the process of performing trench oxidation, it is necessary to make the oxide layers on both sides of the second trench 110 contact each other, the second trench 110 is filled with the oxide layer, and the trench is formed in the first trench 108. . By filling the second trench 110 with a full oxide layer, the polysilicon in step S412 can be prevented from filling into the second trench 110, ensuring that no shield gate structure is formed in the second trench 110.
步骤S412，对第一沟槽进行多晶硅填充。Step S412, filling the first trench with polysilicon.
图5d为完成步骤S412后的示意图。Fig. 5d is a schematic view after completion of step S412.
步骤S414，对多晶硅进行回刻制备得到屏蔽栅。In step S414, the polysilicon is etched back to obtain a shielded grid.
图5e为完成步骤S414后的示意图。在本实施例中，刻蚀后的屏蔽栅的上表面所在高度大于第二导电类型阱区106的表面所在高度。屏蔽栅202的深度至少为2微米。Fig. 5e is a schematic view after completion of step S414. In this embodiment, the height of the upper surface of the etched shield gate is greater than the height of the surface of the second conductivity type well region 106. The shield grid 202 has a depth of at least 2 microns.
步骤S416，对氧化层进行腐蚀以将第二沟槽内的氧化层去除且将屏蔽栅上部两侧的氧化层去除。Step S416, etching the oxide layer to remove the oxide layer in the second trench and removing the oxide layer on both sides of the upper portion of the shield gate.
图5f为完成步骤S416后的示意图。在一实施例中，仅对屏蔽栅上部两侧位于第二导电类型阱区106区域的氧化层进行腐蚀形成空腔，并将第二沟槽内110内的氧化层腐蚀掉。氧化层腐蚀可以采用湿法腐蚀的方法。在一实施例中，第一沟槽108和第二沟槽110中的空腔均贯穿第二导电类型阱区106。更进一步地，该空腔的深度略微大于第二导电类型阱区106的深度。Fig. 5f is a schematic view after completion of step S416. In one embodiment, only the oxide layer in the region of the second conductivity type well region 106 on both sides of the upper portion of the shield gate is etched to form a cavity, and the oxide layer in the second trench region 110 is etched away. The oxide layer can be etched by wet etching. In an embodiment, the cavities in the first trench 108 and the second trench 110 both extend through the second conductivity type well region 106. Still further, the depth of the cavity is slightly greater than the depth of the second conductivity type well region 106.
步骤S418，在器件表面制备栅氧化层。Step S418, preparing a gate oxide layer on the surface of the device.
图5g为完成步骤S418后的示意图。Fig. 5g is a schematic view after completion of step S418.
步骤S420，进行栅多晶硅填充并回刻，在第一沟槽内得到主控制栅并在第二沟槽内得到辅助控制栅。Step S420, performing gate polysilicon filling and etching back, obtaining a main control gate in the first trench and obtaining an auxiliary control gate in the second trench.
在制备得到主控制栅和辅助控制栅时，需要先进行栅多晶硅填充，如图5h所示，然后再进行干法回刻腐蚀，以最终得到需要的主控制栅204和辅助控制栅210，如图5i所示。在一实施例中，得到的第二沟槽110内的辅助控制栅210与第一沟槽108内的主控制栅204相连接，从而使得所有的控制栅 可以连接在一起通过一个电极引出即可。主控制栅204和辅助控制栅210均贯穿第二导电类型阱区106，以使得主控制栅204可以对沟道进行控制。进一步地，主控制栅204的深度可以比第二导电类型阱区106的深度(也即第二导电类型阱区106的有效掺杂深度)略深，从而确保主控制栅204可以完全控制沟道。在一实施例中，主控制栅204的深度大于等于1微米。通常将主控制栅204的深度设置为比1微米略深。辅助控制栅210的深度和主控制栅204的深度相同，均为1微米左右。When preparing the main control gate and the auxiliary control gate, gate polysilicon filling is required first, as shown in FIG. 5h, and then dry etching is performed to finally obtain the required main control gate 204 and auxiliary control gate 210, such as Figure 5i shows. In an embodiment, the auxiliary control gate 210 in the obtained second trench 110 is connected to the main control gate 204 in the first trench 108, so that all the control gates can be connected together and led out through one electrode. . Both the main control gate 204 and the auxiliary control gate 210 penetrate the second conductivity type well region 106 such that the main control gate 204 can control the channel. Further, the depth of the main control gate 204 may be slightly deeper than the depth of the second conductivity type well region 106 (ie, the effective doping depth of the second conductivity type well region 106), thereby ensuring that the main control gate 204 can completely control the channel. . In one embodiment, the depth of the main control gate 204 is greater than or equal to 1 micron. The depth of the main control gate 204 is typically set to be slightly deeper than 1 micron. The depth of the auxiliary control gate 210 is the same as the depth of the main control gate 204, and is about 1 micrometer.
步骤S422，在第二导电类型阱区的表面形成第一导电类型重掺杂的源区。Step S422, forming a source region of a first conductivity type heavily doped on a surface of the second conductivity type well region.
制备得到的屏蔽栅202的上表面介于源区112的上表面和第二导电类型阱区106的上表面之间。The upper surface of the prepared shield gate 202 is interposed between the upper surface of the source region 112 and the upper surface of the second conductivity type well region 106.
通过上述方法制备得到的沟槽型功率器件，元胞内形成有第一沟槽108和第二沟槽110。其中第一沟槽108内形成有传统的包围结构的屏蔽栅结构，也即主控制栅204位于屏蔽栅202两侧且位于屏蔽栅202的上部。第二沟槽110内则仅仅设置辅助控制栅210。元胞的耐压通过第一沟槽108方向的电场耗尽来实现，与第二沟槽110无关。但是在器件导通时，第二沟槽110却可以提供额外的导电沟槽，从而降低了器件的导通电阻。The trench type power device prepared by the above method has a first trench 108 and a second trench 110 formed in the cell. A shielding gate structure of a conventional surrounding structure is formed in the first trench 108, that is, the main control gate 204 is located on both sides of the shielding gate 202 and located at an upper portion of the shielding gate 202. Only the auxiliary control gate 210 is disposed in the second trench 110. The withstand voltage of the cell is achieved by the electric field depletion in the direction of the first trench 108, regardless of the second trench 110. However, when the device is turned on, the second trench 110 can provide additional conductive trenches, thereby reducing the on-resistance of the device.
在另一实施例中，上述方法在前述实施例的基础上还包括以下步骤，如图6所示。In another embodiment, the foregoing method further includes the following steps on the basis of the foregoing embodiment, as shown in FIG. 6.
步骤S502，在第一沟槽、第二沟槽和源区的表面形成层间绝缘介质层。Step S502, forming an interlayer insulating dielectric layer on the surfaces of the first trench, the second trench, and the source region.
步骤S504，在源区位置处的层间绝缘介质层中设置接触孔。Step S504, a contact hole is disposed in the interlayer insulating dielectric layer at the source region position.
步骤S506，进行金属填充，在接触孔内填充金属形成金属层。In step S506, metal filling is performed, and a metal layer is formed by filling a metal in the contact hole.
步骤S508，在层间绝缘介质层表面形成由金属层组成的源极。Step S508, forming a source composed of a metal layer on the surface of the interlayer insulating dielectric layer.
步骤S510，在衬底上与硅外延层相对的一面上形成由金属层组成的漏极。Step S510, forming a drain composed of a metal layer on a side of the substrate opposite to the silicon epitaxial layer.
制备完成后的器件截面图如图2和3所示。A cross-sectional view of the device after preparation is shown in Figures 2 and 3.
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。The technical features of the above-described embodiments may be arbitrarily combined. For the sake of brevity of description, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction between the combinations of these technical features, All should be considered as the scope of this manual.
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。The above-mentioned embodiments are merely illustrative of several embodiments of the present application, and the description thereof is more specific and detailed, but is not to be construed as limiting the scope of the invention. It should be noted that a number of variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the present application. Therefore, the scope of the invention should be determined by the appended claims.

Claims (19)

  1. 一种沟槽型功率器件，包括终端区和被所述终端区包围的元胞区；所述元胞区内包括多个元胞；所述元胞包括：A trench type power device includes a termination area and a cell area surrounded by the termination area; the cell area includes a plurality of cells; and the cell includes:
    第一导电类型重掺杂的硅衬底；a first conductivity type heavily doped silicon substrate;
    第一导电类型轻掺杂的硅外延层，所述硅外延层形成于所述硅衬底表面；a first conductive type lightly doped silicon epitaxial layer, the silicon epitaxial layer being formed on a surface of the silicon substrate;
    第二导电类型阱区，形成于所述硅外延层的表面；a second conductivity type well region formed on a surface of the silicon epitaxial layer;
    第一沟槽，贯穿所述第二导电类型阱区且延伸至所述硅外延层；所述第一沟槽内形成有屏蔽栅和主控制栅；所述主控制栅位于所述屏蔽栅两侧且位于所述屏蔽栅的上部；所述屏蔽栅和所述第一沟槽的侧壁及底部之间形成有氧化层；所述主控制栅和所述屏蔽栅、所述第一沟槽的侧壁之间形成有栅氧化层；a first trench extending through the second conductivity type well region and extending to the silicon epitaxial layer; a shielding gate and a main control gate are formed in the first trench; the main control gate is located in the shielding gate a side of the shielding gate; an oxide layer formed between the shielding gate and the sidewall and the bottom of the first trench; the main control gate and the shielding gate, the first trench a gate oxide layer is formed between the sidewalls;
    第二沟槽，贯穿所述第二导电类型阱区；所述第二沟槽与所述第一沟槽相交连通；所述第二沟槽的宽度小于所述第一沟槽的宽度；所述第二沟槽内形成有辅助控制栅；所述辅助控制栅与所述主控制栅相连；所述辅助控制栅和第二沟槽的侧壁之间形成有栅氧化层；以及a second trench penetrating the second conductivity type well region; the second trench is in communication with the first trench; a width of the second trench is smaller than a width of the first trench; An auxiliary control gate is formed in the second trench; the auxiliary control gate is connected to the main control gate; and a gate oxide layer is formed between sidewalls of the auxiliary control gate and the second trench;
    第一导电类型重掺杂的源区，形成于所述第二导电类型阱区的表面区域上且被所述第一沟槽和所述第二沟槽包围。A first conductivity type heavily doped source region is formed on a surface region of the second conductivity type well region and surrounded by the first trench and the second trench.
  2. 根据权利要求1所述的沟槽型功率器件，其中，所述主控制栅贯穿所述第二导电类型阱区；所述辅助控制栅贯穿所述第二导电类型阱区。The trench type power device of claim 1, wherein the main control gate extends through the second conductivity type well region; the auxiliary control gate extends through the second conductivity type well region.
  3. 根据权利要求1所述的沟槽型功率器件，其中，所述屏蔽栅的深度大于等于2微米；所述主控制栅的深度和所述辅助控制栅的深度均大于等于1微米。The trench type power device according to claim 1, wherein a depth of the shield gate is greater than or equal to 2 μm; and a depth of the main control gate and a depth of the auxiliary control gate are both greater than or equal to 1 μm.
  4. 根据权利要求1所述的沟槽型功率器件，其中，所述屏蔽栅的上表面介于所述源区的上表面和所述第二导电类型阱区的上表面之间。The trench type power device according to claim 1, wherein an upper surface of the shield gate is interposed between an upper surface of the source region and an upper surface of the second conductivity type well region.
  5. 根据权利要求1所述的沟槽型功率器件，其中，所述第二沟槽与所述第一沟槽相交连通呈“#”字格。The trench type power device of claim 1, wherein the second trench is in communication with the first trench in a "#" grid.
  6. 根据权利要求1所述的沟槽型功率器件，其中，所述第一导电类型为N型，第二导电类型为P型。The trench type power device according to claim 1, wherein the first conductivity type is an N type and the second conductivity type is a P type.
  7. 根据权利要求1所述的沟槽型功率器件，其中，所述第一沟槽延伸至硅外延层中靠近硅衬底的区域，但是并不与所述硅衬底接触。The trench type power device according to claim 1, wherein the first trench extends to a region of the silicon epitaxial layer close to the silicon substrate, but is not in contact with the silicon substrate.
  8. 根据权利要求1所述的沟槽型功率器件，其中，还包括层间绝缘介质层，所述层间绝缘介质层覆盖于所述第一沟槽、第二沟槽和源区表面。The trench type power device of claim 1, further comprising an interlayer insulating dielectric layer covering the first trench, the second trench, and the source region surface.
  9. 一种沟槽型功率器件的制备方法，包括：A method for preparing a trench type power device, comprising:
    提供第一导电类型重掺杂的硅衬底；Providing a first conductive type heavily doped silicon substrate;
    在所述硅衬底表面形成第一导电类型轻掺杂的硅外延层；Forming a first conductive type lightly doped silicon epitaxial layer on the surface of the silicon substrate;
    在所述硅外延层表面形成第二导电类型阱区；Forming a second conductivity type well region on the surface of the silicon epitaxial layer;
    刻蚀形成第一沟槽和第二沟槽；所述第一沟槽的宽度大于所述第二沟道的宽度；所述第二沟槽与所述第一沟槽相交连通；所述第一沟槽贯穿所述第二导电类型阱区且延伸至所述硅外延层；所述第二沟槽贯穿所述第二导电类型阱区；Etching to form a first trench and a second trench; a width of the first trench is greater than a width of the second trench; and the second trench is in communication with the first trench; a trench penetrating the second conductivity type well region and extending to the silicon epitaxial layer; the second trench penetrating the second conductivity type well region;
    进行沟槽氧化制备得到氧化层；所述氧化层覆盖所述第一沟槽的侧壁且将所述第二沟槽填充满；Performing trench oxidation to obtain an oxide layer; the oxide layer covers sidewalls of the first trench and fills the second trench;
    对所述第一沟槽进行多晶硅填充；Performing polysilicon filling on the first trench;
    对多晶硅进行回刻制备得到屏蔽栅；The polysilicon is etched back to obtain a shield grid;
    对所述氧化层进行腐蚀以将所述第二沟槽内的氧化层去除且将屏蔽栅上部两侧的氧化层去除；Etching the oxide layer to remove the oxide layer in the second trench and removing the oxide layer on both sides of the upper portion of the shield gate;
    在器件表面制备栅氧化层；Preparing a gate oxide layer on the surface of the device;
    进行栅多晶硅填充并回刻，在第一沟槽内得到主控制栅并在第二沟槽内得到辅助控制栅；所述辅助控制栅与所述主控制栅相连；以及Performing gate polysilicon filling and etching back, obtaining a main control gate in the first trench and obtaining an auxiliary control gate in the second trench; the auxiliary control gate is connected to the main control gate;
    在所述第二导电类型阱区的表面形成第一导电类型重掺杂的源区。A source region of a first conductivity type heavily doped is formed on a surface of the second conductivity type well region.
  10. 根据权利要求9所述的方法，其中，在所述对所述氧化层进行腐蚀以将所述第二沟槽内的氧化层去除且将屏蔽栅上部两侧的氧化层去除的步骤中，形成的空腔贯穿所述第二导电类型阱区。The method according to claim 9, wherein in the step of etching the oxide layer to remove the oxide layer in the second trench and removing the oxide layer on both sides of the upper portion of the shield gate, The cavity extends through the second conductivity type well region.
  11. 根据权利要求9所述的方法，其中，所述屏蔽栅的深度大于等于2微米；所述主控制栅的深度和所述辅助控制栅的深度均大于等于1微米。The method of claim 9, wherein the shielding gate has a depth of 2 μm or more; a depth of the main control gate and a depth of the auxiliary control gate are both greater than or equal to 1 μm.
  12. 根据权利要求9所述的方法，其中，所述屏蔽栅的上表面介于所述源区的上表面和所述第二导电类型阱区的上表面之间。The method of claim 9, wherein an upper surface of the shield gate is interposed between an upper surface of the source region and an upper surface of the second conductivity type well region.
  13. 根据权利要求9所述的方法，其中，所述第二沟槽与所述第一沟槽相交连通呈“#”字格。The method of claim 9 wherein said second trench intersects said first trench in a "#" grid.
  14. 根据权利要求9所述的方法，其中，所述第一导电类型为N型，第二导电类型为P型。The method of claim 9, wherein the first conductivity type is an N type and the second conductivity type is a P type.
  15. 根据权利要求9所述的方法，其中，还包括在所述第一沟槽、第二沟槽和源区的表面形成层间绝缘介质层的步骤。The method of claim 9 further comprising the step of forming an interlayer dielectric layer on the surfaces of said first trench, said second trench and source region.
  16. 根据权利要求15所述的方法，其中，还包括在源区位置处的层间绝缘介质层中设置接触孔的步骤。The method of claim 15 further comprising the step of providing a contact hole in the interlayer dielectric layer at the source region location.
  17. 根据权利要求16所述的方法，其中，还包括在所述接触孔内填充金属形成金属层的步骤。The method according to claim 16, further comprising the step of filling a metal hole in said contact hole to form a metal layer.
  18. 根据权利要求17所述的方法，其中，还包括在层间绝缘介质层表面形成由金属层组成的源极的步骤。The method according to claim 17, further comprising the step of forming a source composed of a metal layer on the surface of the interlayer insulating dielectric layer.
  19. 根据权利要求9所述的方法，其中，还包括在衬底上与硅外延层相对的一面上形成由金属层组成的漏极的步骤。The method of claim 9 further comprising the step of forming a drain of a metal layer on a side of the substrate opposite the epitaxial layer of silicon.
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