JP2015195286A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To satisfy both of a fast operation and improved withstanding voltage.SOLUTION: In this semiconductor device 10, feedback capacity is reduced by a bottom electrode 28. On the other hand, a plurality of electrode projections 281 each having a downward convex shape are formed on the bottom electrode 28 and in a place where the electrode projections 281 are formed, a distance between a bottom face of a groove 24 and an nlayer 22 is locally narrower. By providing the plurality of electrode projections 281, withstanding voltage can be improved. In addition, an increase in output capacitance Coes can be inhibited.

Description

  The present invention relates to a structure of a trench gate type semiconductor device that performs a switching operation.

  A power MOSFET, an insulated gate bipolar transistor (IGBT), or the like is used as a switching element (power semiconductor element) that performs a large current switching operation. In such a switching element, a trench gate type in which an oxide film and a gate electrode are formed in a groove (trench) formed in a semiconductor substrate is used.

FIG. 5 is a cross-sectional view showing an example of the configuration of such a trench gate type power MOSFET (semiconductor device 110). In FIG. 5, in this semiconductor substrate 80, an n ⁻ layer 82 and a p ⁻ layer 83 are sequentially formed on an n ⁺ layer 81 serving as a drain layer. On the surface side of the semiconductor substrate 80, a groove (trench) 85 penetrating the p ⁻ layer 83 is formed. A plurality of grooves 85 (four in the illustrated range) are formed in parallel to extend in the direction perpendicular to the paper surface in FIG. An oxide film 86 is uniformly formed on the inner surface of each groove 85, and a gate electrode 87 is formed so as to fill the groove 85.

Further, on the surface side of the semiconductor substrate 80, n ⁺ layers 88 serving as source regions are formed on both sides of the groove 85. A source electrode (first main electrode) 89 is formed on the surface of the semiconductor substrate 80. On the other hand, a drain electrode (second main electrode) 90 is formed on the entire back surface of the semiconductor substrate 80 in contact with the n ⁺ layer (drain layer) 81. On the other hand, since the interlayer insulating layer 91 is formed on the surface side of the semiconductor substrate 80 so as to cover the groove 85, the source electrode 89 is in contact with both the n ⁺ layer 88 and the p ⁻ layer 83, and the gate electrode 87. Is insulated. On the surface side outside the range shown in FIG. 5, for example, all the gate electrodes 87 are connected on the end side in the extending direction (perpendicular to the paper surface) of the groove 85 and are connected to a common gate wiring. Further, the source electrode 89 is formed on the entire surface within the range shown in FIG. 5, but on the surface side, the gate wiring and the source electrode 89 are formed separately. Therefore, a channel is formed in the p ⁻ layer 83 on the side surface of the groove 85 by the voltage applied to the gate wiring (gate electrode 87) for each groove 85, and n between the n ⁻ layer 82 and the n ⁺ layer 88. It operates as a type MOSFET and this MOSFET is turned on. That is, the switching of current between the source electrode (second main electrode) 89 and the drain electrode (first main electrode) 90 can be controlled by the voltage applied to the gate electrode 87. Since the MOSFETs formed for each groove 85 are all connected in parallel, a large current can flow between the source electrode 89 and the drain electrode 90.

In order to operate this power MOSFET at high speed, it is necessary to reduce the feedback capacitance Crss, the input capacitance Ciss, and the output capacitance Coss. In the structure of FIG. 5, the feedback capacitance Crss is the capacitance between the gate electrode 87 and the drain electrode 90, and the input capacitance Ciss is the sum of the capacitance between the gate electrode 87 and the source electrode 89 and the feedback capacitance Crss. Here, in the structure of FIG. 5, since there is a capacitance through the oxide film 86 at the bottom of the trench 85, it is difficult to reduce the capacitance Crss between the gate electrode 87 and the drain electrode 90. Although it is clear that the Crss can be reduced by increasing the thickness of the oxide film 86, the characteristics of the MOSFET other than the operating speed are also largely dependent on the thickness of the oxide film 86. Is set so as to obtain desired characteristics other than the operation speed. For this reason, unlike the interlayer insulating layer 91, the oxide film 86 is thinly formed by thermal oxidation with particularly good interface characteristics with the semiconductor layer (p ⁻ layer 83, etc.). In this case, it is difficult to reduce Crss.

  In order to solve such a problem, as shown in FIG. 6, Patent Document 1 discloses a first semiconductor layer 92, a first oxidation layer having the same configuration as the gate electrode 87 and the oxide film 86 at the bottom of the trench 85. A structure in which a film 93 is provided and the gate electrode 87 and the oxide film 86 are formed thereon is described.

According to this structure, since the capacitance between the gate electrode 87 and the n ⁻ layer 82 can be reduced, the feedback capacitance Crss can be reduced. On the other hand, in this structure, the oxide film 86 on the p ⁻ layer 83 (side surface) on the side surface of the groove 85 where the channel is formed in the MOSFET can be thinned. A power MOSFET can be obtained.

An IGBT can also be configured with a similar structure. In this case, for example, an n ⁺ layer 81 is replaced with a p ⁺ layer (collector layer), a source electrode 89 is replaced with an emitter electrode, and a drain electrode 90 is replaced with a collector electrode. can do.

JP 2006-93506 A

  However, even in the technique described in Patent Document 1, it is clear that it is difficult to sufficiently reduce Crss when the first oxide film 93 is as thin as the oxide film 86.

Furthermore, in order to reduce Crss in the technique described in Patent Document 1, it is effective to set the first semiconductor layer 92 to the same potential as the source electrode 89. In this case, when a high voltage is applied to the drain electrode 90 at the time of off, a depletion layer may be formed in the n ⁻ layer 82 below the trench 25, and the electric field strength in the depletion layer is particularly high. For this reason, if the width of the depletion layer in FIG. 6 in the vertical direction is narrow, the electric field strength in the depletion layer is locally increased, the breakdown voltage is limited at this portion, and the breakdown voltage is lowered.

  Here, if the thickness of the first oxide film 93 is increased in order to reduce Crss, the width of the depletion layer is reduced, and the breakdown voltage is reduced. That is, it is difficult to achieve both high-speed operation and improved breakdown voltage.

  The present invention has been made in view of such problems, and an object thereof is to provide an invention that solves the above problems.

In order to solve the above problems, the present invention has the following configurations.
In the semiconductor device of the present invention, a groove is formed on the surface side of the semiconductor substrate, a gate electrode in contact with the oxide film formed on the inner surface of the groove is provided, and the first main body formed on the surface side of the semiconductor substrate is provided. An operating current flowing between an electrode and a second main electrode formed on the back side of the semiconductor substrate is a semiconductor device in which switching control is performed by a voltage applied to the gate electrode, and in the groove, Between the gate electrode and the bottom surface of the groove, a bottom electrode having a plurality of electrode protrusions that face the bottom surface of the groove through the oxide film and locally protrude toward the bottom surface side, The oxide film is sandwiched between the side surface, the bottom surface, and the gate electrode, respectively.
The semiconductor device of the present invention is characterized in that the width of the groove is larger than the depth of the groove.
In the semiconductor device of the present invention, the bottom electrode is electrically connected to the first main electrode.

  Since the present invention is configured as described above, it is possible to achieve both high speed operation and improved breakdown voltage.

It is sectional drawing of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows typically the relationship between the shape of the bottom electrode in the semiconductor device which concerns on embodiment of this invention, and the shape of the depletion layer formed in the lower side. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is process sectional drawing (continuation) which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the structure of an example of the conventional trench gate type semiconductor device. It is sectional drawing which shows the structure of another example of the conventional trench gate type semiconductor device.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described. This semiconductor device is a trench gate type IGBT in which channel switching is controlled by controlling on / off of a channel by a gate voltage. The gate electrode is formed in a plurality of grooves (trench) formed in parallel to the surface of the semiconductor substrate, and the gate electrodes are connected in parallel. Each gate electrode is formed inside the trench after an oxide film is formed on the surface in the trench. A bottom electrode facing the inner surface of the groove is formed on the lower side of the gate electrode in the groove through an oxide film, like the gate electrode. This bottom electrode corresponds to the first semiconductor layer 92 in FIG. 6, but is characterized by its cross-sectional shape.

FIG. 1 is a cross-sectional view showing the structure of the semiconductor device (IGBT) 10. The semiconductor device 10 is a trench gate type element having a configuration in which a gate electrode is formed in a groove (trench) formed in a semiconductor substrate 20 made of silicon. In FIG. 1, in this semiconductor substrate 20, an n ⁻ layer 22 and a p ⁻ layer 23 are sequentially formed on a p ⁺ layer 21 serving as a collector layer. On the surface side of the semiconductor substrate 20, a groove (trench) 24 penetrating the p ⁻ layer 23 is formed. A plurality of grooves 24 are formed in parallel to extend in a direction perpendicular to the paper surface in FIG.

On the surface side of the semiconductor substrate 20, n ⁺ layers 25 are formed on both sides of the groove 24. A structure in which the gate electrode 27 and the bottom electrode 28 are embedded in the oxide film 26 is provided inside the trench 24. An interlayer insulating layer 29 is formed on the upper side of the gate electrode 27, and an emitter electrode (first main electrode) 30 is formed so as to cover the entire surface of the semiconductor substrate 20 in the drawing. Emitter electrode 30 is connected to n ⁺ layer 25 and p ⁻ layer 23, and is insulated from gate electrode 27 by interlayer insulating layer 29. A bonding pad is connected to the emitter electrode 30 outside the range shown in the figure, and a bonding wire is connected to the emitter electrode 30, thereby making electrical connection to the emitter electrode 30 from the outside. The gate electrode 27 is taken out from a place where the emitter electrode 30 is not formed outside the range shown in the drawing, and is connected to another bonding pad, and similarly electrically connected to the outside. In practice, a plurality of the structures in FIG. 1 are connected in parallel perpendicularly to the paper surface, and the gate electrodes 27 in each are electrically connected in parallel outside the range shown in the figure. A collector electrode (second main electrode) 31 that is electrically connected to the p ⁺ layer (collector layer) 21 is formed on the entire back surface of the semiconductor substrate 20.

  Further, the bottom electrode 28 is connected to the emitter electrode 30 outside the range shown in the drawing. For this reason, the potential of the bottom electrode 28 becomes equal to the potential of the emitter electrode 30, and this potential is controlled independently of the potentials of the gate electrode 27 and the collector electrode 31.

In this semiconductor device 10, the bottom electrode 28 functions in the same manner as the first semiconductor layer 92 in FIG. 6, and this clearly reduces the feedback capacitance. On the other hand, in the bottom electrode 28, a plurality of electrode convex portions 281 having a convex shape on the lower side are formed, and in the portion where the electrode convex portion 281 is formed, it is between the n ⁻ layer 22 on the bottom surface of the groove 24. The interval is narrowed locally. Alternatively, the oxide film 26 immediately below is locally thin at the portion where the electrode convex portion 281 is formed. In addition to the portions where the electrode protrusions 281 are formed, the distance between the bottom electrode 28 and the bottom surface of the groove 25 is wider than the distance between the gate electrode 27 and the side surface of the groove 25. Alternatively, the oxide film 26 between the bottom electrode 28 and the bottom surface of the groove 24 is thicker than the oxide film 26 between the gate electrode 27 and the side surface of the groove 24 except for the portion where the electrode convex portion 281 is formed. It has become.

The operation of this structure will be described with reference to FIG. FIG. 2A shows a case where a flat bottom electrode 38 not having the electrode convex portion 281 is used, and when a high voltage is applied to the collector electrode 31, the oxide film 26 is interposed immediately below the collector electrode 31. The shape of the depletion layer end portion L formed in the n ⁻ layer 22 is shown. In this case, the depletion layer end portion L has a flat shape. The depletion layer width (distance from the depletion layer end L to the oxide film 26 (n ⁻ layer 22 upper end)) X ₀ is determined according to the thickness D ₀ of the oxide film 26 below the bottom electrode 38, and D _{When 0} is large, X ₀ is small. For the electric field intensity inside the depletion layer increases when X ₀ is small, the breakdown voltage between the emitter and collector is reduced. Therefore, it is preferable to reduce the D ₀ is from this point of view. However, when reducing the D _0, the bottom electrode 38 and the n ^- capacitance between the layer 22 becomes large, because the capacity between the emitter electrode 30 and collector electrode 31 is increased, reducing the output capacitance Coes Is difficult.

On the other hand, FIG. 2B shows the shape of the depletion layer end portion L when the bottom electrode 28 having the electrode convex portion 281 is used. The thickness of the oxide film 26 at the location where the electrode convex portion 281 does not exist is D ₀ as described above, and the thickness of the oxide film 26 at the location of the electrode convex portion 281 is D ₁ (D ₁ <D ₀ ). For this reason, the depletion layer end L is directly below the electrode protrusion 281 as compared with FIG. Since the electrode convex portion 281 exists, the shape of the lower side of the bottom electrode 28 changes stepwise, but the depletion layer end portion L has a continuous shape and changes in a curved manner. Therefore, greater than X ₀ in the depletion layer width FIGS. 2 (a) directly below the location where the electrode protrusion 281 is not present. For this reason, by providing the plurality of electrode protrusions 281, the breakdown voltage can be increased more than the configuration of FIG.

In FIG. 2B, the capacitance between the bottom electrode 28 and the n ⁻ layer 22 is locally increased at the portion where the electrode convex portion 281 is formed. The capacity between the electrodes 31 may increase. For this reason, it is preferable to reduce the area of the electrode convex portion 281 in the horizontal direction in FIG. As a result, an increase in capacitance between the emitter electrode 30 and the collector electrode 31 can be suppressed, and an increase in the output capacitance Coes can also be suppressed. For this reason, it is preferable to form a plurality of electrode projections 281 having a small area in a dispersed manner.

  As described above, in the semiconductor device 10, it is possible to obtain a low feedback capacity equivalent to that in the case where the flat bottom electrode is used, and simultaneously reduce the output capacity and increase the breakdown voltage. Alternatively, the output capacity can be further reduced when a breakdown voltage equivalent to that obtained when a flat bottom electrode is used.

  3 and 4 are process cross-sectional views illustrating the method for manufacturing the semiconductor device 10. Here, only the structure related to one groove 24 is shown.

First, as shown in FIG. 3A, on the p ⁺ layer 21, the surface (where the groove 24 is to be formed in the semiconductor substrate 20 in which the n ⁻ layer 22 and the p ⁻ layer 23 are sequentially formed) In the p ⁻ layer 23), an n ⁺ layer 25 having a width wider than that of the groove 24 is formed by ion implantation or the like.

Next, as shown in FIG. 3B, a groove 24 is formed in the region where the n ⁺ layer 25 is formed (groove forming step). The groove 24 can be formed, for example, by dry etching the semiconductor substrate 20 using a photoresist as a mask. The trench 24 has a depth that penetrates the p ⁻ layer 23 and reaches the n ⁻ layer 22.

Next, the structure of FIG. 3B is thermally oxidized to form a gate oxide film 261 (oxide film 26) on the entire surface of the semiconductor substrate 20 including the inside of the trench 24. The gate oxide film 261 is thinly formed with a uniform thickness on the surface of the semiconductor substrate 20 in which the trench 24 is formed. This thickness is appropriately set according to various characteristics such as the threshold voltage of the IGBT, and is usually 100 nm or less. The gate oxide film 261 contains SiO ₂ as a main component.

Next, a first additional oxide film 262 (oxide film 26) composed of the same component (SiO ₂ ) as the gate oxide film 261 is formed on the wafer having the structure shown in FIG. Is formed thicker than the gate oxide film 261. At this time, by using film formation conditions in which film formation is not performed conformally, the first additional oxide film 262 is hardly formed on the side wall of the groove 24, and only on the bottom surface of the groove 24 and the upper surface of the semiconductor substrate 20. A first additional oxide film 262 can be formed. As a result, as shown in FIG. 3D, the oxide film 26 becomes thick at the bottom surface of the groove 24.

  Next, as shown in FIG. 3E, a plurality of grooves (bottom oxide film grooves 26A) corresponding to the electrode convex portions 281 are formed on the surface of the oxide film 26 thickened at the bottom surface of the grooves 24 by dry etching. Form.

  Next, a polycrystalline silicon (gate electrode material) doped with high concentration so as to have conductivity is formed by a CVD method and then patterned to form the bottom electrode 28 as shown in FIG. Form. At this time, the bottom electrode 28 is formed so that the bottom oxide film groove 26 </ b> A is filled with the bottom electrode 28.

  Next, as shown in FIG. 3G, a second additional oxide film 263 similar to the first additional oxide film 262 is formed again. The film formation condition of the second additional oxide film 263 is the same as that of the first additional oxide film 262, and the second additional oxide film 263 is hardly formed on the sidewall of the groove 24.

  Next, as shown in FIG. 3 (h), the gate electrode 27 is filled so that the trench 24 in the state where the second additional oxide film 263 is formed is buried and is not formed elsewhere in the illustrated range. Form. The material, formation method, and patterning method of the gate electrode 27 are the same as those of the bottom electrode 28. However, the polycrystalline silicon is deposited thicker than when the bottom electrode 28 is formed so that the groove 24 is filled with the gate electrode 27.

Next, as shown in FIG. 4I, an interlayer insulating layer 29 covering the gate electrode 27 exposed on the surface is formed. The material and formation method of the interlayer insulating layer 29 are the same as those of the first additional oxide film 262 and the second additional oxide film 263. The interlayer insulating layer 29 is formed thick so that the insulation (breakdown voltage) between the gate electrode 27 and the emitter electrode 30 formed thereon is sufficient. The interlayer insulating layer 29 and the underlying oxide film 26 are patterned so that the n ⁺ layer 25 on the surface is at least partially exposed from the interlayer insulating layer 29.

  Thereafter, as shown in FIG. 4J, the emitter electrode 30 is formed on the front surface and the collector electrode 31 is formed on the back surface, whereby the semiconductor device 10 of FIG. 1 is manufactured. In the region shown in FIG. 4 (j), the emitter electrode 30 is formed on the entire surface. However, unlike the collector electrode 31, the emitter electrode 30 is actually formed on the entire surface of the semiconductor device 10. Not formed. Actually, the groove 24 extends in a direction perpendicular to the paper surface in FIGS. 3 and 4, and the gate electrode 27 is patterned at the end thereof so as to be drawn out on the surface side so as not to contact the emitter electrode 30. At this time, the plurality of gate electrodes 27 corresponding to the plurality of grooves 24 are electrically connected. Thereby, each of the gate electrode 27, the emitter electrode 30, and the collector electrode 31 functions as an electrode terminal. The plurality of bottom electrodes 28 corresponding to the plurality of grooves 24 are also electrically connected and electrically connected to the emitter electrode 30.

The semiconductor device 10 can be easily manufactured by the above manufacturing process. At this time, D ₀ in FIG. 2B can be adjusted by the growth thickness of the first additional oxide film 262 in FIG. D ₁ can be adjusted by the thickness of the first additional oxide film 262 and the etching depth by dry etching in FIG. The configuration and area of the electrode protrusion 281 can be adjusted by a dry etching (photolithography) mask pattern in FIG.

  In the conventional structure shown in FIGS. 5 and 6, there is no structure patterned in the groove width direction (in the direction of the paper in FIGS. 5 and 6) in the groove like the bottom electrode 28 described above. In contrast, in the semiconductor device 10 described above, the bottom electrode 28 patterned in this direction is provided. For this reason, in said structure, it is preferable to use a groove | channel with a width | variety larger than the depth. Alternatively, in the trench type device using such a wide groove, the above configuration is particularly preferable.

Although the semiconductor device 10 is an IGBT, a trench type power MOSFET can be configured by providing an n ⁺ layer instead of the p ⁺ layer (collector layer) 21. In this case, the emitter electrode 30 is a source electrode, and the collector electrode 31 is a drain electrode. Even in such a case, it is clear that the same effect can be obtained.

  In the above configuration, it is clear that the same effect can be obtained even if the conductivity type (p-type, n-type) is reversed. It is obvious that the above-described structure and manufacturing method can be realized regardless of the material constituting the semiconductor substrate, the gate electrode, and the like, and the same effect can be obtained.

10 Semiconductor device (IGBT)
20, 80 Semiconductor substrate 21 p ⁺ layer 22, 82 n ⁻ layer 23, 83 p ⁻ layer 24, 85 groove (trench)
25, 81 n ⁺ layers 26, 86 Oxide film 26A Bottom oxide film grooves 27, 87 Gate electrodes 28, 38 Bottom electrodes 29, 91 Interlayer insulating layer 30 Emitter electrode (first main electrode)
31 Collector electrode (second main electrode)
89 Source electrode (second main electrode)
90 Drain electrode (first main electrode)
92 First semiconductor layer 93 First oxide film 110 Semiconductor device (power MOSFET)
261 Gate oxide film (oxide film)
262 First additional oxide film (oxide film)
263 Second additional oxide film (oxide film)
281 Electrode convex part (bottom electrode)
L Depletion layer edge

Claims (3)

A groove is formed on the front surface side of the semiconductor substrate, a gate electrode in contact with the oxide film formed on the inner surface of the groove is provided, a first main electrode formed on the front surface side of the semiconductor substrate, and a back surface of the semiconductor substrate A semiconductor device in which an operating current flowing between the second main electrode formed on the side is controlled by a voltage applied to the gate electrode;
Inside the groove, a plurality of electrode protrusions are provided between the gate electrode and the bottom surface of the groove so as to face the bottom surface of the groove through the oxide film and locally protrude toward the bottom surface side. A semiconductor device, wherein a bottom electrode is formed by sandwiching the oxide film between a side surface, a bottom surface, and the gate electrode of the groove.   The semiconductor device according to claim 1, wherein a width of the groove is larger than a depth of the groove.   The semiconductor device according to claim 1, wherein the bottom electrode is electrically connected to the first main electrode.

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