JP2015201617A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve both a high-speed operation and improvement in withstanding voltage.SOLUTION: In a structure in Fig. 1, an oxide film 26 is formed to be uniformly thin on a lateral face where a gate electrode 27 is formed and to be thick at a bottom face center side of a groove 24. In this structure, the gate electrode 27 is not formed at the bottom face side of the groove 24, and is divided into both sides, and a bottom face electrode 28 is made to have the same potential as an emitter electrode 30. Thereby, a feedback capacity is reduced. In the above configuration, because a capacity between the emitter electrode 30 and a collector electrode 31 is also reduced, an output capacity Coes can be reduced. Further, the gate electrode 27 is formed to a position where the oxide film 26 is thinned at the bottom part. Therefore, the oxide film 26 between the gate electrode 27 and the bottom face of the groove 24 becomes thin, and thereby, a depletion layer immediately under the oxide film 26 becomes thick.

Description

  The present invention relates to a structure of a trench gate type semiconductor device that performs a switching operation. Moreover, it is related with the manufacturing method.

  A power MOSFET, an insulated gate bipolar transistor (IGBT), or the like is used as a switching element (power semiconductor element) that performs a large current switching operation. In such a switching element, a trench gate type in which an oxide film and a gate electrode are formed in a groove (trench) formed in a semiconductor substrate is used.

FIG. 8 is a cross-sectional view showing an example of the configuration of such a trench gate type power MOSFET (semiconductor device 110). In FIG. 8, in the semiconductor substrate 80, an n ⁻ layer 82 and a p ⁻ layer 83 are sequentially formed on an n ⁺ layer 81 serving as a drain layer. On the surface side of the semiconductor substrate 80, a groove (trench) 85 penetrating the p ⁻ layer 83 is formed. A plurality of grooves 85 (four in the illustrated range) are formed in parallel to extend in the direction perpendicular to the paper surface in FIG. An oxide film 86 is uniformly formed on the inner surface of each groove 85, and a gate electrode 87 is formed so as to fill the groove 85.

Further, on the surface side of the semiconductor substrate 80, n ⁺ layers 88 serving as source regions are formed on both sides of the groove 85. A source electrode 89 is formed on the surface of the semiconductor substrate 80. On the other hand, a drain electrode 90 is formed on the entire back surface of the semiconductor substrate 80 in contact with the n ⁺ layer (drain layer) 81. On the other hand, since the interlayer insulating layer 91 is formed on the surface side of the semiconductor substrate 80 so as to cover the groove 85, the source electrode 89 is in contact with both the n ⁺ layer 88 and the p ⁻ layer 83, and the gate electrode 87. Is insulated. On the surface side outside the range shown in FIG. 8, for example, all the gate electrodes 87 are connected on the end side in the extending direction (perpendicular to the paper surface) of the groove 85 and are connected to a common gate wiring. Further, the source electrode 89 is formed on the entire surface within the range shown in FIG. 8, but on the surface side, the gate wiring and the source electrode 89 are formed separately. Therefore, a channel is formed in the p ⁻ layer 83 on the side surface of the groove 85 by the voltage applied to the gate wiring (gate electrode 87) for each groove 85, and n between the n ⁻ layer 82 and the n ⁺ layer 88. It operates as a type MOSFET and this MOSFET is turned on. That is, the switching of current between the source electrode (first main electrode) 89 and the drain electrode 90 can be controlled by the voltage applied to the gate electrode 87. Since the MOSFETs formed for each groove 85 are all connected in parallel, a large current can flow between the source electrode 89 and the drain electrode 90.

Although FIG. 8 shows the structure of the power MOSFET, the same structure can be applied to the IGBT. In this case, for example, a structure in which the n ⁺ layer 81 is replaced by a p ⁺ layer, the source electrode 89 is replaced by an emitter electrode, and the drain electrode 90 is replaced by a collector electrode can be employed.

In order to operate this power MOSFET at high speed, it is necessary to reduce the feedback capacitance Crss, the input capacitance Ciss, and the output capacitance Coss. In the structure of FIG. 8, the feedback capacitance Crss is the capacitance between the gate electrode 87 and the drain electrode 90, and the input capacitance Ciss is the sum of the capacitance between the gate electrode 87 and the source electrode 89 and the feedback capacitance Crss. Here, in the structure of FIG. 8, since there is a capacitance through the oxide film 86 at the bottom of the trench 85, it is difficult to reduce the capacitance Crss between the gate electrode 87 and the drain electrode 90. Although it is clear that the Crss can be reduced by increasing the thickness of the oxide film 86, the characteristics of the MOSFET other than the operating speed are also largely dependent on the thickness of the oxide film 86. Is set so as to obtain desired characteristics other than the operation speed. For this reason, unlike the interlayer insulating layer 91, the oxide film 86 is thinly formed by thermal oxidation with particularly good interface characteristics with the semiconductor layer (p ⁻ layer 83, etc.). In this case, it is difficult to reduce Crss.

In order to solve such a problem, Patent Document 1 describes a structure in which the oxide film 86 is particularly thick only at the bottom of the groove 85.

According to this structure, the feedback capacitance Crss can be reduced. On the other hand, in this structure, since the oxide film 86 on the p ⁻ layer 83 (side surface) on the side surface of the groove 85 which is a portion where the channel is formed in the MOSFET is thinned, the power MOSFET having good characteristics other than the operation speed Can be obtained.

JP 2003-158268 A

In the technique described in Patent Document 1, since the gate electrode 87 and the oxide film 86 therebelow are thickened, the capacity of this portion can be reduced. On the other hand, when a high voltage is applied to the drain electrode 90 at the off time, a depletion layer is formed in the n ⁻ layer 82 on the bottom surface side of the groove 85. When the oxide film 86 is thick, the width of this depletion layer becomes narrow. When the width of the depletion layer is narrow, the electric field strength in the depletion layer is increased, so that the breakdown voltage is reduced. For this reason, it has been difficult to achieve both high speed operation and improved breakdown voltage.

  The present invention has been made in view of such problems, and an object thereof is to provide an invention that solves the above problems.

In order to solve the above problems, the present invention has the following configurations.
In the semiconductor device of the present invention, a groove is formed on the surface side of the semiconductor substrate, a gate electrode in contact with the oxide film formed on the inner surface of the groove is provided, and the first main body formed on the surface side of the semiconductor substrate is provided. An operating current flowing between an electrode and a second main electrode formed on the back side of the semiconductor substrate is a semiconductor device whose switching is controlled by a voltage applied to the gate electrode. In the groove, the gate electrode is divided and formed on both side surfaces of the groove, and the gate electrode is not formed on the bottom surface of the groove. And the bottom surface of the groove is formed such that the oxide film below the bottom electrode is thicker than the oxide film below the gate electrode. .
The semiconductor device of the present invention is characterized in that the width of the groove is larger than the depth of the groove.
In the semiconductor device of the present invention, the lower end portion of the gate electrode in the groove has an acute shape, and the angle formed by the bottom surface of the gate electrode with respect to the horizontal direction on the bottom surface side of the groove is in the range of 5 to 85 °. It is characterized by that.
In the semiconductor device of the present invention, in the in-plane distribution of acceptor concentration or donor concentration in a semiconductor layer in which a channel is formed according to a voltage applied to the gate electrode in the semiconductor substrate, the acceptor concentration or the donor concentration is It decreases as it approaches the groove.
The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing the semiconductor device, wherein after forming the groove in the semiconductor substrate, a thermal oxide film is formed by thermal oxidation, and the thermal oxide film is etched. The oxide film and the gate electrode are formed after removing in step (1).

  Since the present invention is configured as described above, it is possible to achieve both high speed operation and improved breakdown voltage.

It is sectional drawing of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows typically the form of the depletion layer formed in the bottom face of the groove | channel in the semiconductor device (a) used as a reference example, and the semiconductor device (b) which concerns on embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing of the 1st modification of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing of the 2nd modification of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which expands and shows the shape of the lower end part of the gate electrode in the semiconductor device which concerns on embodiment of this invention. In the semiconductor device concerning an embodiment of the invention, it is a figure showing typically an in-plane distribution of impurities in a semiconductor layer in which a channel is formed. It is sectional drawing which shows the structure of the conventional trench gate type semiconductor device. It is sectional drawing of the semiconductor device which concerns on other embodiment of this invention.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described. This semiconductor device is a trench gate type IGBT in which channel switching is controlled by controlling on / off of a channel by a gate voltage. The gate electrode is formed in a plurality of grooves (trench) formed in parallel to the surface of the semiconductor substrate, and the gate electrodes are connected in parallel. Each gate electrode is formed inside the trench after an oxide film is formed on the surface in the trench.

FIG. 1 is a cross-sectional view showing the structure of the semiconductor device (IGBT) 10. The semiconductor device 10 is a trench gate type element having a configuration in which a gate electrode is formed in a groove (trench) formed in a semiconductor substrate 20 made of silicon. In FIG. 1, in this semiconductor substrate 20, an n ⁻ layer 22 and a p ⁻ layer 23 are sequentially formed on a p ⁺ layer 21 serving as a collector layer. On the surface side of the semiconductor substrate 20, a groove (trench) 24 penetrating the p ⁻ layer 23 is formed. A plurality of grooves 24 are formed in parallel with each other in the direction perpendicular to the paper surface in FIG. 1, and one of them is shown in FIG.

On the surface side of the semiconductor substrate 20, n ⁺ layers 25 are formed on both sides of the groove 24. An oxide film 26 is formed on the inner surface (side surface and bottom surface) of the groove 24. The oxide film 26 is removed on the surface of the semiconductor substrate 20 away from the trench 24. In this semiconductor device 10, the structure in the groove 24 is particularly different from the semiconductor device 110 shown in FIG.

  First, the gate electrode 27 is provided along the left and right side wall portions of the groove 24, and is formed separately on the left and right at the bottom surface of the groove 24. However, each of the left and right gate electrodes 27 is connected outside the range shown in the figure (for example, the end in the longitudinal direction of the groove 24). The gate electrode 27 is made of, for example, conductive polycrystalline silicon doped at a high concentration.

On the other hand, when viewed from above, the bottom surface of the trench 25 is formed with a bottom electrode 28 separated (insulated) from the left and right gate electrodes 27 between the left and right gate electrodes 27. Since the oxide film 26 is also formed on the bottom surface of the groove 24, the bottom electrode 28 is also insulated from the underlying n ⁻ layer 22. In this state, an interlayer insulating layer 29 is formed in the trench 24 so as to cover the left and right gate electrodes 27 and to separate the bottom electrode 28 and the gate electrodes 27 on both sides thereof.

In this state, an emitter electrode (first main electrode) 30 is formed so as to cover the surface of the semiconductor substrate 20. With the above configuration, the emitter electrode 30 is connected to the p ⁻ layer 23 and the n ⁺ layer 25 on the surface of the semiconductor substrate 20 in the same manner as the source electrode 89 in the semiconductor device 110 configured as shown in FIG. The bottom electrode 28 on the bottom surface of the groove 24 is also connected by a through hole provided therein. The emitter electrode 30 and the gate electrode 27 are insulated by the interlayer insulating layer 29. On the other hand, a collector electrode (second main electrode) 31 that is electrically connected to the p ⁺ layer (collector layer) 21 is formed on the entire back surface of the semiconductor substrate 20.

  Similar to the semiconductor device 110 in FIG. 8, all the gate electrodes 27 are connected to the common gate wiring on the front side in the extending direction of the groove 24 on the surface side. The presence or absence of a channel in the p− layer 23 on the side surface of the trench 24 can be controlled by the voltage applied to the gate electrode 27. Thus, the potentials of the emitter electrode (first main electrode) 30, the collector electrode (second main electrode) 31, and the gate wiring (gate electrode 28) are controlled, and the emitter electrode 31, Switching of current between the collector electrodes 32 can be controlled. This operation is the same as that of a normal IGBT.

  In this structure, since the gate electrode 27 is not formed on the bottom surface side of the groove 24 but is divided on both sides, and the bottom electrode 28 is set to the same potential (ground potential) as the emitter electrode 30, the gate electrode 27 and the collector electrode The capacity Cres (feedback capacity) between 31 is reduced. However, when the bottom electrode 28 is provided, a capacitance between the emitter electrode 30 and the collector electrode 31 is generated due to the capacitance between the bottom electrode 28 and the bottom surface of the groove 24, thereby generating an output capacitance Coes (in a power MOSFET). Coss) may increase. However, in the above configuration, since the capacitance between the emitter electrode 30 and the collector electrode 31 is also reduced, the output capacitance Coes can also be reduced.

  Further, in a general trench gate type device, when the width of the groove 24 is wide (for example, when the width is 1 to 20 μm), the depletion layer on the bottom side of the groove 24 is difficult to expand. In many cases, the breakdown voltage of the entire device is lowered at this portion. On the other hand, by providing the bottom electrode 28 between the left and right gate electrodes 27 as described above, even when the width of the groove 24 is wide, the depletion layer on the bottom side of the groove 24 is well spread. It is possible to improve.

Here, in the structure of FIG. 1, the oxide film 26 is uniformly thin on the side surface on which the gate electrode 27 is formed, and thick on the center side of the bottom surface of the groove 24. For this reason, the capacitance between the bottom electrode 28 and the n ⁻ layer 22 (collector electrode 31 side) can be greatly reduced, and the capacitance between the emitter electrode 30 and the collector electrode 31 can be reduced.

  On the other hand, as described above, when a high voltage is applied to the collector electrode 31 at the time of OFF, a depletion layer spreads on the bottom side of the groove 24. Both the gate electrode 27 and the bottom electrode 28 affect the depletion layer. When the oxide film 26 under these electrodes is thin, the vertical width of the depletion layer in FIG. When the oxide film 26 is thick, the width becomes narrow. For this reason, the Crss can be lowered by making the oxide film 26 thick at the center of the bottom surface of the groove 24, while the width of the depletion layer formed immediately below this portion becomes narrow. For this reason, the withstand voltage in this part is lowered, and the withstand voltage when the IGBT is off may be limited and lowered in this part.

  On the other hand, the oxide film 26 is thick at the center of the bottom surface of the groove 24, but on both sides, it is as thin as the left and right side surfaces. Further, the gate electrode 27 is formed up to the portion where the oxide film 26 is thinned at the bottom. For this reason, since the oxide film 26 between the gate electrode 27 and the bottom surface of the trench 24 becomes thin, the depletion layer directly below becomes thick.

The operation of this structure will be described with reference to FIG. 2 (a) shows the shape of the depletion layer end L schematically in case the thickness of the oxide film 26 of the groove 24 bottom surface is uniformly D ₀ (reference example). In this case, the depletion layer end portion L has a substantially flat shape. Further, the depletion layer width (distance from the depletion layer end portion L from the oxide film 26 (n ⁻ layer 22 upper end portion)) X ₀ is determined according to the thickness D ₀ of the oxide film 26, and when D ₀ is large. the _{X 0} decreases. For the electric field intensity inside the depletion layer increases when X ₀ is small, the breakdown voltage between the emitter and collector is reduced. Therefore, it is preferable to reduce the D ₀ is from this point of view. However, when reducing the D ₀ is the bottom electrode 28 and the n ^- capacitance between the layer 22 becomes large, it is difficult to reduce the capacitance between the emitter electrode 30 and collector electrode 31.

On the other hand, FIG. 2B shows the shape of the depletion layer end L when the configuration of FIG. 1 is used. The thickness of the oxide film 26 in the groove 25 the center and the same D ₀ and the is thinner than this in both ends. For this reason, the depletion layer end portion L is directly below the gate electrode 27 as compared with FIG. 2A, and the depletion layer width is increased. Depletion layer end L becomes continuous shape corresponding thereto, in order to be the depletion layer end L in the central portion of the groove 24 is dragged by the opposite ends thereof, a depletion layer width X ₁ in the central portion of the groove 24, it can be greater than X ₀ of the. The breakdown voltage can be increased as compared with the configuration of FIG. Meanwhile, because the spacing between the bottom electrode 28 and the groove 24 bottom (thickness of the oxide film 26) is to be kept as large as D _0, the capacitance between the emitter electrode 30 and collector electrode 31 or the output capacitance Coes, is reduced Is done.

  A method for manufacturing the semiconductor device 10 will be specifically described below. 3A to 3H are process cross-sectional views illustrating the manufacturing process of the semiconductor device 10. Here, only the structure related to one groove 24 is shown.

First, as shown in FIG. 3A, a semiconductor substrate in which an n ⁻ layer 22 and a p ⁻ layer 23 also made of silicon are sequentially formed on a p ⁺ layer 21 made of silicon by epitaxial growth. An n ⁺ layer 25 having a width wider than that of the groove 24 is formed by ion implantation on the surface (in the p ⁻ layer 23) where the groove 24 is to be formed in 20. The conductivity type and impurity concentration in the n ⁻ layer 22 and the p ⁻ layer 23 are adjusted by adding impurities during the growth.

Next, as shown in FIG. 3B, a groove 24 is formed in the region where the n ⁺ layer 25 is formed. The groove 24 can be formed, for example, by dry etching the semiconductor substrate 20 using a photoresist as a mask. The trench 24 has a depth that penetrates the p ⁻ layer 23 and reaches the n ⁻ layer 22.

Next, by thermally oxidizing the structure of FIG. 3B, a gate oxide film 261 (oxide film 26) is formed on the entire surface of the semiconductor substrate 20 including the inside of the trench 24 as shown in FIG. 3C. Form. The gate oxide film 261 is thinly formed on the surface of the semiconductor substrate 20 in which the trench 25 is formed. This thickness is appropriately set according to various characteristics such as the threshold voltage of the IGBT, and is usually 100 nm or less. The gate oxide film 261 is a thermal oxide film containing SiO ₂ as a main component. The formation of the gate oxide film 261 is greatly affected by the supply of oxygen during thermal oxidation. For this reason, in order to form the gate oxide film 261 in the trench 24 with a uniform thickness, it is necessary to supply oxygen uniformly and stably. If the width of the trench 24 is narrow, it is difficult to supply oxygen uniformly in this case, whereas if the width of the trench 24 is wide, oxygen is supplied uniformly and the gate oxide film 261 It is easy to make the thickness uniform.

Next, an additional oxide film 262 (oxide film 26) composed of the same component (SiO ₂ ) as the gate oxide film 261 is gated on the wafer having the structure of FIG. It is formed thicker than the oxide film 261. At this time, the additional oxide film 262 is hardly formed in the vicinity of the side wall of the groove 24 or the bottom surface of the groove 24 by using a film forming condition in which the film is not formed conformally and an anisotropic film is formed. The first additional oxide film 262 can be formed in a shape raised on the bottom surface of the groove 24. As a result, as shown in FIG. 3D, the oxide film 26 becomes thick at the center of the bottom surface of the groove 24.

  Next, polycrystalline silicon (gate electrode material) doped with high concentration so as to have conductivity is formed over the entire surface by CVD. In this case, unlike the additional oxide film 262 described above, the film forming conditions are used such that the film is formed conformally and the polycrystalline silicon is uniformly formed on the bottom and side surfaces of the groove 24. It is done. Thereafter, the polycrystalline silicon layer is dry-etched using a photoresist as a mask, and as shown in FIG. 3 (e), the bottom surface made of conductive polycrystalline silicon on the center and side walls of the groove 24, respectively. The electrode 28 and the gate electrode 27 can be formed separately.

Thereafter, as shown in FIG. 3F, an interlayer insulating layer 29 made of SiO ₂ similar to the additional oxide film 262 is formed by CVD. However, unlike the additional oxide film 262, here, film forming conditions are used in which the film is formed conformally and the additional oxide film 262 is uniformly formed. The interlayer insulating layer 29 is formed thick so that the insulation (breakdown voltage) between the gate electrode 27 and the emitter electrode 30 formed thereon is sufficient.

Next, as shown in FIG. 3G, the interlayer insulating layer 29 and the oxide film 26 are patterned so that the surfaces of the n ⁺ layer 25 and the p ⁻ layer 23 are at least partially exposed. Further, the groove 24 is patterned so that a part of the bottom electrode 29 is exposed.

  Thereafter, as shown in FIG. 3H, the emitter electrode 30 is formed on the front surface and the collector electrode 31 is formed on the back surface, whereby the semiconductor device 10 of FIG. 1 is manufactured. In the region shown in FIG. 3 (h), the emitter electrode 30 is formed on the entire surface, but actually, unlike the collector electrode 31, the emitter electrode 30 is formed on the entire surface of the semiconductor device 10. Not formed. Actually, the groove 24 extends in a direction perpendicular to the paper surface in FIG. 33, and the gate electrode 27 is patterned so as to be drawn out on the surface side so as not to contact the collector electrode 30 at the end thereof. Thereby, each of the gate electrode 27, the emitter electrode 30, and the collector electrode 31 functions as an electrode terminal.

  Similarly to the above, FIGS. 4 and 5 show a cross-sectional view of another example in which the oxide film 26 under the bottom electrode 28 is thick and the oxide film 26 under the gate electrode 27 on both sides is thin. .

In the structure of FIG. 4, since the oxide film 26 is thinner at the bottom corner than the side surface in the trench 24, the oxide film 26 is particularly thin under the gate electrode 27 and thick under the bottom electrode 28. Therefore, the same effect as described above can be obtained. Such a shape of the oxide film 26 can be realized by adjusting the film formation conditions of the additional oxide film 262 shown in FIG. In the case of FIG. 3D, the additional oxide film 262 is formed on the side wall of the groove 24 under the condition that the additional oxide film 262 is hardly formed on the side wall of the groove 24. Therefore, the oxide film 26 formed on the side wall of the p ⁻ layer 23 contributing to the formation of the channel becomes thick.

  In the structure of FIG. 5, the oxide film 26 at the bottom of the groove 24 is formed thick as in the case shown in FIG. 3D, and then the oxide film 26 on both sides of the bottom of the groove 24 is thinly processed by dry etching. Can be obtained. In this case, the thickness of the oxide film 26 immediately below the gate electrode 27 can be adjusted by adjusting the dry etching depth (dry etching time). The width of the portion dug down by dry etching can be adjusted by the mask pattern at the time of dry etching.

  In addition, by adjusting the film formation conditions of the additional oxide film 262, the dry etching conditions of the oxide film 26, etc., the feedback capacity and the output capacity are reduced, and the width of the depletion layer immediately below the trench 24 is widened. The breakdown voltage can be increased.

  FIG. 6 is an enlarged view showing the lower structure of the right gate electrode 27 in the configuration of FIG. In this structure, since the cross-sectional shape of the oxide film 26 formed on the bottom surface of the trench 24 is as shown in FIG. 1, the lower end portion of the gate electrode 27 has an acute angle shape. As a result, the oxide film 26 immediately below the right lower end of the gate electrode 27 in FIG. 6 can be locally thinned, and the width of the depletion layer immediately below the groove 24 can be increased, while the gate electrode 27 and the groove It is possible to reduce the capacity between the bottom of the 24 and the feedback capacity. Further, since the bottom oxide film 26 is thickened on the center side of the trench 24 (left side in FIG. 6), the capacitance between the bottom electrode 28 and the bottom of the trench 24 can be reduced, and the output capacitance can be reduced. it can. About this point, the structure of FIG. 4 is also the same. In order to obtain such an effect, in the configuration of FIGS. 1 and 4, it is preferable that the angle θ formed between the bottom surface of the gate electrode 27 and the horizontal direction is in the range of 5 to 85 °. The shape of the bottom surface of the gate electrode 27 reflects the shape of the oxide film 26 in the trench 24. Therefore, by forming the oxide film 26 in such a shape, the gate electrode 27 having such a shape can be formed.

  As shown in FIG. 1 and the like, the gate electrode 27 is sandwiched between the oxide film 26 and the interlayer insulating layer 29. At this time, by forming the lower end portion of the gate electrode 27 in such an acute angle shape, the gate electrode 27 formed only on the side surface of the groove 24 is particularly stably supported between the oxide film 26 and the interlayer insulating layer 29. be able to. For this reason, high reliability can also be obtained.

Further, in the structure of FIG. 1 and the like, the oxide film 26 has a great influence on the threshold voltage of the IGBT and the power MOSFET. It is well known that the threshold voltage is affected by the thickness of the oxide film 26 between the p ⁻ layer 23 where the channel is formed and the gate electrode 27 and the doping concentration in the p ⁻ layer 23. Here, the oxide film 26 also affects the doping concentration of the p ⁻ layer 23. FIG. 7 is a schematic diagram for explaining this point. 7 shows the structure around the right gate electrode 27 in the trench 24. In the lower part of FIG. 7, the horizontal distribution (in-plane distribution) of the doping concentration in the p ⁻ layer 23 is schematically shown.

Here, it is assumed that boron (B) serving as an acceptor is added to the p ⁻ layer 23. Since the p ⁻ layer 23 and the n ⁻ layer 22 are formed on the p ⁺ layer 21 by epitaxial growth, impurities in each layer are introduced at the time of epitaxial growth, and at least in the in-plane direction, impurity distribution (acceptor concentration distribution). Is uniform. However, the gate oxide film 261 formed by thermal oxidation affects this distribution. Specifically, B is easily taken into the thermal oxide film (gate oxide film 261) at the time of thermal oxidation in FIG. 3C, and therefore, in the p ^- layer 23 where the gate oxide film 261 is formed. The B concentration decreases. For this reason, the in-plane distribution of the B concentration in the p ⁻ layer 23 decreases toward the groove 24 as shown in the lower side of FIG. As a result, the threshold voltage falls below a value determined by the B concentration introduced when the p ⁻ layer 23 is formed. Therefore, the threshold voltage can be controlled not only by the amount of B added at the time of forming the p ⁻ layer 23 but also by the formation conditions and film thickness setting of the gate oxide film 261.

Here, as described above, when the width of the groove 24 is wide, the thermal oxide film can be formed particularly uniformly. For this reason, control of the threshold voltage in this case can also be performed with high accuracy. Alternatively, as shown in FIG. 3C, after a thermal oxide film is formed by thermal oxidation, the thermal oxide film is removed by wet etching and then thermally oxidized again to form the thermal oxide film again (sacrificial). The threshold voltage can also be controlled to a desired value by repeating the oxidation step) as appropriate, and using the gate oxide film 261 as the last formed thermal oxide film. At this time, the thermal oxide film can be removed over the entire surface or partially. When the narrow groove 24 is used, it is difficult to form the thermal oxide film uniformly with good controllability, and thus it is difficult to perform such control with high accuracy. When a wide groove 24 having an electrode 28 therein is used, such a threshold voltage can be adjusted even after the p ^- layer 23 is formed by performing such a manufacturing method.

  Such adjustment of the threshold voltage can also be performed by performing ion implantation or the like at a position where the gate electrode 27 is to be formed before the gate electrode 27 is formed. However, it is not easy to perform ion implantation uniformly and highly accurately on the side surface of the groove 24 in the trench gate type device. On the other hand, according to the above method, the threshold voltage can be adjusted with high accuracy. That is, in the trench type element using the wide groove 25, the threshold voltage can be controlled with high accuracy by the above process.

The second embodiment shown in FIG. 9 will be described as follows. The difference between the semiconductor device of the second embodiment and the above-described embodiment is that the thickness of the oxide film 26 on the bottom surface of the groove 24 is substantially the same from the center side of the bottom surface of the groove 24 to both side surfaces of the bottom surface of the groove 24. The lower surface of the bottom electrode 28 is substantially the same as the lower end of the gate electrode 27, and the interlayer insulating film 29 is interposed between the lower end of the gate electrode 27 and the gate electrode 27. The difference is that the emitter electrode 30 extends in the groove 24 and is not connected to the bottom electrode 28.

In the semiconductor device 10 of the second embodiment, the lower end portion of the gate electrode 27 has an acute shape. Thereby, similarly to the above-described embodiment, the lower end portion of the gate electrode 27 has an acute shape, so that the distance between the lower end portion of the gate electrode 27 and the n ⁻ layer 22 on the center side of the groove 25 is increased. Therefore, the capacitance between the gate electrode 27 and the n ⁻ layer 22 below the bottom of the trench 24 can be reduced by that amount, and the feedback capacitance can be reduced.

Further, for example, an interlayer insulating film 29 is formed between the lower end portion of the gate electrode 27 and the trench 24 as an insulating film different from the oxide film 26. Here, the material different from the oxide film 26 between the lower end portion of the gate electrode 27 and the trench 24 may be, for example, an insulating layer having a high dielectric constant. When an insulating layer having a dielectric constant higher than that of the oxide film 26 is provided between the lower end portion of the gate electrode 27 and the trench 24, the semiconductor device 10 is interposed between the gate electrode 27 and the n ⁻ layer 22 below the bottom portion of the trench 24. Can be further reduced, and the feedback capacitance can be further reduced.

Further, the lower end portion of the gate electrode 27 on the side surface side of the groove 24 is lower than the lower end portion of the gate electrode 27 on the center side of the groove 24. As a result, the depletion layer on the side surface side of the groove 24 can be favorably spread to the n ⁻ layer 22 side by the lower end portion of the gate electrode 27 on the side surface side of the groove 24, and the breakdown voltage of the semiconductor device 10 can be ensured.

Further, the bottom surface of the bottom electrode 28 is substantially the same height as the lower end portion of the gate electrode 27. However, the distance between the side surface on the lower surface side of the bottom electrode 28 and the lower end portion of the gate electrode 27 is reduced because the central portion of the lower end portion of the gate electrode 27 facing the side surface of the bottom electrode 28 is scraped and inclined. As a result, the gate-emitter capacitance Cge can be reduced. Furthermore, by providing an inclination on the side surface of the bottom electrode 28 so that the width of the bottom surface of the bottom electrode 28 is larger than the width of the top surface, the distance between the side surface on the top surface side of the bottom electrode 28 and the lower end portion of the gate electrode 27 is increased. Further, the gate-emitter capacitance Cge can be remarkably reduced while ensuring the spread of the depletion layer by the bottom electrode 28.
Further, as shown in FIG. 9, there may be a region where the emitter electrode 30 is not connected to the bottom electrode 28 in the longitudinal direction in which the groove 24 extends. For example, the emitter electrode 30 and the bottom electrode 28 may be connected only at the end of the groove 24.

  In the above description, the semiconductor device is a trench gate type IGBT, but a similar structure can be used for a trench gate type element such as a power MOSFET. That is, a groove is formed on the surface of the semiconductor substrate, a gate electrode in contact with the oxide film formed on the inner surface thereof is provided, and the first main electrode formed on the front surface side of the semiconductor substrate and the first electrode formed on the back surface side. It is clear that the same structure can be adopted and the same effect can be obtained as long as the semiconductor device is controlled so that the operating current flowing between the two main electrodes is switched by the voltage applied to the gate electrode. .

  In the above structure, in particular, in the case of an IGBT having a wide groove of 1 to 20 μm, more preferably 3 to 15 μm, holes are accumulated at the bottom of the groove, which can reduce the on-voltage. Therefore, it is particularly preferable. In addition, since the number of gate electrodes can be reduced, the feedback capacitance can be further reduced.

In addition, each of the above configurations is an n-channel element, but it is apparent that a p-channel element can be similarly obtained by reversing the conductivity type (p-type and n-type). In this case, the acceptor concentration shown in FIG. 7 is the donor concentration in the n ⁻ layer corresponding to the p ⁻ layer 23. In addition, it is obvious that the above-described structure and manufacturing method can be realized without depending on the material constituting the semiconductor substrate, the gate electrode, and the like, and the same effect can be obtained.

10 Semiconductor device (IGBT)
20, 80 Semiconductor substrate 21 p ⁺ layer 22, 82 n ⁻ layer 23, 83 p ⁻ layer 24, 85 groove (trench)
25, 81, 88 n ⁺ layers 26, 86 Oxide film 27, 87 Gate electrode 28 Bottom electrode 29, 91 Interlayer insulating layer 30 Emitter electrode (first main electrode)
31 Collector electrode (second main electrode)
89 Source electrode (first main electrode)
90 Drain electrode (second main electrode)
110 Semiconductor Device (Power MOSFET)
261 Gate oxide film (oxide film)
262 Additional oxide film (oxide film)
L Depletion layer edge

Claims (9)

A groove is formed on the front surface side of the semiconductor substrate, a gate electrode in contact with the oxide film formed on the inner surface of the groove is provided, a first main electrode formed on the front surface side of the semiconductor substrate, and a back surface of the semiconductor substrate A semiconductor device in which an operating current flowing between the second main electrode formed on the side is controlled by a voltage applied to the gate electrode;
The gate electrode is divided into both sides of the groove and formed inside the groove,
A bottom electrode separated from the gate electrode and electrically connected to the first main electrode on the oxide film in a portion where the gate electrode is not formed at the bottom of the groove;
The semiconductor device according to claim 1, wherein the oxide film below the bottom electrode is formed thicker than the oxide film below the gate electrode at the bottom of the trench.   The semiconductor device according to claim 1, wherein a width of the groove is larger than a depth of the groove. The lower end portion of the gate electrode in the groove has an acute angle shape,
3. The semiconductor device according to claim 1, wherein an angle formed by a bottom surface of the gate electrode with respect to a horizontal direction on a bottom surface side of the groove is in a range of 5 to 85 °.   In the in-plane distribution of acceptor concentration or donor concentration in a semiconductor layer in which a channel is formed in the semiconductor substrate in accordance with a voltage applied to the gate electrode, the acceptor concentration or donor concentration decreases as the groove is approached. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. A method of manufacturing a semiconductor device according to any one of claims 1 to 4,
A thermal oxide film is formed by performing thermal oxidation after forming the trench in the semiconductor substrate, and the oxide film and the gate electrode are formed after removing the thermal oxide film by etching. A method for manufacturing a semiconductor device. A groove is formed on the front surface side of the semiconductor substrate, a gate electrode in contact with the oxide film formed on the inner surface of the groove is provided, a first main electrode formed on the front surface side of the semiconductor substrate, and a back surface of the semiconductor substrate A semiconductor device in which an operating current flowing between the second main electrode formed on the side is controlled by a voltage applied to the gate electrode;
The gate electrode is formed on both sides of the trench;
The position of the lower end portion of the gate electrode is higher on the center side of the groove than on the side wall side of the groove.   7. The semiconductor device according to claim 6, further comprising an insulating layer different from the oxide film between a lower end portion of the gate electrode and a bottom portion of the trench. The lower end portion of the gate electrode forms an inclined surface from the side wall side of the groove toward the center side of the groove,
In a region where the gate electrode is not formed on the bottom surface of the groove, a bottom electrode electrically insulated from the gate electrode and electrically connected to the first main electrode is provided.
The semiconductor device according to claim 6, wherein a side surface of the bottom electrode is opposed to an inclined surface of the gate electrode.   9. The semiconductor device according to claim 8, wherein the width of the upper surface of the bottom electrode is smaller than the width of the lower surface of the bottom electrode.

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