CN107644902A - Semiconductor device - Google Patents
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- CN107644902A CN107644902A CN201610821866.8A CN201610821866A CN107644902A CN 107644902 A CN107644902 A CN 107644902A CN 201610821866 A CN201610821866 A CN 201610821866A CN 107644902 A CN107644902 A CN 107644902A
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Abstract
The present invention provides the semiconductor device of the trench gate for the stable conductivity for making gate electrode.Semiconductor device has：Drift region (10)；Base (20), it is configured on drift region (10)；Launch site (30), it is configured on base (20)；Inner wall insulation film (40), it configures the inwall in groove, and the groove extends from the upper surface of launch site (30) and penetrates launch site (30) and base (20)；Gate electrode (50), the side of itself and base (20) are opposed to configuration on the inner wall insulation film (40) of the side of groove；And the interlayer dielectric (70) on gate electrode (50), gate electrode (50) are made up of polysilicon film, interlayer dielectric (70) has：1st interlayer dielectric (71), its material change the electric conductivity of gate electrode (50) when being contacted with gate electrode (50)；And the 2nd interlayer dielectric (72), it is configured between gate electrode (50) and the 1st interlayer dielectric (71) so that the electric conductivity of gate electrode (50) is constant.
Description
Technical field
The present invention relates to the semiconductor device of trench gate.
Background technology
As the switch element (power semiconductor) for the switch motion for carrying out high current, using power MOSFET and absolutely
Edge grid-type bipolar transistor (IGBT) etc..(trench gate) is constructed using groove-shaped gate electrode in these switch elements, i.e.,
Gate insulating film and gate electrode are formed in the groove (groove) for being formed at semiconductor substrate.But the semiconductor in trench gate fills
In putting, the electric capacity (grid-collection between electric capacity (electric capacity between gate-to-drain), gate electrode and collecting zone between gate electrode and drain region
Interelectrode capacitance) etc. feedback capacity it is larger.Therefore, switching speed declines, and problem is produced in high frequency mo.
It is used for the various methods for reducing feedback capacity in research.Such as, it has been disclosed that following construction：Match somebody with somebody in the side of groove
Put gate electrode, the electrode that configuration is connected with emission electrode in the bottom surface of groove (for example, referring to patent document 1).
【Prior art literature】
【Patent document】
【Patent document 1】Japanese Unexamined Patent Publication 2015-201615 publications
The content of the invention
Problems to be solved by the invention
But the impurity included in interlayer dielectric becomes the electric conductivity of the gate electrode being made up of polysilicon inside groove
Change, thus the electrical characteristic that can not be stablized.Therefore, it is an object of the present invention to provide the stable conductivity for making gate electrode
Trench gate semiconductor device.
The means used to solve the problem
The mode of the present invention provides semiconductor device, and the semiconductor device has：1st semiconductor of the 1st conductivity type
Region；2nd semiconductor regions of the 2nd conductivity type, it is configured on the 1st semiconductor regions；3rd semiconductor region of the 1st conductivity type
Domain, it is configured on the 2nd semiconductor regions；Inner wall insulation film, it configures the inwall in groove, and the groove is from the 3rd semiconductor regions
Upper surface extends and penetrates the 3rd semiconductor regions and the 2nd semiconductor regions；Coordination electrode, its side with the 2nd semiconductor regions
Configuration is opposed on the inner wall insulation film of the side of groove；And the interlayer dielectric in coordination electrode, coordination electrode is by polycrystalline
Silicon fiml is formed, and interlayer dielectric has：1st interlayer dielectric, the material of the 1st interlayer dielectric with coordination electrode when contacting
Change the electric conductivity of coordination electrode；And the 2nd interlayer dielectric, it is configured between coordination electrode and the 1st interlayer dielectric,
So that the electric conductivity of coordination electrode is constant.
Another mode of the present invention provides semiconductor device, and the semiconductor device has：Lead the 1st half of 1st conductivity type
Body region；2nd semiconductor regions of the 2nd conductivity type, it is configured on the 1st semiconductor regions；3rd semiconductor of the 1st conductivity type
Region, it is configured on the 2nd semiconductor regions；Inner wall insulation film, it configures the inwall in groove, and the groove is from the 3rd semiconductor regions
Upper surface extend and penetrate the 3rd semiconductor regions and the 2nd semiconductor regions；Coordination electrode, its side with the 2nd semiconductor regions
Face is opposed to configuration on the inner wall insulation film of the side of groove, is made up of polysilicon film；Bottom-side electrodes, it insulate with coordination electrode
Discretely configure on the inner wall insulation film of the bottom surface of groove；1st interlayer dielectric, it is to cover coordination electrode and bottom-side electrodes
Mode is filled in the inside of groove, is made up of bpsg film；And the 2nd interlayer dielectric, its configuration are exhausted in coordination electrode and the 1st interlayer
Between velum, suppress the diffusion of phosphorus, from the lower surface of coordination electrode at least one of distance of the bottom surface of groove, than from bottom surface
At least one of distance of the lower surface of electrode to the bottom surface of groove.
Invention effect
In accordance with the invention it is possible to provide the semiconductor device of the trench gate for the stable conductivity for making gate electrode.
Brief description of the drawings
Fig. 1 is the diagrammatic cross-section of the construction for the semiconductor device for showing embodiments of the present invention.
Fig. 2 is the in-built schematic diagram of the groove for the semiconductor device for showing embodiments of the present invention.
Fig. 3 is the process diagrammatic cross-section for illustrating the manufacture method of the semiconductor device of embodiments of the present invention
One of ().
Fig. 4 is the process diagrammatic cross-section for illustrating the manufacture method of the semiconductor device of embodiments of the present invention
(two).
Fig. 5 is the process diagrammatic cross-section for illustrating the manufacture method of the semiconductor device of embodiments of the present invention
(three).
Fig. 6 is the process diagrammatic cross-section for illustrating the manufacture method of the semiconductor device of embodiments of the present invention
(four).
Fig. 7 is the process diagrammatic cross-section for illustrating the manufacture method of the semiconductor device of embodiments of the present invention
(five).
Fig. 8 is the process diagrammatic cross-section for illustrating the manufacture method of the semiconductor device of embodiments of the present invention
(six).
Fig. 9 is the process diagrammatic cross-section for illustrating the manufacture method of the semiconductor device of embodiments of the present invention
(seven).
Figure 10 is the process diagrammatic cross-section for illustrating the manufacture method of the semiconductor device of embodiments of the present invention
(eight).
Figure 11 is the schematic diagram of another construction of the inside of the groove for the semiconductor device for showing embodiments of the present invention.
Figure 12 is the signal of another construction of the interlayer dielectric for the semiconductor device for showing embodiments of the present invention
Figure.
Figure 13 is the diagrammatic cross-section of the construction of the semiconductor device for the variation for showing embodiments of the present invention.
Figure 14 is the diagrammatic cross-section of the construction for the semiconductor device for showing other embodiments of the present invention.
Figure 15 is the diagrammatic cross-section of the construction for the semiconductor device for showing other embodiments of the present invention.
Figure 16 is the diagrammatic cross-section of the construction for the semiconductor device for showing other embodiments of the present invention.
Figure 17 is the schematic diagram of another construction of the inside of the groove for the semiconductor device for showing embodiments of the present invention.
Figure 18 is the schematic diagram of another construction of the inside of the groove for the semiconductor device for showing embodiments of the present invention.
Label declaration
10 drift regions；20 bases；30 launch sites；40 inner wall insulation films；50 gate electrodes；60 collecting zones；65 termination area；
70 interlayer dielectrics；71 the 1st interlayer dielectrics；72 the 2nd interlayer dielectrics；73 heat oxide films；80 collecting electrodes；90 transmitting electricity
Pole；100 grooves；150 bottom-side electrodes.
Embodiment
Below, embodiments of the present invention are described with reference to.In following accompanying drawing, to same or similar part
Mark same or similar label.It is the relation of thickness and planar dimension, each it should however be noted that accompanying drawing is schematically to scheme
The ratio of partial length etc. is different from actual product.Therefore, specific size should be judged with reference to the following description
Size.Also, the relation that also the includes accompanying drawing mutual size to each other certainly part different with ratio.
Also, embodiment described below is the apparatus and method that example is used to the technological thought of the present invention be embodied
Mode, the shape of component parts, construction, configuration etc. be not defined as following modes by technological thought of the invention.The present invention
Embodiment various changes can be carried out in the range of claims.
The semiconductor device of embodiments of the present invention has as shown in Figure 1：The 1st semiconductor regions (drift of 1st conductivity type
Move area 10)；2nd semiconductor regions (base 20) of the 2nd conductivity type, it is configured on the 1st semiconductor regions；1st conductivity type
3rd semiconductor regions (launch site 30), it is configured on the 2nd semiconductor regions.Inner wall insulation film is configured with the inwall of groove
40, the flute profile turn into extend from the upper surface of the 3rd semiconductor regions and penetrate the 3rd semiconductor regions and the 2nd semiconductor regions and
Reach the 1st semiconductor regions.
The interarea extension of layered product of the groove along above-mentioned semiconductor regions, the length of the groove in the direction of extension are wider than groove
Spend W length.Fig. 1 shows the section vertical with the direction of groove extension.
Semiconductor device shown in Fig. 1 is the IGBT of trench gate, has and is opposed to configuration in groove with the side of base 20
Side inner wall insulation film 40 on coordination electrode (gate electrode 50).As shown in figure 1, the bottom surface electricity of the lower surface of gate electrode 50
The side of pole 150 does not contact with the inner wall insulation film 40 of the bottom surface of groove.In addition, semiconductor device has with the insulated separation of gate electrode 50
Configure the bottom-side electrodes 150 on the inner wall insulation film 40 of the bottom surface of groove.Bottom-side electrodes 150 electrically connect with launch site 30.
1st conductivity type and the 2nd conductivity type are reciprocal conductivity types.That is, if the 1st conductivity type be n-type, if the 2nd lead
Electric type is p-type, if the 1st conductivity type be p-type, if the 2nd conductivity type be n-type.Below, illustratively explanation the 1st conductivity type be n-type,
2nd conductivity type is the situation of p-type.
As shown in figure 1, between gate electrode 50 and bottom-side electrodes 150 and the lower surface of gate electrode 50 and inner wall insulation
Between film 40, interlayer dielectric 70 is embedded with the gap of the inside of the groove in bottom-side electrodes 150.Pass through layer insulation
Film 70 is by gate electrode 50 and the insulated separation of bottom-side electrodes 150.In semiconductor devices, from the lower surface of gate electrode 50 to the bottom of groove
The distance (hereinafter referred to as " the 1st distance d1 ") in face, than the distance from the lower surface of bottom-side electrodes 150 to the bottom surface of groove (hereinafter referred to as
For " the 2nd distance d2 ") grow, or the 1st distance d1 and the 2nd distance d2 equal.That is, positioned at the gate electrode 50 of the lower section of gate electrode 50
The thickness (the thickness sum for referring to inner wall insulation film 40 and interlayer dielectric 70 in Fig. 1) of dielectric film between drift region 10,
Thickness than the dielectric film between the bottom-side electrodes 150 of the lower section of bottom-side electrodes 150 and drift region 10 (refers to interior in Fig. 1
The thickness of wall dielectric film 40) it is thick or equal.
Drift region 10 is configured on an interarea of the collecting zone 60 of p-type.In addition, between drift region 10 and collecting zone 60
It is configured with the field termination area 65 of the impurity concentration n-type higher than drift region 10.Semiconductor dress is limited in using field termination area 65
The amount in the hole of drift region 10 is reached under the conducting state put from collecting zone 60.Also, suppress the cut-off shape in semiconductor device
The depletion layer extended under state from the upper surface of drift region 10 reaches collecting zone 60.It is configured with another interarea of collecting zone 60
The collecting electrodes 80 electrically connected with collecting zone 60.
Gate electrode 50 is arranged opposite across inner wall insulation film 40 and base 20.Hair is optionally configured on the top of base 20
Penetrate area 30.Emission electrode 90 is configured on interlayer dielectric 70, and emission electrode 90 is connected with base 20 and launch site 30.Pass through layer
Between dielectric film 70 gate electrode 50 and emission electrode 90 are electrically insulated.
In the semiconductor device shown in Fig. 1, across the surface of the base 20 opposed with gate electrode 50 of inner wall insulation film 40
It is the channel region to form raceway groove.That is, sent out as gate insulating film in the region between the gate electrode 50 and base 20 of inner wall insulation film 40
The effect of waving.Gate electrode 50 is at least arranged opposite with base 20 so that is formed in base 20 along groove from launch site 30 to drift
The raceway groove in area 10.Also, it is preferred that the end (end of the side of groove) of the corner side of the groove of gate electrode 50 extends to and compares base
20 and the interface of drift region 10 position low with the side of the groove position intersected, i.e. on drift region 10.Thereby, it is possible in base 20
In along groove be reliably formed raceway groove from launch site 30 to drift region 10, semiconductor device is reliably turned on.
As shown in figure 1, it is each configured with gate electrode 50 in the opposed side of the inwall of groove.Also, in the extension side with groove
Into vertical section, gate electrode 50 is continuously configured along the inwall of groove, and gate electrode 50 is configured without in the bottom surface of groove.
Here, the action to the semiconductor device shown in Fig. 1 illustrates.Between emission electrode 90 and collecting electrodes 80
Collector voltage as defined in application, the grid voltage as defined in application between emission electrode 90 and gate electrode 50.For example, colelctor electrode
Voltage is approximately 300V~1600V, and grid voltage is approximately 10V~20V.When semiconductor device so is set into conducting state, ditch
Road area is inverted to n-type from p-type and forms raceway groove.Electronics is in the raceway groove formed by being injected into drift from emission electrode 90
In area 10.Between collecting zone 60 and drift region 10 turn into along biasing, hole (hole) from collecting electrodes 80 via collecting zone 60 successively
It is moved to drift region 10, base 20.When continuing to increase electric current, the hole increase from collecting zone 60, hole accumulation
In the lower section of base 20.As a result, conducting voltage is modulated by conductivity to reduce.
Make semiconductor device from conducting state turn into cut-off state in the case of, control gate voltage make its than threshold value electricity
Force down.For example, grid voltage is set to reach and emitter voltage identical current potential or negative potential.Thus, the raceway groove of base 20 disappears
Lose, the injection from emission electrode 90 to the electronics of drift region 10 stops.The current potential of collecting electrodes 80 is higher than emission electrode 90, thus
Depletion layer extends from the interface of base 20 and drift region 10, and the hole accumulated in drift region 10 is leaked to emission electrode
90.Now, in semiconductor regions of the hole between groove and groove by and it is mobile.That is, the region between groove is the sucking-off in hole
Mouthful.
In the past, in the semiconductor device of trench gate, exist between the end of gate electrode and the end of bottom-side electrodes
Produce electric discharge and the problem of malfunction.But in the semiconductor device shown in Fig. 1, the width of groove is more than the depth of groove, groove
Bottom surface it is relatively flat on the whole.Also, the position of the side at least opposed with bottom-side electrodes 150 of the lower surface of gate electrode 50
Put, it is more upper in the position of the upper surface of the side of gate electrode 50 than bottom-side electrodes 150.Also, from the lower surface of gate electrode 50 to
Lack the side opposed with bottom-side electrodes 150 to the distance of the bottom surface of groove, it is more electric than from the bottom surface of the side opposed with gate electrode 50
Distance of the lower surface of pole 150 to the bottom surface of groove.As a result, the end in the end of gate electrode and bottom-side electrodes can be reduced
Produce and discharge and the situation of malfunction between portion.
In addition, in the semiconductor device shown in Fig. 1, gate electrode 50, gate electrode 50 are preferably configured without in the bottom surface of groove
Lower surface and the distance between groove it is longer than the side of gate electrode 50 and the distance between groove.Therefore, it is possible to reduce gate electrode 50
Feedback capacity (grid-inter-collector electric capacity) between collecting zone 60.
In addition, by configuring the bottom-side electrodes 150 with the same potential of launch site 30 on the bottom surface of groove, semiconductor device exists
Played a role under cut-off state as field plate, depletion layer can be made to be extended well from the bottom of groove to drift region 10.It is in addition, logical
The configuration bottom-side electrodes 150 on the bottom surface of groove are crossed, compared with the situation of gate electrode 50 is set in the entirety in groove, are further reduced
The feedback capacity of grid-inter-collector.In addition, in order to which bottom-side electrodes 150 are electrically connected with launch site 30, such as be embedded in
Interlayer dielectric 70 in groove sets through hole, the through hole is filled with electric conductor film, by bottom-side electrodes 150 and emission electrode 90
Electrical connection.Through hole can both be located at least a portion of active region, and the end that can also be located at bottom-side electrodes 150 (is partly led
The outer circumferential side of body device).
In addition, in the semiconductor device shown in Fig. 1, the 1st distance d1 of the preferably lower section of gate electrode 50 compares bottom-side electrodes
The 1st distance d2 length of 150 lower section.That is, the interval of gate electrode 50 and collecting zone 60 expands, thus, it is possible to further reduce grid
The feedback capacity of pole-inter-collector.
As described above, in the semiconductor device shown in Fig. 1, reduced in feedback capacity caused by the bottom surface of groove.Its result
It is that can shorten the switch time of semiconductor device.
Also, by making the 1st distance d1 longer than the 1st distance d2, as shown in Fig. 2 the end 51 of gate electrode 50 and bottom surface electricity
The distance of the end 151 of pole 150 and the end 51 of gate electrode 50 and corner 101 (bottom surface of groove and the border of side of groove
Portion) distance expand.As a result, it can suppress between the end 51 of gate electrode 50 and the end 151 of bottom-side electrodes 150
The generation of electric discharge and the generation of the electric discharge between the end 51 of gate electrode 50 and the corner 101 of groove.Therefore, shown in Fig. 1
Semiconductor device in, electrical characteristic can be made stable.
Further, since by gate electrode 50 and the separate configuration of bottom-side electrodes 150, in the position away from these electrodes, the angle of groove
The pressure-resistant reduction in portion 101.In order to suppress the pressure-resistant reduction, preferably gate electrode 50 is configured near the corner 101 of groove.Cause
This, as shown in Fig. 2 it is preferred that the position of the lower surface of gate electrode 50 than the upper surface of bottom-side electrodes 150 position on the lower.
Also, as shown in Fig. 2 it is preferably formed as following inner wall insulation film 40 so that configuration is in the region of the bottom surface of groove
It is thickness, thicker than configuring thickness in the side of groove and the region opposed with base 20.With following tendency：In broadening gate electrode
During 50 width, caused parasitic capacitance increase between the gate electrode 50 and semiconductor regions in the bottom surface of groove.But pass through
The thickness of inner wall insulation film 40 is thickeied in the bottom surface of groove, the parasitic capacitance can be reduced.
But because the configuration of inner wall insulation film 40 plays a role in the region of the side of groove as gate insulating film, thus
It is limitary to thicken the thickness of inner wall insulation film 40 in the side of groove.Therefore, the configuration with inner wall insulation film 40 is in groove
The thickness in the region of side is compared, and thickness of the configuration of inner wall insulation film 40 in the region of the bottom surface of groove is thickeied.For example, by
Thickness of the wall dielectric film 40 in the bottom surface of groove is set to about 300nm, and the thickness in the side of groove is set into about 150nm.
Inside is configured with the width W of the groove of gate electrode 50 in width to fixation degree, as described below, semiconductor
The conducting voltage of device reduces, and pressure-resistant raising.E.g., about 3 μm~20 μm of the width W of groove during such case.
First, the reasons why conducting voltage reduces is illustrated.When semiconductor device is in the conduction state, channel region is being formed at
Raceway groove in by and from emission electrode 90 mainly along groove side move electronics be injected into drift region 10.In groove
The thickness of the drift region 10 of the lower section of bottom surface is, for example, 30 μm~180 μm, sufficiently wide compared to the width W of groove.Therefore, even groove
Width W when broadening, the electronics moved along groove is diffused in the region than groove depth in drift region 10.Thus, not only groove it
Between region the collecting zone 60 of underface and the interface of drift region 10, and in the scope broader than its collecting zone 60 and drift
Moving the interface in area 10 also turns into along biasing, and hole is moved in drift region 10 from collecting zone 60.
Hindered from the movement in the hole that collecting zone 60 is moved through coming by the bottom surface of groove, hole is accumulated in the bottom surface of groove
In neighbouring drift region 10, and produce conductivity modulation.When the width W of groove is wider, hole is more likely to accumulate in the bottom surface of groove
In neighbouring drift region 10.Therefore, reduced to the hole that emission electrode 90 moves, conducting voltage reduces.
In addition, when the interval S of groove and groove is wider, the lower section that causes that base 20 can not be accumulated in and moved to base 20
The amount increase or chip area increase in hole.Therefore, in order to reduce conducting voltage, the preferably width W of groove is wider than interval S.
Below, illustrate by the width W of enlarged slot, the reasons why the pressure-resistant raising of semiconductor device.Make semiconductor device
When turning into cut-off state from conducting state, depletion layer extends not only from the PN junction with base 20 from the bottom periphery of groove
Into drift region 10.Now, the extended mode of preferably depletion layer is the same and expands to broader scope.Depletion layer extension not
In the case of uniform or narrow, pressure-resistant reduction.In the case where the width W of groove is narrower, the corner as the groove of electric field concentration point
101 is relatively near each other, thus in the underface of the bottom surface of groove, and depletion layer has good uniformity and expands to wide scope.But
In the case that the width W of groove is wider, the corner 101 of groove is each other farther out, thus the underface of the bottom surface of the groove between corner 101
Depletion layer more uniformly or expand to broader scope.Therefore, it is pressure-resistant in the wider semiconductor devices of the width W of groove
Improve.
Also, by making the interval S-phase of groove and groove to narrowing, the pressure-resistant raising of semiconductor device.This is based on following
Reason.That is, the depth as shallow of the depletion layer of the underface of the depth ratio groove of the depletion layer in region between groove.At interval, S is wider
When, further planarized from the depletion layer extended with the PN junction of base 20 in the region between groove.Therefore, the consumption of the bottom surface of groove
Layer turns into the part being connected with the depletion layer of the sideways expansion from groove further shape obtained from deformation to the greatest extent.Therefore, electric field collection
In depletion layer deformation part be pressure-resistant reduction near the corner 101 of groove.It is therefore preferable that being spaced, S is narrow to arrive certain journey
Degree, such as make interval S narrower than the width W of groove.
As described above, in the semiconductor device shown in Fig. 1, the width W of preferably groove is wider, interval S is narrower.For example, shape
Into following groove, in top view, the length of the long side direction of groove extension is longer than the width W of groove, and the width W of groove compares phase
Adjacent groove and the interval S of groove are wide.
In the case where the width W of groove is wider, there is the increased tendency of feedback capacity between grid-colelctor electrode.But
In the semiconductor device shown in Fig. 1, by the way that in the configuration of the bottom surface of groove, using the capacitance part of bottom-side electrodes 150, grid can be reduced
Feedback capacity between pole-colelctor electrode.
Here, it is preferred that the width of bottom-side electrodes 150 is more than the thickness of bottom-side electrodes 150.Thereby, it is possible to suppress gate electrode 50
The part opposed with bottom-side electrodes 150, make gate electrode 50 close to the corner 101 of groove.As a result, being capable of suppressor grid-transmitting
Electric capacity between pole, it is ensured that pressure-resistant.
However, because chip area is limitary, thus in the case where setting chip size and fixing, in the width of enlarged slot
When spending W, raceway groove bar number is reduced.Now, when channel region ratio shared in the chip size of semiconductor device is decreased to necessarily
During degree, the saturation voltage increase between colelctor electrode-emitter stage.Therefore, the electric conduction caused by the reduction because of raceway groove bar number
When the effect of the rising of pressure is more than the effect for making hole accumulation be reduced and conducting voltage by the width W of enlarged slot, semiconductor dress
The conducting voltage put rises.
The present inventors according to above-mentioned viewpoint studied as a result, it is preferred that the width W of groove is about 3 μm~20 μm.Separately
Outside, the width W of more preferably groove is about 5 μm~13 μm.According to the research of the present inventors, the situation for being about 7 μm in the width W of groove
Under, it most effectively can reduce conducting voltage.Because the depth of groove ordinarily be about 5 μm, thus the knot that the width W of groove is expanded
Fruit is the width W situation bigger than the depth of groove for producing groove.
As described above, in the semiconductor device of embodiments of the present invention, from the lower surface of gate electrode 50
It is the 1st distance d1 to the bottom surface of groove, longer than the 2nd distance d2 from the lower surface of bottom-side electrodes 150 to the bottom surface of groove.Accordingly, it is capable to
Enough feedback capacities further reduced between grid-colelctor electrode.As a result, the switching speed of semiconductor device improves.Also,
The generation in the electric discharge of the inside of semiconductor device can be suppressed.Therefore, electrical characteristic is stable.In addition, the width for passing through enlarged slot
W is spent, high withstand voltage, the semiconductor device of low conducting voltage can be realized.
3~Figure 10 of reference picture illustrates the manufacture method of the semiconductor device of embodiments of the present invention.Fig. 3~Figure 10 is illustrated
Go out the region for including a groove.In addition, manufacture method described below is an example, can utilize certainly includes its variation
Various manufacture methods in addition inside are realized.
As shown in figure 3, using impurity diffusion method or epitaxial growth method in n-P is formed on the drift region 10 of type-The base of type
20, n-The drift region 10 of type is formed at p+The collecting zone 60 and n of type+On the layered product of the field termination area 65 of type.For example, utilize
Impurity diffusion method injects n-type impurity in drift region 10 from the upper surface of drift region 10, is then diffused by annealing,
Base 20 is set to be formed as substantially the same thickness.N-type impurity in base 20 is, for example, boron (B).Then, as shown in figure 4, example
N is such as formed selectively using a part for ion implanting and the upper surface for being diffused in base 20+The launch site 30 of type.
Then, extend from the upper surface of launch site 30 as shown in figure 5, being formed and penetrate launch site 30 and base 20, end
Reach the groove 100 of drift region 10.Groove 100 can be formed using such as photoetching technique and etching technique.
Then, as shown in fig. 6, forming inner wall insulation film 40 on the internal face of groove 100.For example, utilize thermal oxidation method shape
Into silica (SiO2) it is used as inner wall insulation film 40.The thickness of inner wall insulation film 40 e.g., about 100nm~300nm.
After inner wall insulation film 40 is formed, the polysilicon film 500 that with the addition of impurity is formed in entire surface.Thus, such as Fig. 7
It is shown, in the inside of groove 100, polysilicon film 500 is configured on inwall dielectric film 40.Now, as shown in fig. 7, the inside of groove 100
Do not filled by polysilicon film 500, polysilicon film 500 is formed along the wall of groove 100.
Then, as shown in figure 8, in the groove side formed with gate electrode 50 and the groove bottom formed with bottom-side electrodes 150
The surface of polysilicon film 500, mask 510 is formed using photoetching technique and etching technique etc..As shown in figure 8, it is being configured at groove side
Gap is provided between the mask 510a in face and the mask 510b for being formed at groove bottom.For example, mask 510a and mask 510b is used
Oxide-film etc..
Etching, using the mask 510 shown in Fig. 8, is etched with mask by isotropic etching to polysilicon film 500.
Now, using the etching mode entered from mask 510a and mask 510b gap, to the polysilicon configured in the corner of groove 100
Film 500 is etched.Thus, as shown in figure 9, forming gap between the lower surface of polysilicon film 500 and inner wall insulation film 40.
Handled more than, form the gate electrode 50 being made up of polysilicon film 500.Now, it is exhausted in the lower surface of gate electrode 50 and inwall
Complete gap is not formed between velum 40, in the situation that the lower surface of gate electrode 50 and the part of inner wall insulation film 40 contact
Under, the 1st distance d1 and the 2nd distance d2 are equal.Also, work as and formed between the lower surface of gate electrode 50 and inner wall insulation film 40
In the case of full gap, by the process of Figure 10 below, gap is filled by interlayer dielectric 70, thus the 1st distance d1 ratios
2nd distance d2 grows.
Also, the bottom for being residued in groove 100 as bottom-side electrodes 150 by the region that mask 510b is covered of polysilicon film 500
Face.In the manufacture method, gate electrode 50 and bottom-side electrodes 150 are formed in same process, the material of gate electrode 50 and
The material of bottom-side electrodes 150 is identical.
After mask 510 is removed, as shown in Figure 10, the interlayer dielectric 70 of landfill groove 100 is formed in entire surface.So
Afterwards, the emission electrode 90 being connected with launch site 30 and base 20 is formed on interlayer dielectric 70.For example, in interlayer dielectric 70
A part set opening portion, expose launch site 30 and the surface of base 20, formed fill the opening portion emission electrode 90.
In addition, forming collecting electrodes 80 on the back side of collecting zone 60, the semiconductor device shown in Fig. 1 is completed.
The manufacture method of the semiconductor device of embodiments of the present invention from the description above, it can make from gate electrode 50
Lower surface to the bottom surface of groove 100 the 1st distance d1, than from the lower surface of bottom-side electrodes 150 to the bottom surface of groove 100 the 2nd away from
It is long from d2 or same.As a result, the electric capacity between grid-colelctor electrode can be reduced.In addition, it can suppress in grid electricity
Electric discharge between the end 51 of pole 50 and the end 151 of bottom-side electrodes 150 and in the end 51 of gate electrode 50 and the corner of groove
Electric discharge between 101.
In addition, make the Film Thickness Ratio in the bottom surface of groove in the thick inner wall insulation film 40 of the thickness of the side of groove, energy to be formed
Enough using following method etc..That is, oxide-film is integrally formed in the inwall of groove 100, then etching removes the oxide-film on side.
Then, oxide-film is formed again on the side of groove and on bottom surface.
In addition, illustrate to form gate electrode 50 and bottom-side electrodes 150 in same process above exemplarily, make gate electrode
50 material and the material identical situation of bottom-side electrodes 150.But it is also possible to the He of gate electrode 50 is formed in different processes
Bottom-side electrodes 150.In this case, the material of gate electrode 50 and the material of bottom-side electrodes 150 can also be different.
, it is necessary in the lower section of gate electrode 50 seamlessly in the forming process for the interlayer dielectric 70 that reference picture 10 illustrates
Configure interlayer dielectric 70.In order to seamlessly bury layer insulation in the corner surrounded by gate electrode 50 and bottom-side electrodes 150
Film 70, preferably interlayer dielectric 70 use the reflow higher material relatively soft when being formed.
For example, interlayer dielectric 70 is adapted to using bpsg film of phosphorus (P) containing high concentration etc..But in gate electrode 50
In the case of using polysilicon film, when bpsg film and gate electrode 50 contact, phosphorus diffusion to gate electrode 50.As a result, grid are electric
The electric conductivity change of pole 50, the deterioration in characteristics of semiconductor device.
Therefore, in order that the electric conductivity of gate electrode 50 is constant, preferably as shown in figure 11, in gate electrode 50 and by bpsg film structure
Into the 1st interlayer dielectric 71 between configure the 2nd interlayer dielectric 72, the diaphragm as the diffusion for preventing phosphorus.2nd interlayer is exhausted
Velum 72 uses the material for the electric conductivity for not influenceing gate electrode 50.For example, to be suitable for the 2nd interlayer exhausted for NSG films using TEOS etc.
Velum 72.In addition, the 2nd interlayer dielectric 72 can also be formed as thinner than the 1st interlayer dielectric 71.By forming thicker interlayer
Dielectric film 71, interlayer dielectric 70 can be seamlessly filled in groove.
As described above, it is preferred to using by the 1st interlayer of material that is reflow higher but changing the electric conductivity of gate electrode 50
Dielectric film 71 and do not influence gate electrode 50 electric conductivity the interlayer dielectric 70 that is laminated of the 2nd interlayer dielectric 72.By
This, can seamlessly fill the inside of groove until corner, and prevent the characteristic of semiconductor device using interlayer dielectric 70
Deterioration.
Alternatively, it is also possible to the surface thermal oxide by making gate electrode 50, as shown in figure 12, in the interlayer of gate electrode 50 and the 2nd
Heat oxide film 73 is configured between dielectric film 72.Using fine and close and uniform film thickness heat oxide film 73, can more reliably prevent
Diffusion of the phosphorus from the 1st interlayer dielectric 71 being made up of bpsg film to gate electrode 50.
In addition, in order that interlayer dielectric 70 is easily accessible to corner, as shown in figure 11, make the lower surface shape of gate electrode 50
As connection gate electrode 50 in the end of the corner side of groove and gate electrode 50 in the end of the side of bottom-side electrodes 150 or grid
At least a portion missing of the lower surface of electrode 50.Also, wedge surface can also be formed in the lower surface of gate electrode 50 so that connection
Gate electrode 50 is in the end of the corner side of groove and gate electrode 50 in the end of the side of bottom-side electrodes 150.That is, by making gate electrode 50
With being shortened close to the side of groove 100, interlayer dielectric 70 is easily accessible to angle the distance of lower surface and the bottom surface of groove 100
Portion.
Here, in Figure 11 semiconductor device, the end (gate electrode from gate electrode 50 in the lower surface of the corner side of groove
50 in the end of the corner side of groove) to groove bottom surface distance d3, than from bottom-side electrodes 150 the lower surface of the side of gate electrode 50 to
The distance d5 length of the lower surface of groove.Also, (gate electrode 50 is the bottom of in the end of the lower surface of the side of bottom-side electrodes 150 for gate electrode 50
The end of the side of face electrode 150) it is located at than bottom-side electrodes 150 in the high position in the upper surface of the side of gate electrode 50, gate electrode 50 is the bottom of at
The end of the lower surface of the side of face electrode 150 is located at than bottom-side electrodes 150 in the top position in the upper surface of the side of gate electrode 50.And
And the distance d4 from gate electrode 50 in the end of the side of bottom-side electrodes 150 to the bottom surface of groove, than from bottom-side electrodes 150 in gate electrode
The distance d6 of the upper surface of 50 sides to the bottom surface of groove grows.Moreover, the lower surface of gate electrode 50 is formed as connecting gate electrode 50 in groove
Corner side lower surface end and gate electrode 50 in the end of the side of bottom-side electrodes 150.In the lower surface of gate electrode 50 extremely
Few part missing, such as wedge surface is provided with the lower surface of gate electrode 50., being capable of suppressor in Figure 11 semiconductor device
Electric discharge of the electrode 50 between the end of the side of bottom-side electrodes 150 and bottom-side electrodes 150, reduce the feelings of semiconductor device malfunction
Condition.
Here, can also be as shown in Figure 17 semiconductor device, from gate electrode 50 at the end of the lower surface of the corner side of groove
Portion to the bottom surface of groove distance d3, and the bottom-side electrodes 150 from the side opposed with gate electrode 50 lower surface to groove upper table
The distance d5 in face is identical.Moreover, in Figure 17 semiconductor device, and gate electrode 50 is in the lower surface of the side of bottom-side electrodes 150
End be located at than bottom-side electrodes 150 in the top position in the upper surface of the side of gate electrode 50, be provided with the lower surface of gate electrode 50
Wedge surface so that the distance d4 from gate electrode 50 in the lower surface of the side of bottom-side electrodes 150 to the bottom surface of groove, than to bottom-side electrodes 150
Upper surface distance d6 length.Therefore, in Figure 17 semiconductor device, can also reduce in the end of gate electrode and bottom surface electricity
Produce and discharge and the situation of malfunction between the end of pole.Although also, semiconductor device increase of the feedback capacity than Figure 11,
But Figure 17 semiconductor device is by the way that gate electrode 50 is configured near the corner 101 of groove, improve groove corner 101 it is attached
Near is pressure-resistant, thus is preferable mode.
Alternatively, it is also possible to as shown in figure 18, the distance d3 from gate electrode 50 in the end of the corner side of groove to the bottom surface of groove,
Distance d5 than lower surface to the bottom surface of groove of the bottom-side electrodes 150 from the side opposed with gate electrode 50 is short.Moreover, in Figure 18
Semiconductor device in, and gate electrode 50 in the end of the side of bottom-side electrodes 150 positioned at more top than the upper surface of bottom-side electrodes 150
Position, be provided with wedge surface in the lower surface of gate electrode 50 so that from gate electrode 50 in the end of the side of bottom-side electrodes 150 to the bottom of groove
The distance d4 in face, it is longer than the distance d6 from the upper surface of bottom-side electrodes 150 to the bottom surface of groove.In Figure 18 semiconductor device,
Also the generation of the electric discharge between the end of gate electrode and the end of bottom-side electrodes can be suppressed, reduce the situation of malfunction.
Although also, semiconductor device increase of the feedback capacity than Figure 11, Figure 18 semiconductor device is by the way that gate electrode 50 is configured
Near the corner 101 of groove, further improve pressure-resistant near the corner 101 of groove, thus be preferred mode.
Alternatively, it is also possible to as shown in figure 11, bottom-side electrodes 150 are made to be formed as trapezoidal shape so that the following table of bottom-side electrodes 150
Face is more than the upper surface of bottom-side electrodes 150, the thickness of bottom-side electrodes 150 with close to the side of groove 100 and it is thinning.Thus, layer
Between dielectric film 70 be also easily accessible to corner.
Also, as shown in figure 11, the lower surface of bottom-side electrodes 150 and gate electrode 50 are between the end of the corner side of groove
Distance is longer than the distance between the end of the side of bottom-side electrodes 150 of upper surface and gate electrode 50 of bottom-side electrodes 150.Thus, energy
Enough make the distortion in electric field caused by gate electrode 50 and the gap location of bottom-side electrodes 150 gentle.
In the case where the width W of groove 100 is expanded, in the top of groove 100, the upper surface generation of interlayer dielectric 70 is recessed
The narrower intervals on the top of hole, emission electrode 90 and gate electrode 50, it is possible to pressure-resistant reduction.Accordingly it is also possible to as shown in figure 11
The upper surface of gate electrode 50 is set to form wedge surface.By making the upper surface of gate electrode 50 be reduced with the central portion close to groove 100,
The pressure-resistant reduction of the semiconductor device caused by due to gate electrode 50 and emission electrode 90 can be suppressed.
<Variation>
Figure 13 shows the variation of the semiconductor device of embodiments of the present invention.In the semiconductor device shown in Figure 13
In, the middle section of the thickness of inner wall insulation film 40 in the side away from groove is thicker than in the neighboring area of the side close to groove.That is,
Distance from the lower surface of bottom-side electrodes 150 to the bottom surface of groove is longer than in the neighboring area of bottom-side electrodes 150 in middle section.
Therefore, it is possible to reduce the electric capacity between emitter stage-colelctor electrode of semiconductor device.
(other embodiment)
The present invention is described using embodiment as described above, but should not be construed the part for forming present disclosure
Narration and accompanying drawing be for limiting the present invention.It is clear that those skilled in the art can expect respectively from present disclosure
Alternate embodiments, embodiment and the application technology of formula various kinds.
Semiconductor device illustrated above is IGBT example.But semiconductor device can also use trench gate
Other constructions switch element.Figure 14 shows that semiconductor device is one of the MOSFET of trench gate.Half shown in Figure 14
Conductor device is the MOSFET of the construction in the drain region 160 that n-type is configured with the lower surface of drift region 10.Following table in drain region 160
Face is configured with the drain electrode 180 electrically connected with drain region 160.
Even the semiconductor device of the MOSFET shown in Figure 14, by making the bottom surface from the lower surface of gate electrode 50 to groove
The 1st distance d1, longer than the 2nd distance d2 from the lower surface of bottom-side electrodes 150 to the bottom surface of groove, can also reduce grid-leakage
Feedback capacity between pole.As a result, the switching speed of semiconductor device improves.Even in addition, trench gate
MOSFET, interlayer dielectric 70 can also be made to be formed as the 1st interlayer dielectric 71 and the 2nd interlayer dielectric 72 shown in Figure 11
The construction being laminated.Therefore, it is possible to seamlessly fill the inside of groove using interlayer dielectric 70 until corner, and prevent
The deterioration of the characteristic of semiconductor device.
In addition, show in the entire surface of the lower surface of gate electrode 50, make from gate electrode 50 in Fig. 1 semiconductor device
Lower surface to the bottom surface of groove distance than the distance from the lower surface of bottom-side electrodes 150 to the bottom surface of groove situation.But
In a part for the lower surface of gate electrode 50, make from gate electrode 50 in the lower surface of the side of bottom-side electrodes 150 to the bottom surface of groove
Distance, than the bottom-side electrodes 150 from the side opposed with gate electrode 50 lower surface to the bottom surface of groove distance.In addition,
The position of the side in groove of gate electrode 50 is set to, extends to the upper surface of side than bottom-side electrodes 150
Position is on the lower and roughly the same with the position of the lower surface of the side of bottom-side electrodes 150.In this case, also can
Reduce the feedback capacity between gate-to-drain.Can also be as Figure 16~Figure 18 semiconductor device, not in the He of gate electrode 50
2nd interlayer dielectric 72/ and heat oxide film 73 are set between the 1st interlayer dielectric 71 being made up of bpsg film as preventing phosphorus
The diaphragm of diffusion.
For example, in the semiconductor device shown in Figure 15, the 2nd interlayer dielectric 72/ and heat oxide film 73 are not provided with, by
1 interlayer dielectric 71 forms interlayer dielectric 70.Wherein, the end of the bottom-side electrodes side of gate electrode 50 exists than bottom-side electrodes 150
The upper surface of the side of gate electrode 50 is top, and from a part for the lower surface of gate electrode 50, (gate electrode 50 is at the end of the side of bottom-side electrodes 150
Portion) to the distance d4 of the bottom surface of groove, it is longer than the distance d6 from the upper surface of bottom-side electrodes 150 to the bottom surface of groove.Also, from grid electricity
Another part (gate electrode 50 is in end of the corner side of groove) of the lower surface of pole 50 to the bottom surface of groove distance d3, and from bottom surface
The distance d5 of the lower surface of electrode 150 to the bottom surface of groove is identical.In the semiconductor device shown in Figure 15, can reduce grid-
Feedback capacity between drain electrode.Further, it is possible to improve in the pressure-resistant of the corner of groove.Moreover, it can reduce at the end of gate electrode 50
Produce and discharge and the situation of malfunction between portion and the end of bottom-side electrodes 150.
In addition, can also be another part (grid from the lower surface of gate electrode 50 in the semiconductor device shown in Figure 15
Electrode 50 is in the end of the corner side of groove) to the distance d3 of the bottom surface of groove, than the bottom surface from the lower surface of bottom-side electrodes 150 to groove
Distance d5 length.The feedback capacity between gate-to-drain can be also reduced in the semiconductor device.Further, it is possible to reduce
Produce and discharge and the situation of malfunction between the end of gate electrode 50 and the end of bottom-side electrodes 150.
In addition, can also be another part (grid from the lower surface of gate electrode 50 in the semiconductor device shown in Figure 15
Electrode 50 is in the end of the corner side of groove) to the distance d3 of the bottom surface of groove, than the bottom surface from the lower surface of bottom-side electrodes 150 to groove
Distance d5 it is short.In the semiconductor device, it can also reduce between the end of gate electrode 50 and the end of bottom-side electrodes 150
Produce and discharge and the situation of malfunction.Further, it is possible to further improve in the pressure-resistant of the corner of groove.Moreover, by making grid electric
Pole 50 is located at the electric field that until the position of the adjacent corner of groove, can further relax the adjacent corner of groove.
Also, in Figure 16~Figure 18 semiconductor device, wedge surface is set in the lower surface of gate electrode 50, but can not also
Wedge surface is set in the lower surface of gate electrode 50, and makes gate electrode 50 in the height and gate electrode of the lower surface of the side of bottom-side electrodes 150
50 height in the bottom surface of the corner side of groove is identical.Also, in Figure 16~Figure 18 semiconductor device, gate electrode can also be made
50 height in the end of the side of bottom-side electrodes 150 is lower than the height of the upper surface of bottom-side electrodes 150.In above-mentioned semiconductor device
In, diffusion of the phosphorus from the 1st interlayer dielectric 71 being made up of bpsg film to gate electrode 50 can be more reliably prevented from.
Also, in Figure 16~Figure 18 semiconductor device, can also adapt to be not provided with bottom-side electrodes 150 and known in using
Trench gate other constructions switch element.In above-mentioned semiconductor device, can be more reliably prevented from phosphorus from by
Diffusion of the 1st interlayer dielectric 71 that bpsg film is formed to gate electrode 50.
Also, bottom-side electrodes 150 are set to trapezoidal shape in fig. 11 so that the thickness of bottom-side electrodes 150 is with close to groove
100 side and it is thinning, i.e., the width of the upper surface of bottom-side electrodes 150 be less than bottom-side electrodes 150 lower surface width.But
It is that bottom-side electrodes 150 can also be set to trapezoidal shape as shown in figure 16 so that the thickness of bottom-side electrodes 150 is with close to groove
100 side and it is thickening.Thus, the layer insulation being sandwiched between bottom-side electrodes 150 and gate electrode 50 and inner wall insulation film 40
The part of film 70 and the stickiness of bottom-side electrodes 150 and gate electrode 50 are good, the transmitting on interlayer dielectric 70 is welded in
During electrode 90, it can suppress to produce skew in interlayer dielectric 70.
In addition, Figure 16 semiconductor device changes bottom-side electrodes 150 compared with Figure 11 semiconductor device, otherwise scheming
It is terraced the bottom-side electrodes 150 of the semiconductor device such as Figure 11 can also be replaced into 17 or Figure 18 semiconductor device
The bottom-side electrodes 150 of shape, the i.e. width of the upper surface of bottom-side electrodes 150 are less than the width of the lower surface of bottom-side electrodes 150.
In this case, the lower surface of gate electrode 50 and the distance of bottom-side electrodes 150, thus energy can be substantially ensured that in a thickness direction
Enough electric discharges suppressed well between gate electrode 50 and bottom-side electrodes 150.
In addition, illustratively illustrate that semiconductor device is the situation of n-channel type, but when semiconductor device is p-channel type,
The apparent effect that can also obtain the present invention.
So, the present invention is certainly comprising various embodiments not described here etc..Therefore, technical scope of the invention
It can only utilize and be determined according to the specific item of related invention that above-mentioned explanation is appropriate claims.
Claims (16)
1. a kind of semiconductor device, it is characterised in that the semiconductor device has：
1st semiconductor regions of the 1st conductivity type；
2nd semiconductor regions of the 2nd conductivity type, it is configured on the 1st semiconductor regions；
3rd semiconductor regions of the 1st conductivity type, it is configured on the 2nd semiconductor regions；
Inner wall insulation film, it configures the inwall in groove, and the groove extends from the upper surface of the 3rd semiconductor regions and penetrated described
3rd semiconductor regions and the 2nd semiconductor regions；
Coordination electrode, the inwall that the side of itself and the 2nd semiconductor regions is opposed to configure in the side of the groove are exhausted
On velum；And
Interlayer dielectric in the coordination electrode,
The coordination electrode is made up of polysilicon film,
The interlayer dielectric has：
1st interlayer dielectric, the material of the 1st interlayer dielectric make the coordination electrode when being contacted with the coordination electrode
Electric conductivity changes；And
2nd interlayer dielectric, it is configured between the coordination electrode and the 1st interlayer dielectric so that the control electricity
The electric conductivity of pole is constant.
2. semiconductor device according to claim 1, it is characterised in that
The semiconductor device also has bottom-side electrodes, and the bottom-side electrodes are configured described with the coordination electrode insulated separation
On the inner wall insulation film of the bottom surface of groove,
The interlayer dielectric will insulate between the coordination electrode and the bottom-side electrodes.
3. semiconductor device according to claim 2, it is characterised in that
1st interlayer dielectric is made up of bpsg film, and the 2nd interlayer dielectric is made up of NSG films.
4. the semiconductor device according to Claims 2 or 3, it is characterised in that
The semiconductor device also has heat oxide film of the configuration between the 2nd interlayer dielectric and the coordination electrode.
5. a kind of semiconductor device, it is characterised in that the semiconductor device has：
1st semiconductor regions of the 1st conductivity type；
2nd semiconductor regions of the 2nd conductivity type, it is configured on the 1st semiconductor regions；
3rd semiconductor regions of the 1st conductivity type, it is configured on the 2nd semiconductor regions；
Inner wall insulation film, it configures the inwall in groove, and the groove extends from the upper surface of the 3rd semiconductor regions and penetrated described
3rd semiconductor regions and the 2nd semiconductor regions；
Coordination electrode, the inwall that the side of itself and the 2nd semiconductor regions is opposed to configure in the side of the groove are exhausted
On velum, it is made up of polysilicon film；
Bottom-side electrodes, it is configured with the coordination electrode insulated separation on the inner wall insulation film of the bottom surface of the groove；
1st interlayer dielectric, it fills in the inside of the groove, is made up of bpsg film, by the coordination electrode and the bottom surface
Insulated between electrode；And
2nd interlayer dielectric, it is configured between the coordination electrode and the 1st interlayer dielectric, suppresses the diffusion of phosphorus,
The distance of the bottom surface from least a portion of the lower surface of the coordination electrode to the groove, it is more electric than from the bottom surface
Distance of at least a portion of the lower surface of pole to the bottom surface of the groove.
6. semiconductor device according to claim 5, it is characterised in that
2nd interlayer dielectric is made up of NSG films.
7. the semiconductor device according to claim 5 or 6, it is characterised in that
The semiconductor device also has heat oxide film of the configuration between the 2nd interlayer dielectric and the coordination electrode.
8. the semiconductor device described in any one in claim 1~7, it is characterised in that
The position of the lower surface of the coordination electrode than the upper surface of the bottom-side electrodes position on the lower.
9. the semiconductor device described in any one in claim 1~8, it is characterised in that
The lower surface of the coordination electrode is formed as wedge surface as follows：The lower surface of the coordination electrode and institute
The distance between described bottom surface of groove is stated to shorten with the side close to the groove.
10. the semiconductor device described in any one in claim 1~9, it is characterised in that
The bottom-side electrodes are following trapezoidal shape：The thickness of the bottom-side electrodes becomes with the side close to the groove
It is thin.
11. the semiconductor device described in any one in claim 1~10, it is characterised in that
Distance from the lower surface of the bottom-side electrodes to the bottom surface of the groove the bottom-side electrodes it is described under
It is long in neighboring area in middle section ratio in surface.
12. the semiconductor device described in any one in claim 1~11, it is characterised in that
In top view, the length on the bearing of trend of the groove is longer than the width of the groove, and the width ratio of the groove
The interval of the adjacent groove is wide.
13. the semiconductor device described in any one in claim 1~12, it is characterised in that
The thickness of the inner wall insulation film in the region of the bottom surface of the groove is configured in, than being configured in the groove
The region of the side is thick.
14. the semiconductor device described in any one in claim 1~13, it is characterised in that
In the entire surface of the lower surface of the coordination electrode, from the lower surface of the coordination electrode to the groove
The distance of the bottom surface, than the distance from the lower surface of the bottom-side electrodes to the bottom surface of the groove.
15. the semiconductor device described in any one in claim 1~13, it is characterised in that
From a part for the bottom-side electrodes side of the lower surface of the coordination electrode to the bottom surface of the groove away from
From, than the distance from the lower surface of the bottom-side electrodes to the bottom surface of the groove, from the institute of the coordination electrode
Another part of lower surface is stated to the distance of the bottom surface of the groove, with the lower surface from the bottom-side electrodes to described
The distance of the bottom surface of groove is identical.
16. the semiconductor device described in any one in claim 1~15, it is characterised in that
The position of the side at least opposed with the bottom-side electrodes of the lower surface of the coordination electrode, than bottom surface electricity
The position of the upper surface of the coordination electrode side of pole is upper.
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| JP2016-144324 | 2016-07-22 | ||
| JP2016144324 | 2016-07-22 | ||
| JP2016163168A JP2018022858A (en) | 2016-07-22 | 2016-08-23 | Semiconductor device |
| JP2016-163168 | 2016-08-23 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112740550A (en) * | 2018-10-24 | 2021-04-30 | 株式会社村田制作所 | Resonance device |
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| JPH09199614A (en) * | 1996-01-23 | 1997-07-31 | Sony Corp | Semiconductor storage and its manufacture |
| JP2000012851A (en) * | 1998-06-24 | 2000-01-14 | Nec Corp | Field-effect transistor and manufacture thereof |
| CN104465769A (en) * | 2013-09-20 | 2015-03-25 | 三垦电气株式会社 | Semiconductor device |
| JP2015162533A (en) * | 2014-02-27 | 2015-09-07 | サンケン電気株式会社 | semiconductor device |
| JP2015201615A (en) * | 2014-03-31 | 2015-11-12 | サンケン電気株式会社 | Semiconductor device and method of manufacturing the same |
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| JPH05129541A (en) * | 1991-10-30 | 1993-05-25 | Takehide Shirato | Semiconductor device |
| JPH08255791A (en) * | 1995-03-17 | 1996-10-01 | Nec Corp | Formation of interlayer insulating film of semiconductor device |
| JPH09199614A (en) * | 1996-01-23 | 1997-07-31 | Sony Corp | Semiconductor storage and its manufacture |
| JP2000012851A (en) * | 1998-06-24 | 2000-01-14 | Nec Corp | Field-effect transistor and manufacture thereof |
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| CN112740550A (en) * | 2018-10-24 | 2021-04-30 | 株式会社村田制作所 | Resonance device |
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