JPH08255791A - Formation of interlayer insulating film of semiconductor device - Google Patents

Abstract

PURPOSE: To form an interlayer insulating film covering a MOS transistor of a titanium salicide structure by suppressing degradation of transistor characteristics and coagulation of titanium silicide film. CONSTITUTION: A silicon dioxide film 21 is formed by the LPCVD process, a PSG film 31 is formed by the APCVD process using ozone, TEOS, etc., as raw materials, these films are heat-treated in a 750 deg.C nitrogen atmosphere, and a silicon dioxidg film 41 is formed by the ECR-PECVD process, and the surface of this silicon dioxide film 41 is polished by the CMP process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an interlayer insulating film in a semiconductor device, and more particularly to a method for forming an interlayer insulating film covering a titanium salicide structure MOS transistor formed on the surface of a silicon substrate.

[0002]

2. Description of the Related Art As semiconductor devices have been highly integrated, wirings have been miniaturized and multilayered. In order to realize a fine multilayer wiring structure, it is essential that the film characteristics of the interlayer insulating film be excellent and that the interlayer insulating film be flat. In particular, in the film characteristics, it is required that the residual stress is small, the relative dielectric constant is small, and the residual water content is small. Also,
The degree of flattening of the interlayer insulating film has a great influence on the dimensional accuracy of the upper-layer metal wiring formed on the interlayer insulating film. This is because the step difference caused by the multi-layered wiring exceeds the depth of focus in photolithography, and the wiring processing dimensions at the high portion and the bottom portion of this step differ. Therefore, it is indispensable to completely reduce such a step and improve the wiring dimensional accuracy.

Conventionally, when the lower layer wiring is made of a polycrystalline silicon film, the interlayer insulating film between the aluminum type wiring which is the upper layer wiring and these lower layer wiring is 850 to 9
BPSG film reflowed at 00 ° C has been frequently used. This is because these lower layer wirings can withstand a relatively high temperature heat treatment. On the other hand, with the recent miniaturization of the device structure, the dimensions of the impurity diffusion layer and the gate electrode forming the source / drain regions have been reduced in the MOS transistor. As a result, the decrease in signal processing speed due to the increase in resistance of the gate electrode and the impurity diffusion layer has become remarkable. In order to solve this problem, a method of forming a titanium silicide film in a self-aligned manner on the upper surface of the gate electrode made of a polycrystalline silicon film and the surface of the impurity diffusion layer to form a MOS transistor having a titanium salicide structure is proposed. is there.

The specific contents of this method are as follows, for example, with reference to Japanese Patent Laid-Open No. 63-133622.

First, a field oxide film for element isolation is formed on the surface of a silicon substrate of one conductivity type, and a gate oxide film is formed in an element formation region. After the polycrystalline silicon film pattern is formed in the region where the gate electrode is to be formed, sidewall spacers made of a silicon dioxide film are formed on the side surfaces of the polycrystalline silicon film pattern. Reverse conductivity type impurities are introduced, the above-mentioned polycrystalline silicon film pattern becomes a reverse conductivity type polycrystalline silicon gate electrode, and the surface of the silicon substrate is self-aligned with the field oxide film and the sidewall spacers. A reverse conductivity type diffusion layer for the drain region is formed. Next, the film thickness 50-60
nm titanium film and 20 nm thick titanium nitride film are formed on the entire surface, and the titanium film is silicidized in a nitrogen, helium, or argon atmosphere at 600 to 700 ° C. Then, the titanium nitride film and the unreacted titanium film are removed by an alkaline solution, and the titanium / silicide film is left only on the upper surface of the polycrystalline silicon gate electrode and the surface of the opposite conductivity type diffusion layer.

[0006]

However, there are the following problems in forming a multilayer wiring structure on a titanium salicide structure MOS transistor.

First, a BPSG film is usually used as an interlayer insulating film formed on a MOS transistor. As described above, the BPSG film is reflowed by the high temperature heat treatment at about 900 ° C. and the surface is flattened. BP
The reflow of the SG film requires heat treatment at a temperature of 850 ° C. or higher. When a titanium salicide MOS transistor is heat-treated at such a temperature, in 1991,
I-E-E-Transaction-On-Electron-Devices, Vol. 38, No. 2, 262-
269 (IEEE-Transaction-on-
Electron-Devices, Vol. 38, N
o. 2, pp262-269, 1991), agglomeration of the titanium silicide film occurs. This phenomenon is likely to occur particularly on the upper surface of the polycrystalline silicon gate electrode having a fine line width. As a result, there arises a problem that the low resistance, which is the purpose of adopting the titanium salicide structure, cannot be achieved.

In order to avoid the problem of aggregation of the titanium silicide film, the reflow temperature of the BPSG film is set to 8
It is necessary to lower the temperature to 00 ° C or lower. However, at a temperature of 800 ° C. or lower, reflow of the BPSG film does not occur, so that the surface of the BPSG film cannot be flattened.
Further, the heat treatment at a temperature of 800 ° C. or lower does not sufficiently densify the BPSG film and reduce the residual water content of the BPSG film itself. As a result, the characteristic of the MOS transistor is deteriorated, especially the resistance to hot carrier is deteriorated.

Therefore, an object of the present invention is to suppress an increase in the resistance value of a titanium silicide film in forming an interlayer insulating film on a titanium salicide structure MOS transistor, and to improve the characteristics of the titanium salicide structure MOS transistor. An object of the present invention is to provide a method for forming an interlayer insulating film which does not deteriorate and facilitates formation of an upper metal wiring having a fine line width on the surface of the interlayer insulating film.

[0010]

A method of forming an interlayer insulating film of a semiconductor device according to the present invention is a method of forming a titanium salicide structure MO.
2 on the surface of the silicon substrate on which the S transistor is formed.
A step of forming a first insulating film made of silicon oxide,
A step of forming a silicon dioxide-based second insulating film containing at least phosphorus on the surface of the first insulating film;
A step of performing heat treatment in a nitrogen gas atmosphere of 0 ° C., a step of forming a third insulating film made of silicon dioxide on the surface of the second insulating film by a chemical vapor deposition method using high density plasma, And a step of planarizing the surface of the third insulating film by a chemical mechanical polishing method.

Preferably, the second insulating film is a PSG film formed by chemical vapor deposition or a spin-on-glass film containing phosphorus. The chemical vapor deposition method using the high-density plasma is a chemical vapor deposition method using electron cyclotron resonance, a chemical vapor deposition method using a helicon wave, or a chemical vapor deposition method using inductively coupled plasma. Further, the chemical vapor deposition method using the high density plasma is performed while applying an AC bias to the silicon substrate.

[0012]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a manufacturing process of a semiconductor device.
Referring to FIG. 2 and a sectional view of the semiconductor device, the first embodiment of the present invention is as follows.

First, a field oxide film 12 having a thickness of about 0.6 μm is formed in the element isolation region on the surface of the P-type silicon substrate 11, and a gate having a thickness of about 10 nm is formed on the element formation region on the surface of the P-type silicon substrate 11. Oxide film 13 is formed. A polycrystalline silicon film with a thickness of about 0.4 μm is formed on the entire surface,
This polycrystalline silicon film is patterned to form a polycrystalline silicon film pattern (not shown) in the area where the gate electrode is to be formed. A silicon dioxide film having a thickness of about 0.15 μm is formed on the entire surface, the silicon dioxide film is etched back, and the silicon dioxide film is formed on the side surface of the polycrystalline silicon film pattern.
Sidewall spacers 15 made of silicon oxide film
Is formed. By implanting arsenic ions, the polycrystalline silicon film pattern becomes the N ⁺ -type polycrystalline silicon gate electrode 14. At the same time, in the element formation region on the surface of the P-type silicon substrate 11, (source / drain regions)
The N ⁺ type diffusion layer 16 is formed in self-alignment with the field oxide film 12 and the sidewall spacers 15.

Next, a titanium film (not shown) having a thickness of about 30 nm is formed on the entire surface. 650 ℃ in nitrogen gas atmosphere,
The heat treatment for 30 seconds is performed by the lamp heating furnace, and the silicidation reaction occurs. As a result, a titanium silicide film (not shown) having a C49 structure is formed on the upper surface of the polycrystalline silicon gate electrode 14 and the surface of the N ⁺ type diffusion layer 16 in a self-aligned manner. The titanium nitride film and the unreacted titanium film are selectively removed by a mixed aqueous solution of hydrogen peroxide and ammonia. Subsequently, heat treatment is again performed at 750 ° C. for 10 seconds in a lamp heating furnace, and the titanium / silicide film having a C49 structure formed on the upper surface of the polycrystalline silicon gate electrode 14 and the surface of the N ⁺ type diffusion layer 16 undergoes phase transition. At these positions, titanium silicide films 17a and 17b having a C54 structure with a thickness of about 40 nm are formed. As a result, an N-channel MOS transistor having a titanium salicide structure is formed [FIG. 1 (a)]. The maximum step difference at this stage due to the one formed on the surface of the P-type silicon substrate 11 is about 0.7 μm.

Next, silane (SiH ₄ ) and oxygen (O ₂ )
A silicon dioxide film 21 having a thickness of about 0.2 μm (which is a first insulating film) is formed on the entire surface by a low pressure vapor deposition (LPCVD) method using and as source gases (FIG. 1B). . This LPCVD method uses a substrate temperature of 700 ° C. and a silane flow rate of 20.
0 sccm, oxygen flow rate 100 sccm, pressure 3 × 10 ²
It is performed under the condition of Pa. Although the MOS transistor in this embodiment is an N-channel type, when a CMOS transistor or the like is assumed, the silicon dioxide film 21 prevents diffusion of phosphorus from the PSG film formed in the next step to the MOS transistor. It will be. The silicon dioxide film 21 in this embodiment has tensile stress,
Although the thickness of the silicon dioxide film 21 is thin, if a thick silicon dioxide film is formed by this manufacturing method, it becomes an overhang shape, which is not preferable.

Next, tetraethyl orthosilicate (T
EOS, Si (OC ₂ H ₅ ) ₄ ) vaporized gas, trimethoxyphosphoric acid (TMP, PO (OCH ₃ ) ₃ ) vaporized gas, and ozone (O ₃ ) are used as source gases under atmospheric pressure vapor deposition (AP).
By the CVD method, the thickness (which is the second insulating film) is about 0.
A 5 μm PSG film 31 is formed on the entire surface. This PSG
The film 31 also has tensile stress, and the concentration of phosphorus in this PSG film 31 is about 5 mol%. The conditions of this APCVD method are as follows. The substrate temperature is 400 ° C. T
EOS is vaporized by bubbling nitrogen gas at 50 ° C,
The flow rate of this vaporized gas containing nitrogen gas is 1 SLM. TMP is vaporized by bubbling nitrogen gas at 40 ° C., and the flow rate of this vaporized gas containing nitrogen gas is also 1 SLM. The flow rate of ozone with oxygen as the carrier gas is 7.5.
SLM, and the concentration of ozone in the carrier gas at this time is about 5 vol. %. Then, heat treatment is performed at 750 ° C. for 30 minutes in an electric furnace in a nitrogen gas atmosphere. This heat treatment does not cause reflow of the PSG film 31, but the PSG film 31 is densified and the residual water content is reduced [FIG. 1 (c)]. The temperature of this heat treatment is 7
It is preferably in the range of 00 ° C to 800 ° C. 700
The heat treatment at a temperature lower than 0 ° C. does not cause the film quality improvement such as the densification of the PSG film 31 and the reduction of residual moisture as described above. Further, in the heat treatment at a temperature higher than 800 ° C., as described above, the titanium / silicide films 17a and 17b are formed.
Aggregation will occur.

Next, high density plasma vapor deposition (PECV)
D) by vapor phase growth using electron cyclotron resonance (ECR-PECVD), using silane and oxygen as source gases, the entire surface (which is the third insulating film) having a thickness of about 1.0 μm. A silicon oxide film 41 is formed. The silicon dioxide film 41 has compressive stress and is denser than the silicon dioxide film 21 and the PSG film 31. This 2
The silicon oxide film 41 is the silicon dioxide film 21 and PS.
By being laminated on the G film 31, the stress is relaxed. Further, since the silicon dioxide film 41 has a low hygroscopic property, the penetration of water into the silicon oxide film 21 and the PSG film 31 is suppressed by the silicon dioxide film 41. Silicon dioxide film 21, PS up to this stage
The total film thickness of the G film 31 and the silicon dioxide film 41 is about 1.7 μm. The conditions of the ECR-PECVD method are as follows. Flow rate of silane and oxygen is 40sc
cm and 60 sccm. Electron cyclotron resonance is performed under a pressure of 0.3 Pa, a frequency of 2.45 GHz, a microwave power of 2 kW, and a magnetic field strength of 8.75 × 10 ^-2 T. No high frequency bias is applied to the P-type silicon substrate 11 side. The deposition rate of the silicon dioxide film 41 at this time is about 600 nm / min [FIG.
(D)].

Next, by a chemical mechanical polishing (CMP) method, 2
The silicon oxide film 41 is polished by about 0.5 μm and becomes a silicon dioxide film 41a having a flattened surface. This completes the formation of the interlayer insulating film of this embodiment. The step on the surface of the P-type silicon substrate 11 at this stage is almost eliminated [FIG. 1 (e)]. This CMP is performed under the following conditions. For polishing, a colloidal silica (concentration 12 wt%) with an ammonium salt added, pH 7 to 8
The polishing agent of is used. The rotation speeds of the surface plate having the polishing pad and the polishing head for adsorbing the P-type silicon substrate 11 are 50 rpm and 100 rpm, respectively. The weight of the polishing head is 2.1 × 10 ⁴ Pa. The amount of abrasive added was 50 cc / min. The polishing rate of the silicon dioxide film 41 under this condition is about 100 nm / min.

Subsequently, a contact hole 51 reaching the N ⁺ type diffusion layer 16 and the like is formed by a known photolithography technique. Then, by a thermal chemical vapor deposition method using tungsten hexafluoride (WF ₆ ) gas and hydrogen (H ₂ ),
A tungsten film 52 having a thickness of about 1.2 μm is selectively grown in the contact hole 51. At this time, the flow rates of the tungsten hexafluoride gas and hydrogen are 20 sccm and 12
sccm, substrate temperature 270 ° C., pressure about 4 Pa
Is. Under these conditions, the growth rate of the tungsten film 52 is about 0.6 μm / min. Then,
A titanium film 53 having a thickness of about 50 nm, a titanium nitride film 54 having a thickness of about 0.1 μm, an aluminum-copper alloy film 55 having a thickness of about 0.5 μm, and a titanium nitride film 56 having a thickness of about 0.1 μm.
Are sequentially formed, and the metal laminated film made of these is patterned to form the upper layer metal wiring. This completes the manufacture of the semiconductor device employing this embodiment [FIG. 2].

By adopting the first embodiment, for example, a gate length of about 0.35 μm (polycrystalline silicon gate electrode 1
Even in an N-channel MOS transistor having a titanium salicide structure having a gate electrode line width of 4, the agglomeration of the titanium silicide film 17a formed on the upper surface of the polycrystalline silicon gate electrode 14 is avoided, and this titanium silicide film is prevented. The sheet resistance of 17a is a sufficiently low value (about 6Ω
/ □). Further, the variation of the threshold value (V _TH ) in the high temperature bias test at 1000 hours when the applied voltage to the MOS transistor is 5 V and the storage temperature is 150 ° C. is about −5.
%, Which proved to be sufficiently practical. This is a result of sufficient removal of residual water in the PSG film 31 by the heat treatment at 750 ° C. further,
Silicon dioxide film 41a having an upper surface (having a flat surface)
Since the inter-layer insulation film is made of, it is easy to form an upper metal wiring having a line width of 0.4 μm.

The first embodiment relates to a method of forming an interlayer insulating film formed on an N-channel MOS transistor having a titanium salicide structure, but this embodiment is a P-channel MOS transistor having a titanium salicide structure or a CMOS. It can also be applied to transistors. In this embodiment, P of titanium salicide structure having a gate length of 0.35 μm is used.
When applied to channel MOS transistors, titanium
Even if a titanium silicide film is formed of a titanium film having the same film thickness (about 30 nm) as that of the N-channel MOS transistor having the salicide structure, the titanium film formed on the upper surface of the polycrystalline silicon gate electrode in a self-aligned manner.
Sheet resistance of silicide film is about 4Ω / □ and N channel M
The value is lower than that of the OS transistor. This is titanium
The film thickness of the silicide film 17a was about 40 nm, whereas C5 formed in a self-aligned manner on the upper surface of the polycrystalline silicon gate electrode in the case of a P-channel MOS transistor.
This is because the titanium / silicide film having the four structure becomes thicker at about 63 nm.

In the first embodiment, the ECR-PECVD method is adopted as the chemical vapor deposition method using high density plasma for forming the silicon dioxide film 41 which is the third insulating film, but it is not limited to this. However, the chemical vapor deposition (HW-PECVD) method using a helicon wave or the chemical vapor deposition (IC-PE) using an inductively coupled plasma is not performed.
The CVD method can also be adopted. The ECR-PECVD method can be used only up to a silicon wafer having a diameter of about 6 inches due to the limitation of uniformity of plasma density.
A silicon wafer having a diameter of about 8 inches can be used in the -PECVD method, and a silicon wafer having a diameter of 8 inches or more can be used in the IC-PECVD method. Also, I
The CVD apparatus used for the C-PECVD method is ECR-PE.
The size can be easily reduced as compared with a CVD apparatus used for the CVD method or the HW-PECVD method.

FIG. 3 is a sectional view of the manufacturing process of the semiconductor device.
2, the second embodiment of the present invention is different from the first embodiment in the method of forming the second and third insulating films, and is as follows.

First, by the same method as in the first embodiment, up to the silicon dioxide film 21 having a thickness of about 0.2 μm (which is the first insulating film) is formed. After that, spin-on-glass (SOG) containing phosphorus is used as the second insulating film.
A PSG film 32 having a thickness of about 300 nm is formed on the entire surface. The raw material for the PSG film 32 is silanol (S
i (OH) ₄ ) oligomer as the main component, triethoxyphosphoric acid (PO (OC ₂ H ₅ ) ₃ ) was added (concentration: 5mo
It is an ethanol solution having a solid component concentration of 5 wt%. Since only one SOG film having a thickness of about 150 nm can be formed in one cycle process, the same process is repeated twice to form the PSG film 32. This process is as follows. The ethanol solution is dropped on the surface of the P-type silicon substrate 11 and spin coated at a rotation speed of 4000 rpm for 20 seconds. Prebaking is performed for 1 minute on a hot plate in a nitrogen atmosphere at 150 ° C. Further, heat treatment is performed at 300 ° C. for 60 minutes in an electric furnace in a nitrogen gas atmosphere. Thickness of about 300n by 2 cycle process
After the PSG film 32 having a thickness of m is formed, as in the first embodiment, at 750 ° C. and 30 ° C. in an electric furnace in a nitrogen gas atmosphere.
A heat treatment of 1 minute is performed. By this heat treatment, the PSG film 32 is densified and the residual water content is reduced [FIG.
(A)]. When the gap distance between the polycrystalline silicon gate electrodes 14 is narrow, the PSG film 32 of this embodiment, which is an SOG film, is superior in burying property between the PSG film 31 of the first embodiment and the PSG film 31 of the first embodiment. There is.

Next, the thickness (which is the third insulating film) is about 0.
The 8 μm silicon dioxide film 42 is formed by ECR-PECVD.
Formed by the method. ECR-PECVD in this example
The method is performed under the same conditions as the ECR-PECVD method in the first embodiment except that a high frequency bias of 13.56 MHz is applied to the P-type silicon substrate 11. The deposition rate of the silicon dioxide film 42 at this time is about 400 nm / min. The total film thickness of the silicon dioxide film 21, the PSG film 32 and the silicon dioxide film 42 up to this stage is about 1.3 μm [FIG.
(B)]. 2 formed under application of high frequency bias
The silicon oxide film 42 is more excellent in embedding property than the silicon dioxide film 41 in the first embodiment. The effect of the embedding property can also be obtained by applying an AC bias of the order of 100 kHz. In addition, HW-PECVD
Even when the method or IC-PECVD method is used, the same effect can be obtained by applying an AC bias to the P-type silicon substrate 11.

Next, a CM under the same conditions as in the first embodiment described above.
The silicon dioxide film 42a having a flattened surface by polishing the silicon dioxide film 42 by P method to about 0.5 μm
become. This completes the formation of the interlayer insulating film of this embodiment. The step on the surface of the P-type silicon substrate 11 at this stage is almost eliminated [FIG. 3 (c)].

Next, although not shown, contact holes reaching the N ⁺ type diffusion layer 16 and the like are formed by the same method as in the first embodiment, and the thickness of each contact hole is reduced to about 0. Selective growth of a tungsten film of 8 μm is performed. Furthermore, a titanium film with a thickness of about 50 nm and a thickness of about 0.1
A titanium nitride film having a thickness of 0.5 μm, an aluminum-copper alloy film having a thickness of about 0.5 μm, and a titanium nitride film having a thickness of about 0.1 μm are sequentially formed, and a metal laminated film made of these is patterned to form an upper metal wiring. It This completes the manufacture of the semiconductor device employing this embodiment.

The second embodiment has the effects of the first embodiment. Furthermore, as described above, this embodiment can form an interlayer insulating film having excellent embeddability as compared with the first embodiment. From this, it is possible to make the film thickness of the interlayer insulating film in this embodiment smaller than the film thickness of the interlayer insulating film in the first embodiment.

[0030]

As described above, according to the method for forming an interlayer insulating film of a semiconductor device of the present invention, a first insulating film made of silicon dioxide is formed, and a silicon dioxide containing silicon dioxide containing at least phosphorus is formed. A second insulating film is formed, heat treatment is performed in a nitrogen gas atmosphere at a temperature of at most 800 ° C., and a third silicon oxide layer is formed by a chemical vapor deposition method using high-density plasma.
Is formed, and the surface of the third insulating film is flattened by the CMP method to form an interlayer insulating film covering the titanium salicide structure MOS transistor formed on the surface of the silicon substrate.

Therefore, by adopting the present invention,
The increase in the resistance value of the titanium / silicide film is suppressed, the characteristic deterioration of the MOS transistor of the titanium / salicide structure is reduced, and the formation of the upper metal wiring having a fine line width on the surface of the interlayer insulating film is facilitated. .

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process according to a first embodiment of the present invention.

FIG. 2 is a sectional view of the first embodiment.

FIG. 3 is a cross-sectional view of the manufacturing process of the second embodiment of the present invention.

[Explanation of symbols]

11 P-type silicon substrate 12 Field oxide film 13 Gate oxide film 14 Polycrystalline silicon gate electrode 15 Side wall spacer 16 N ⁺ type diffusion layer 17a, 17b Titanium silicide film 21, 41, 41a, 42, 42a 2 Silicon oxide film 31, 32 PSG film 51 Contact hole 52 Tungsten film 53 Titanium film 54, 56 Titanium nitride film 55 Aluminum-copper alloy film

Claims (4)

[Claims] 1. A step of forming a first insulating film made of silicon dioxide on a surface of a silicon substrate on which a MOS transistor having a titanium salicide structure is formed, and at least phosphorus on the surface of the first insulating film. A step of forming a second insulating film of silicon dioxide containing silicon, a step of performing heat treatment in a nitrogen gas atmosphere at a temperature of at most 800 ° C., and a second insulating layer formed by a chemical vapor deposition method using high density plasma. A semiconductor device comprising: a step of forming a third insulating film made of silicon dioxide on the surface of the film; and a step of planarizing the surface of the third insulating film by a chemical mechanical polishing method. Method for forming interlayer insulating film of. 2. The interlayer insulating film of a semiconductor device according to claim 1, wherein the second insulating film is a PSG film formed by chemical vapor deposition or a spin-on-glass film containing phosphorus. Forming method. 3. The chemical vapor deposition method using the high density plasma is a chemical vapor phase epitaxy method using electron cyclotron resonance, a chemical vapor phase epitaxy method using a helicon wave, or a chemical vapor phase epitaxy method using inductively coupled plasma. 3. The method for forming an interlayer insulating film of a semiconductor device according to claim 1 or 2, wherein: 4. The method for forming an interlayer insulating film of a semiconductor device according to claim 3, wherein the chemical vapor deposition method using the high density plasma is performed while applying an AC bias to the silicon substrate.