JP4273268B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device that can be miniaturized to half a micron or less and has an interlayer insulating film, and a manufacturing method thereof.
[0002]
[Background]
In semiconductor devices such as LSIs, with the miniaturization, high density, and multi-layering of elements, the low temperature and flattening of the interlayer insulating film and the technology for forming metal wiring are important issues. Yes.
[0003]
The interlayer insulating film is formed, for example, by first growing a silicon oxide film by chemical vapor deposition at a low temperature on a substrate on which an element is formed, and then containing an impurity such as a silane compound, oxygen or ozone, and phosphorus or boron. A gas is reacted in a gas phase to form a BPSG film with a thickness of about several hundred nm to 1 μm. Thereafter, the BPSG film is fluidized and flattened by a so-called high temperature flow annealing at a high temperature in a nitrogen atmosphere. Through holes (contact holes) are formed in the interlayer insulating film thus formed, a barrier layer made of titanium or titanium nitride is formed, and then a metal wiring layer is formed.
[0004]
The planarization of the interlayer insulating film using such a BPSG film is performed using the high-temperature flow characteristics of the BPSG film, and the planarization progresses as the impurity concentration in the BPSG film and the annealing temperature are higher. In order for the BPSG film to obtain sufficient flatness and denseness, the annealing temperature is required to be 850 ° C. or higher.
[0005]
However, in order to prevent the occurrence of punch-through in a miniaturized MOS transistor, it is important to suppress the spread of an excessive source / drain impurity layer due to annealing. For example, the processing is performed at 850 ° C. or lower. It is desirable. In addition, when a silicide layer such as titanium is formed on the surface of the source / drain impurity layer constituting the MOS transistor, the high temperature annealing causes the silicide layer region to expand more than necessary, which causes deterioration of the junction characteristics. ing. For these reasons, development of a technique for forming an interlayer insulating film at a low temperature is required.
[0006]
Further, in order to further promote the planarization of the interlayer insulating film, after annealing the BPSG film, a silicon oxide film is further laminated by about 1 to 2 μm by a chemical vapor deposition method, and then planarized by chemical mechanical polishing (CMP). A method of performing the conversion process is also being performed. However, in this method, when a part of the BPSG film is exposed by polishing, it is difficult to control the film thickness and flatness because the uppermost silicon oxide film and the BPSG film have different polishing rates. Further, if a through hole is formed with the upper silicon oxide film remaining, it is difficult to form a through hole having a good shape because the etching rate of the silicon oxide film and the BPSG film is different. There is a problem that satisfactory embedding of the conductive film in the through hole cannot be achieved.
[0007]
For example, Japanese Patent Laid-Open No. 7-86284 discloses a method shown in FIGS. 7A to 7C in order to planarize an interlayer insulating film. In this technique, a first wiring layer 3 is formed on an insulating film 2 of a semiconductor substrate 1, and a first interlayer insulating film 4 is formed thereon. An SOG layer (spin-on-glass layer) 5 is applied thereon to alleviate the step between the first wiring layers 3, and the second interlayer insulating film 6 is thicker than the first wiring layer 3 thereon. Form. Then, the surface of the second interlayer insulating film 6 is planarized by the CMP method (see FIG. 7A). Thereafter, a through hole 7 is formed in the second interlayer insulating film 6, the SOG layer 5 and the first interlayer insulating film 4 (see FIG. 7B), and a second metal wiring layer 8 is formed thereon. Is formed (see FIG. 7C). In this technique, the SOG layer 5 is provided below the second interlayer insulating film 6 to prevent the formation of a concave groove in the interlayer insulating film.
[0008]
However, since the polishing rate is different between the uppermost second interlayer insulating film 6 and the SOG layer 5 below it, it is necessary to stop the polishing process in the second interlayer insulating film 6 in order to obtain good flatness. In addition to the difficulty in controlling the polishing process, it is necessary to increase the thickness of the second interlayer insulating film 6, which is disadvantageous in terms of cost and throughput. Further, when the through hole 7 is formed, the second interlayer insulating film 6 and the SOG layer 5 have different etching rates and polymer generation amounts, and a step or a constriction is formed on the side surface of the through hole 7. As a result, the contact of the barrier layer and the metal wiring layer 8 in the through hole 7 is deteriorated, and it is difficult to form a wiring by embedding aluminum by sputtering.
[0009]
[Problems to be solved by the invention]
An object of the present invention is to form a contact structure on a semiconductor substrate that can be formed at a low temperature as compared with an interlayer insulating film using a conventional BPSG film, has excellent flatness, and can form a highly reliable contact structure. It is an object of the present invention to provide a semiconductor device including the interlayer insulating film and a manufacturing method thereof.
[0010]
[Means for Solving the Problems]
The method of manufacturing a semiconductor device of the present invention includes a step of forming an interlayer insulating film on a semiconductor substrate including elements, a step of forming a through hole in the interlayer insulating film, and a barrier on the surface of the interlayer insulating film and the through hole. Including a step of forming a layer and a step of forming a conductive film on the surface of the barrier layer, and the step of forming the interlayer insulating film includes at least the following steps (a) to (e): .
[0011]
(A) forming a first silicon oxide film by reacting a silicon compound and hydrogen peroxide by chemical vapor deposition;
(B) a step of reacting a silicon compound, at least one of oxygen and a compound containing oxygen, and a compound containing an impurity by chemical vapor deposition to form a porous second silicon oxide film;
(C) a step of performing an annealing process at a temperature of 600 to 850 ° C .;
(D) forming a third silicon oxide film by reacting at least one of a silicon compound and a compound containing oxygen and oxygen by a chemical vapor deposition method; and
(E) A step of planarizing the third silicon oxide film by chemical mechanical polishing.
[0012]
According to this method for manufacturing a semiconductor device, the first silicon oxide film is formed by reacting the silicon compound and hydrogen peroxide by chemical vapor deposition in step (a), thereby providing excellent flatness. A layer can be formed. That is, the first silicon oxide film formed in this step (a) has high fluidity by itself and excellent self-flattening characteristics. The mechanism is that when a silicon compound and hydrogen peroxide are reacted by chemical vapor deposition, silanol is formed in the gas phase, and this silanol is deposited on the wafer surface to form a highly fluid film. It is thought that.
[0013]
For example, when monosilane is used as the silicon compound, silanol is formed by a reaction represented by the following formulas (1), (1) '.
[0014]
Formula (1)
SiH_Four+ 2H₂O₂  → Si (OH)_Four+ 2H₂
Formula (1) '
SiH_Four+ 3H₂O₂  → Si (OH)_Four+ 2H₂O + H₂
And the silanol formed by Formula (1), (1) 'turns into a silicon oxide, when water remove | eliminates by the polycondensation reaction shown by following formula (2).
[0015]
Formula (2)
Si (OH)_Four  → SiO₂+ 2H₂O
Examples of the silicon compound include monosilane, disilane, and SiH.₂Cl₂, SiF_Four, CH_ThreeSiH_ThreeInorganic silane compounds such as, and organic silane compounds such as tripropylsilane and tetraethoxysilane can be exemplified.
[0016]
The film-forming step of the step (a) is performed under the temperature condition of 0 to 20 ° C. when the silicon compound is an inorganic silicon compound, and 100 to 150 when the silicon compound is an organic silicon compound. It is desirable to carry out by a low pressure chemical vapor deposition method under a temperature condition of ° C. In this film forming step, if the temperature is higher than the upper limit, the polycondensation reaction of the formula (2) proceeds too much, so that the fluidity of the first silicon oxide film is lowered and good flatness is obtained. Hateful. On the other hand, when the temperature is lower than the lower limit, adsorption of decomposed water in the chamber and dew condensation outside the chamber occur, which makes it difficult to control the film forming apparatus.
[0017]
The first silicon oxide film formed in the step (a) is desirably formed with a film thickness that can sufficiently cover the step on the surface of the silicon substrate. The lower limit of the film thickness of the first silicon oxide film is preferably 300 to 1000 nm, although it depends on the height of the irregularities on the surface of the silicon substrate including the element. If the thickness of the first silicon oxide film exceeds the upper limit, cracks may occur due to the stress of the film itself.
[0018]
In the step (b), at least one of a silicon compound, a compound containing oxygen and oxygen, and a compound containing an impurity are reacted by chemical vapor deposition to form a porous layer on the first silicon oxide film. A second silicon oxide film is formed.
[0019]
This second silicon oxide film not only functions as a cap layer, but is porous, and in the annealing process in the subsequent step (c), gas components generated from the first silicon oxide film are gradually removed from the outside. Can be released. Further, in addition to being porous, the second silicon oxide film is doped with impurities such as phosphorus and boron, preferably phosphorus, to form Si-O of silicon oxide constituting the film. By weakening the intermolecular bonding force, the stress of the film can be relaxed, so that a layer that is moderately soft and hardly cracked can be formed. In addition, an important role of the second silicon oxide film is to function as a movable ion getter that impurities such as phosphorus contained in the silicon oxide film adversely affect the reliability characteristics of elements such as alkali ions. The concentration of impurities contained in the second silicon oxide film is preferably 1 to 6% by weight in view of the gettering function and the stress relaxation of the film described above.
[0020]
Further, since the second silicon oxide film has a compressive stress of 100 to 600 MPa, it has a function of preventing a tensile stress from increasing and cracking when the first silicon oxide film undergoes polycondensation. is there. Furthermore, the second silicon oxide film also has a function of preventing moisture absorption of the first silicon oxide film.
[0021]
The step (b) is preferably performed by a plasma chemical vapor deposition method with a high frequency of 1 MHz or less under a temperature condition of 300 to 450 ° C. By performing film formation under this temperature condition, the gas component is easily removed at the initial stage of annealing in the annealing of the step (c), and the reliability of the device is improved.
[0022]
Moreover, the compound containing oxygen used in the step (b) is dinitrogen monoxide (N₂O) is desirable. By using dinitrogen monoxide as the reaction gas, the dinitrogen monoxide in the plasma state is likely to react with the hydrogen bond (-H) of the silicon compound constituting the first silicon oxide film, so that the second silicon oxide film The desorption of gasification components (hydrogen, water) of the first silicon oxide film can be promoted even during film formation.
[0023]
The step (b) may be performed by a normal pressure chemical vapor deposition method under a temperature condition of 300 to 550 ° C. instead of the plasma chemical vapor deposition method. In this case, it is preferable that the oxygen-containing compound used in the step (b) is ozone.
[0024]
Further, it is desirable that the first silicon oxide film is exposed to an ozone atmosphere before forming the second silicon oxide film in the step (b). Through this step, ozone easily reacts with hydrogen bonds (—H) and hydroxyl groups (—OH) of the silicon compound constituting the first silicon oxide film, so that hydrogen and water in the first silicon oxide film Can be promoted.
[0025]
The thickness of the second silicon oxide film is preferably 100 nm or more in consideration of flatness and prevention of cracks.
[0026]
In the step (c), the first and second silicon oxide films formed in the steps (a) and (b) are densified by performing an annealing process at a temperature of 600 to 850 ° C. In addition, the moisture resistance is improved.
[0027]
In other words, regarding the first silicon oxide film, the polycondensation reaction according to the above-described equation (2) is completed at the initial stage of the annealing treatment, and water and hydrogen generated by this reaction are generated in the second silicon oxide film. The first silicon oxide film is discharged to the outside through the hole, and is densely formed with the gasification component sufficiently removed. The second silicon oxide film is changed from a porous to a dense film by annealing.
[0028]
In this annealing process, by setting the temperature to 600 ° C. or higher, the first and second silicon oxide films can be made sufficiently dense and, for example, the activity of impurities in the source and drain diffusion layers constituting the MOS element Can be sufficiently performed. Further, by setting the annealing temperature to 850 ° C. or lower, the interlayer insulating film can be planarized at a temperature lower than that required for the conventional BPSG film, and the first and second silicon oxide films Can be sufficiently densified. Further, if the annealing temperature is higher than 850 ° C., the source and drain diffusion layers are expanded more than necessary, causing problems such as punch-through, and it is difficult to miniaturize the element.
[0029]
By forming a porous second silicon oxide film on the first silicon oxide film, in the annealing process in the step (c), the wafer is placed directly at a temperature of 600 to 850 ° C. Thus, even if there is a sudden temperature change, the second silicon oxide film has an appropriate softness and can absorb the stress of the first silicon oxide film. Annealing can be performed without occurring.
[0030]
The annealing treatment in the step (c) is preferably performed by ramping annealing that raises the temperature continuously or intermittently in order to prevent the first silicon oxide film from cracking more reliably.
[0031]
Further, following the annealing treatment in the step (c), a third silicon oxide film is formed by a chemical vapor deposition method in the step (d), and further, in the step (e), the third silicon oxide film is formed. Is flattened by chemical mechanical polishing.
[0032]
In this planarization step, the first, second, and third silicon oxide films have substantially the same polishing rate, so that even when a plurality of silicon oxide films partially exist on the final polished surface, the flatness is improved. A good interlayer insulating film can be obtained, and the polishing amount can be easily managed.
[0033]
In the present invention, before the step (a), at least one of a silicon compound and a compound containing oxygen and oxygen is reacted by chemical vapor deposition to form a fourth silicon oxide film serving as a base layer. It is desirable to form. The base layer has a passivation function that prevents moisture and excess impurities from moving from the first silicon oxide film to the underlying silicon substrate, and a function that improves the adhesion between the silicon substrate and the first silicon oxide film.
[0034]
Further, in the manufacturing method according to the present invention, in the interlayer insulating film obtained by the above-described manufacturing method, a tapered through hole whose diameter gradually decreases from the upper end portion toward the bottom portion is obtained. That is, the etching rate of the first silicon oxide film is slightly lower than that of the second silicon oxide film, and the first silicon oxide film and the second silicon oxide film are in good contact at the interface between them. Therefore, a through hole having no level difference and an appropriate linear taper is formed. In such a tapered through hole, for example, an aluminum film or an aluminum alloy film can be embedded by sputtering, and a contact structure with excellent conductivity can be formed.
[0035]
In addition to those formed by anisotropic dry etching, the through hole is formed by combining isotropic wet etching and anisotropic dry etching so that the upper end of the through hole is further curved and tapered. It may be.
[0036]
In the through hole, first, a first aluminum film made of aluminum or an alloy containing aluminum as a main component is formed at a temperature of 200 ° C. or lower, and then aluminum or aluminum is heated at a temperature of 300 ° C. or higher. It is desirable to form a second aluminum film made of an alloy containing as a main component.
[0037]
Examples of the alloy containing aluminum as a main component include binary, ternary or higher alloys with at least one selected from copper, silicon, germanium, magnesium, cobalt, beryllium and the like.
[0038]
The semiconductor device formed by the above manufacturing method includes a semiconductor substrate including elements, an interlayer insulating film formed on the semiconductor substrate, a through hole formed in the interlayer insulating film, the interlayer insulating film, and the through hole. A barrier layer formed on the surface of the film, and a conductive film formed on the barrier layer,
The interlayer insulating film is
A first silicon oxide film formed by a polycondensation reaction between a silicon compound and hydrogen peroxide;
A second silicon oxide film formed on the first silicon oxide film and containing impurities;
A third silicon oxide film formed on the second silicon oxide film and planarized by chemical mechanical polishing;
[0039]
DETAILED DESCRIPTION OF THE INVENTION
1 to 4 are schematic cross-sectional views for explaining an embodiment of a semiconductor device manufacturing method and a semiconductor device according to the present invention. 1A to 1C and FIGS. 2A and 2B show the first-layer wiring region L1, and FIGS. 3A and 3B and FIGS. 4A and 4B show the first wiring region L1. A process for manufacturing the two-layer wiring region L2 will be described.
[0040]
Below, an example of the manufacturing method of a semiconductor device is shown.
[0041]
(A) The process shown in FIG. 1A will be described.
[0042]
(Element formation)
First, a MOS element is formed on the silicon substrate 11 by a generally used method. Specifically, for example, the field insulating film 12 is formed on the silicon substrate 11 by selective oxidation, and the gate oxide film 13 is formed in the active region. After adjusting the threshold voltage by channel implantation, SiH_FourA gate electrode 14 is formed by sputtering tungsten silicide on a polysilicon film grown by thermal decomposition of the film, further laminating a silicon oxide film 18 and etching it into a predetermined pattern. At this time, a wiring layer 37 made of a polysilicon film and a tungsten silicide film is formed on the field insulating film 12 as necessary.
[0043]
Next, phosphorus is ion-implanted to form the low concentration impurity layer 15 in the source region or the drain region. Next, after a side wall spacer 17 made of a silicon oxide film is formed on the side of the gate electrode 14, arsenic is ion-implanted, and an impurity is activated by an annealing process using a halogen lamp, whereby a source region or a drain region is formed. The high concentration impurity layer 16 is formed.
[0044]
Next, a vapor-grown silicon oxide film of 100 nm or less is formed, and the film is formed with HF and NH._FourA predetermined silicon substrate region is exposed by selective etching with a mixed aqueous solution of F. Subsequently, for example, titanium was sputtered with a film thickness of about 30 to 100 nm, and an opening was made by performing instantaneous annealing for about several seconds to 60 seconds at a temperature of 650 to 750 ° C. in a nitrogen atmosphere with oxygen controlled to 50 ppm or less. A titanium monosilicide layer is formed on the surface of the silicon substrate, and a titanium-rich titanium nitride (TiN) layer is formed on the silicon oxide film 18. Then NH_FourOH and H₂O₂The titanium nitride layer is etched away and a titanium monosilicide layer remains only on the surface of the silicon substrate. Further, lamp annealing at 750 to 850 ° C. is performed to disilicide the monosilicide layer, and the titanium silicide layer 19 is formed on the surface of the high concentration impurity layer 16 in a self-aligned manner.
[0045]
When the gate electrode 14 is formed of only polysilicon and exposed by selective etching, a titanium salicide structure is obtained in which both the gate electrode and the source and drain regions are separated by a sidewall spacer.
[0046]
The salicide structure may be made of tungsten silicide or molybdenum silicide instead of titanium silicide.
[0047]
(B) Next, the process shown in FIG. 1B will be described.
[0048]
(Formation of the first interlayer insulating film I1)
The first interlayer insulating film I1 is a four-layer silicon oxide film, that is, in order from the bottom, the fourth silicon oxide film 20, the first silicon oxide film 22, the second silicon oxide film 24, and the third silicon. An oxide film 26 is used.
[0049]
a. Formation of fourth silicon oxide film 20
First, tetraethoxylane (TEOS) and oxygen are reacted at 300 to 500 ° C. by a plasma chemical vapor deposition (CVD) method to form a fourth silicon oxide film 20 having a thickness of 100 to 200 nm. This silicon oxide film 20 is formed without SiH or oxidation of the silicide layer 19 and without SiH._FourThe film grown from the above has a higher insulating property and a slower etching rate with respect to an aqueous solution of hydrogen fluoride, resulting in a dense film.
[0050]
Here, the silicon oxide film 20 is formed directly on the titanium silicide layer 19, but if the film formation temperature at this time is high, the oxidizing gas and the titanium silicide react easily at the initial stage of film formation, so that cracks and peeling are likely to occur. The treatment temperature is preferably 600 ° C. or lower, more preferably 250 to 400 ° C. Then, after the silicon oxide film is formed on the titanium silicide layer 19 with a film thickness of about 100 nm at the above-described relatively low temperature, the temperature is set for annealing or vapor phase oxidation treatment that is exposed to an oxidizing atmosphere other than water vapor. There is no problem even if it is raised to about 900 ° C.
[0051]
b. Formation of first silicon oxide film 22
Next, preferably 2.5 × 10²Pa or less, more preferably 0.3 × 10²~ 2.0 × 10²Under reduced pressure of Pa, SiH as a carrier with nitrogen gas_FourAnd H₂O₂Is reacted by the CVD method to form the first silicon oxide film 22. The first silicon oxide film 22 has a film thickness that is at least larger than the step of the lower fourth silicon oxide film 20, that is, has a film thickness that sufficiently covers the step. The upper limit of the film thickness of the first silicon oxide film 22 is set to such an extent that no cracks are generated in the film. Specifically, the film thickness of the first silicon oxide film 22 is desirably thicker than the lower step, and is preferably set to 300 to 1000 nm in order to obtain better flatness.
[0052]
The film formation temperature of the first silicon oxide film 22 is related to the fluidity at the time of film formation. When the film formation temperature is high, the film fluidity is lowered and the flatness is impaired. The temperature is preferably set to 0 to 20 ° C, more preferably 0 to 10 ° C.
[0053]
H₂O₂The flow rate of SiH is not particularly limited, but SiH_FourThe flow rate is preferably at least twice the flow rate, and from the viewpoint of film uniformity and throughput, it is desirable to set the flow rate within a range of, for example, 100 to 1000 SCCM in terms of gas.
[0054]
The first silicon oxide film 22 formed in this step is in a silanol polymer state, has good fluidity, and has high self-flattening characteristics. Further, since the first silicon oxide film 22 includes many hydroxyl groups (—OH), it has a high hygroscopic property.
[0055]
c. Formation of second silicon oxide film 24
Next, SiH_Four, PH_ThreeAnd N₂In the presence of O, a PSG film (second silicon oxide film) 24 having a thickness of 100 to 600 nm is formed by reacting a gas by a plasma CVD method at a temperature of 300 to 450 ° C. and a high frequency of 200 to 600 kHz. The In consideration of the high hygroscopicity of the first silicon oxide film 22, the second silicon oxide film 24 is formed continuously following the formation of the first silicon oxide film 22, or Alternatively, it is desirable that the first silicon oxide film 22 be formed after being stored in an atmosphere not containing moisture.
[0056]
Further, it is considered that the second silicon oxide film 24 can easily and sufficiently desorb gas components such as water and hydrogen contained in the first silicon oxide film 22 by an annealing process performed later. Therefore, it is necessary to be porous. For this purpose, the second silicon oxide film 24 is formed, for example, by plasma CVD at a temperature of preferably 450 ° C. or lower, more preferably 300 to 400 ° C., preferably 1 MHz or lower, more preferably 200 to 600 kHz. And it is desirable to contain impurities, such as phosphorus. By including such an impurity in the second silicon oxide film 24, the second silicon oxide film 24 becomes more porous and not only relieves stress on the film but also has a gettering effect on alkali ions and the like. Can also have. Such impurity concentration is set in consideration of the gettering effect, stress resistance, and the like. For example, when the impurity is phosphorus, it is desirable that the impurity is contained at a ratio of 2 to 6% by weight.
[0057]
In plasma CVD, N is added as a compound containing oxygen.₂By using O, desorption of hydrogen bonds in the first silicon oxide film 22 is promoted. As a result, gasification components such as moisture and hydrogen contained in the first silicon oxide film 22 can be more reliably removed.
[0058]
The film thickness of the second silicon oxide film 24 has a role of adjusting the required thickness of the interlayer insulating film, and N₂In consideration of the function of O plasma to desorb hydrogen bonds, the thickness is preferably set to 100 nm or more, more preferably 100 to 600 nm.
[0059]
d. Annealing treatment
Next, annealing is performed at a temperature of 600 to 850 ° C. in a nitrogen atmosphere. By this annealing treatment, the first silicon oxide film 22 and the second silicon oxide film 24 are densified and have good insulating properties and water resistance. That is, by setting the annealing temperature to 600 ° C. or higher, the polycondensation reaction of silanol in the first silicon oxide film 22 is almost completely performed, and water and hydrogen contained in the film are sufficiently released. A dense film can be formed. In addition, by setting the annealing temperature to 850 ° C. or lower, miniaturization of the element can be achieved without adversely affecting the diffusion layer of the source region or drain region constituting the MOS transistor such as punch-through or junction leakage. Can do.
[0060]
In the annealing process, in order to reduce the influence of thermal strain on the first silicon oxide film 22, it is desirable to perform a ramping annealing in which the temperature of the wafer is increased stepwise or continuously. For example, when the temperature of the wafer is kept at about 400 ° C. and then raised to the annealing temperature (600 to 850 ° C.), the impurity concentration of the second silicon oxide film 24 can be considerably lowered. For example, when the impurity is phosphorus, it has been confirmed that the first silicon oxide film 22 does not crack even if the phosphorus concentration is 2 wt% or less, apart from the gettering effect of mobile ions.
[0061]
e. Formation of third silicon oxide film 26
Next, a third silicon oxide film 26 having a thickness of 1000 to 1500 nm is formed by plasma CVD at 350 to 400 ° C. using TEOS and oxygen.
[0062]
The TEOS-oxygen silicon oxide film using the plasma CVD method is dry etching that is the same as or slightly faster than the first silicon oxide film 22 and the second silicon oxide film 24 that have been annealed at a high temperature even when annealing is not performed. Have speed. This is a factor for obtaining a well-shaped contact hole without causing a constriction or a step on the side surface of the hole in the formation of the contact hole described later.
[0063]
(C) Next, the process shown in FIG. 1C will be described.
[0064]
(Smoothing by CMP)
Next, the third silicon oxide film 26 and, if necessary, the second silicon oxide film 24 and the first silicon oxide film 22 are polished by a CMP method to be smoothed. Since the first silicon oxide film 22, the second silicon oxide film 24, and the third silicon oxide film 26 have almost the same polishing rate, the second silicon oxide film 24 or the first silicon oxide film is polished by polishing. Even if a portion of the oxide film 22 is exposed on the surface, a flat surface can be obtained, and therefore the amount of polishing can be easily managed.
[0065]
For example, according to the study by the present inventors, the polishing rate of each silicon oxide film was as follows.
[0066]
First silicon oxide film (annealing temperature 800 ° C.); 250 nm / min
Second silicon oxide film (annealing temperature 800 ° C.); 250 nm / min
Third silicon oxide film (no annealing); 250 nm / min
BPSG film for comparison (annealing temperature 900 ° C.); 350 nm / min
(D) Next, the process shown in FIG.
[0067]
(Formation of contact holes)
Then CHF_ThreeAnd CF_FourThe silicon oxide films 20, 22, 24, and 26 constituting the first interlayer insulating film I1 are selectively anisotropically etched with a reactive ion etcher that mainly contains A .5 μm contact hole 32 is formed.
[0068]
The contact hole 32 has a tapered shape whose diameter decreases linearly from the upper end to the bottom. The taper angle θ cannot be generally defined depending on etching conditions or the like, but has an inclination of, for example, 5 to 15 degrees. The reason why such a tapered through hole is obtained is as follows. First, the silicon oxide films 20, 22, 24 and 26 have basically the same etching rate, and the first silicon oxide film 22 is that the etching rate is slightly lower than that of the second silicon oxide film 24, and secondly, the interfaces of the silicon oxide films are in very good contact. In such a tapered contact hole 32, an aluminum film can be satisfactorily deposited as will be described later.
[0069]
The dry etching rate of each silicon oxide film measured by the present inventors will be described below. Note that dry etching has a power of 800 W, an atmospheric pressure of 20 Pa, an etchant gas, and a CF._Four: CHF_Three: He = 1: 2: 9.
[0070]
First silicon oxide film (annealing temperature 800 ° C.); 525 nm / min
Second silicon oxide film (annealing temperature 800 ° C.); 550 nm / min
Third silicon oxide film (no annealing); 565 nm / min
BPSG film for comparison (annealing temperature 900 ° C.); 750 nm / min
(E) Next, the process shown in FIG.
[0071]
(Degassing treatment)
First, heat treatment including a degassing step will be described.
[0072]
1.5x10 in the lamp chamber^-FourLamp heating (heat treatment A) is performed at a base pressure of Pa or lower and a temperature of 150 to 250 ° C. for 30 to 60 seconds. Then 1 x 10 in another chamber^-1~ 15 × 10^-1Degassing is performed by introducing argon gas at a pressure of Pa and performing heat treatment (degassing step; heat treatment B) for 30 to 120 seconds at a temperature of 150 to 550 ° C.
[0073]
In this step, first, in the heat treatment A, moisture or the like adhering to the wafer can be removed mainly by heat-treating the entire wafer including the back surface and side surfaces of the wafer.
[0074]
Further, in the heat treatment B, mainly gasification components (H, H in the first silicon oxide film 22 constituting the first interlayer insulating film I1).₂O) can be removed. As a result, generation of gasification components from the first interlayer insulating film I1 can be prevented when forming the barrier layer and the aluminum film in the next step.
[0075]
In the present embodiment, the barrier layer 33 is formed of a multilayer film including a barrier film having a barrier function and a conductive film. The conductive film is formed between the barrier film and the impurity diffusion layer in order to increase the conductivity between the barrier film and the impurity diffusion layer formed on the silicon substrate, that is, the source region or the drain region. As the barrier film, a general substance such as titanium nitride or titanium tungsten can be preferably used. As the conductive film, a refractory metal such as titanium, cobalt, or tungsten can be used. These titanium, cobalt, and tungsten react with silicon constituting the substrate to form silicide.
[0076]
A barrier layer, for example, a TiN film / Ti film has a gasification component (O, H, H₂O, N) is dissolved, so that the gasification component in the first interlayer insulating film I1 can be removed before forming these films, so that the aluminum film can be formed well in the contact holes. It is extremely effective in performing. If the gasification component in the first interlayer insulating film I1 below the barrier layer is not sufficiently removed, the first interlayer insulating film I1 is formed at the temperature at which the barrier layer is formed (usually 300 ° C. or higher). The gasified component therein is released and this gas is taken into the barrier layer. Further, since this gas is detached from the barrier layer and formed at the interface between the barrier layer and the aluminum film when the aluminum film is formed, the adhesion and fluidity of the aluminum film are adversely affected.
[0077]
(Barrier layer deposition)
A titanium film having a thickness of 20 to 70 nm is formed as a conductive film constituting the barrier layer 33 by sputtering, and then a TiN film having a thickness of 30 to 150 nm is formed as a barrier film in another chamber. The sputtering temperature is selected in the range of 200 to 450 ° C. depending on the film thickness.
[0078]
Next, 0.1 × 10²~ 1.5 × 10²Titanium oxide can be formed in an island shape in the barrier layer by exposing it to oxygen plasma at a pressure of Pa for 10 to 100 seconds and annealing in a nitrogen or hydrogen atmosphere at 450 to 700 ° C. for 10 to 60 minutes. it can. It has been confirmed that the barrier property of the barrier layer can be improved by this treatment.
[0079]
This annealing treatment can also be performed by a heat treatment at 400 to 800 ° C. in a lamp annealing furnace containing at least several hundred ppm to several% oxygen, and the barrier property of the barrier layer can be similarly improved.
[0080]
Although not shown, a wetting layer made of titanium, cobalt, silicon, or the like may be formed on the surface of the barrier layer 33 for the purpose of improving wettability with respect to an aluminum film described later. By providing such a wetting layer, the fluidity of the first aluminum film can be increased. The thickness of the wetting layer may be usually several tens of nm or more.
[0081]
(Degassing treatment before aluminum film formation and wafer cooling)
First, before cooling the wafer, in the lamp chamber, 1.5 × 10^-FourA heat treatment (heat treatment C) is performed at a base pressure of Pa or lower and a temperature of 150 to 250 ° C. for 30 to 60 seconds to remove substances such as water attached to the substrate. Thereafter, before the aluminum film is formed, the substrate temperature is lowered to 100 ° C. or lower, preferably from room temperature to 50 ° C. This cooling step is important for lowering the substrate temperature raised by the heat treatment C. For example, a wafer is placed on a stage having a water cooling function to lower the wafer temperature to a predetermined temperature.
[0082]
By cooling the wafer in this way, when the first aluminum film is formed, the amount of gas released from the first interlayer insulating film I1 and the barrier layer 33 and the entire wafer surface can be reduced as much as possible. it can. As a result, it is possible to prevent the influence of gas adsorbing on the interface between the barrier layer 33 and the first aluminum film 34 and detrimental to coverage and adhesion.
[0083]
(Deposition of aluminum film)
First, at a temperature of 200 ° C. or less, more preferably 30 to 100 ° C., aluminum containing 0.2 to 1.0% by weight of copper is formed at a high speed by sputtering with a film thickness of 150 to 300 nm. An aluminum film 34 is formed. Subsequently, the substrate temperature is heated to 420 to 460 ° C. in the same chamber, and similarly, aluminum containing copper is formed at a low speed by sputtering to form a second aluminum film 35 having a thickness of 300 to 600 nm. . Here, in the film formation of an aluminum film, “high speed” cannot be generally defined by the film formation conditions or the design items of the device to be manufactured, but means a sputtering speed of approximately 10 nm / second or more, and “low speed” "Means a sputtering rate of approximately 3 nm / second or less.
[0084]
FIG. 5 shows an example of a sputtering apparatus for forming the first and second aluminum films 34 and 35. This sputtering apparatus includes a target 51 serving as an electrode and an electrode 52 serving as a stage in a chamber 50, and a substrate (wafer) W to be processed is installed on the electrode 52. A first gas supply path 53 is connected to the chamber 50, and a second gas supply path 54 is connected to the electrode 52. Argon gas is supplied from both gas supply paths 53 and 54. The temperature of the wafer W is controlled by the gas supplied from the second gas supply path 54. A means for discharging the gas in the chamber 50 is not shown.
[0085]
An example of controlling the substrate temperature using such a sputtering apparatus is shown in FIG. In FIG. 6, the horizontal axis indicates the elapsed time, and the vertical axis indicates the substrate (wafer) temperature. In FIG. 6, a line indicated by symbol “a” indicates a change in substrate temperature when the temperature of the stage 52 of the sputtering apparatus is set to 350 ° C., and a line indicated by symbol “b” indicates high-temperature argon through the second gas supply path 54. The figure shows a change in the substrate temperature when the temperature of the stage 52 is raised by supplying gas into the chamber.
[0086]
For example, the temperature control of the substrate is performed as follows. First, the temperature of the stage 52 is set in advance to a temperature (350 to 500 ° C.) for forming the second aluminum film. When the first aluminum film is formed, no gas is supplied from the second gas supply path 54, and the substrate temperature gradually rises as indicated by the symbol a in FIG. When forming the second aluminum film, the heated gas is supplied through the second gas supply path 54, whereby the substrate temperature rapidly rises as shown by the symbol b in FIG. It is controlled to be constant at a predetermined temperature.
[0087]
In the example shown in FIG. 6, the first aluminum film 34 is formed while the stage temperature is set to 350 ° C. and the substrate temperature is set to 125 to 150 ° C., and immediately after that, the second aluminum is formed. The film 35 is formed.
[0088]
In film formation of the aluminum film, it is important to control the power applied to the sputtering apparatus as well as the film formation speed and the substrate temperature control. That is, although related to the film formation speed, the first aluminum film 34 is formed at a high power, the second aluminum film 35 is formed at a low power, and power is switched when switching from a higher power to a lower power. It is important not to make zero. When the power is reduced to zero, an oxide film is formed on the surface of the first aluminum film even under reduced pressure, the wettability of the second aluminum film with respect to the first aluminum film is lowered, and the adhesion between the two is deteriorated. In other words, by always applying power, active aluminum can be continuously supplied to the surface of the aluminum film being formed, and the formation of an oxide film can be suppressed. Note that the magnitude of the power depends on the sputtering apparatus and the film formation conditions and cannot be defined unconditionally. However, for example, in the case of the temperature condition shown in FIG. It is desirable.
[0089]
In this way, by continuously forming the first aluminum film 34 and the second aluminum film 35 in the same chamber, the temperature and power can be controlled strictly, and at a lower temperature than in the prior art. A stable aluminum film can be formed efficiently.
[0090]
The film thickness of the first aluminum film 34 is such that a continuous layer can be formed with good step coverage, and the gasification component from the barrier layer 33 and the first interlayer insulating film I1 below the aluminum film 34 An appropriate range is selected in consideration of the ability to suppress the release of selenium, for example, 200 to 400 nm is desirable. The second aluminum film 35 is determined by the size of the contact hole and the aspect ratio thereof. For example, in order to fill a hole having an aspect ratio of about 3 and 0.5 μm or less, a film of 300 to 1000 nm is used. Thickness is necessary.
[0091]
(Formation of antireflection film)
Furthermore, the antireflection film 36 having a film thickness of 30 to 80 nm is formed by depositing TiN by sputtering in another sputtering chamber. Then Cl₂And BCl_ThreeThe deposited layer composed of the barrier layer 33, the first aluminum film 34, the second aluminum film 35, and the antireflection film 36 is selectively etched with an anisotropic dry etcher mainly composed of a gas of The metal wiring layer 40 is patterned.
[0092]
In the metal wiring layer 40 formed in this manner, aluminum with good step coverage without generating voids in a contact hole having an aspect ratio of 0.5 to 3 and a diameter of 0.2 to 0.8 μm. Has been confirmed to be embedded.
[0093]
(F) Next, the process shown in FIG.
[0094]
(Formation of second interlayer insulating film I2)
The second interlayer insulating film I2 basically has the same configuration as that of the first interlayer insulating film I1. That is, the second interlayer insulating film I2 is a four-layer silicon oxide film, that is, in order from the bottom, the eighth silicon oxide film 70, the fifth silicon oxide film 72, the sixth silicon oxide film 74, and the seventh silicon oxide film. The silicon oxide film 76 is formed. These silicon oxide films 70, 72, 74 and 76 are formed by the same method as the silicon oxide films 20, 22, 24 and 26 except for the annealing process. The main parts will be described below, but description of common matters is omitted.
[0095]
a. Formation of the eighth silicon oxide film 70
First, tetraethoxylane (TEOS) and oxygen are reacted at 300 to 500 ° C. by a plasma chemical vapor deposition (CVD) method, thereby forming an eighth silicon oxide film 70 having a thickness of 50 to 200 nm.
[0096]
b. Formation of fifth silicon oxide film 72
Next, preferably 2.5 × 10²Pa or less, more preferably 0.3 × 10²~ 2x10²Under reduced pressure of Pa, SiH as a carrier with nitrogen gas_FourAnd H₂O₂Is reacted by a CVD method at a temperature of 0 to 10 ° C. to form a fifth silicon oxide film 72. Similar to the first silicon oxide film 22, the fifth silicon oxide film 72 has a film thickness that is at least larger than the step of the lower eighth silicon oxide film 70, that is, sufficiently covers the step. The film is formed with a film thickness. The upper limit of the thickness of the fifth silicon oxide film 72 is set to such an extent that no cracks are generated in the film. Specifically, the film thickness of the fifth silicon oxide film 72 is desirably thicker than the lower step, and is preferably set to 500 to 1000 nm in order to obtain better flatness.
[0097]
The deposition temperature of the fifth silicon oxide film 72 is preferably set to 0 to 20 ° C., more preferably 0 to 10 ° C.
[0098]
The fifth silicon oxide film 72 formed in this step has high fluidity and excellent planarization characteristics.
[0099]
c. Formation of sixth silicon oxide film 74
Next, SiH4, PH_ThreeAnd N₂In the presence of O, a PSG film (sixth silicon oxide film) 74 having a film thickness of 100 to 600 nm is formed by performing a reaction by a plasma CVD method at a temperature of 300 to 450 ° C. and a high frequency of 200 to 600 kHz.
[0100]
Similarly to the second silicon oxide film 24, the sixth silicon oxide film 74 desorbs gasification components such as water contained in the fifth silicon oxide film 72 by an annealing process performed later. It is necessary to be porous in view of the fact that is easily and sufficiently performed. For this purpose, the sixth silicon oxide film 74 is formed by, for example, a high-frequency plasma CVD method with a temperature of preferably 450 ° C. or lower, more preferably 300 to 400 ° C., preferably 1 MHz or lower, more preferably 200 to 600 kHz. It is desirable that impurities such as phosphorus be included. When such impurities are contained in the second silicon oxide film 74, the second silicon oxide film 74 becomes more porous and can relieve stress on the film. Such impurity concentration is set in consideration of stress resistance, gettering effect, and the like. For example, when the impurity is phosphorus, it is preferably contained in a proportion of 1 to 6% by weight.
[0101]
In plasma CVD, N is added as a compound containing oxygen.₂By using O, desorption of hydrogen bonds in the fifth silicon oxide film 72 is promoted. As a result, gasification components such as moisture contained in the fifth silicon oxide film 72 can be more reliably removed.
[0102]
The film thickness of the sixth silicon oxide film 74 is preferably set to 100 nm or more, more preferably 200 to 600 nm.
[0103]
d. Annealing treatment
Next, annealing is performed at a temperature of 350 to 450 ° C. By this annealing treatment, the fifth silicon oxide film 72 and the sixth silicon oxide film 74 are densified and have good insulation and water resistance. That is, by setting the annealing temperature to 350 ° C. or higher, the polycondensation reaction of silanol in the fifth silicon oxide film 72 is almost completely performed, and moisture contained in the film is sufficiently released to be dense. A film can be formed. Moreover, by setting the annealing temperature to 450 ° C. or lower, the aluminum film constituting the first wiring layer 40 is not adversely affected.
[0104]
e. Formation of seventh silicon oxide film 76
Next, a third silicon oxide film 76 having a thickness of 1000 to 1500 nm is formed by plasma CVD at 350 to 400 ° C. using TEOS and oxygen.
[0105]
(G) Next, the process shown in FIG. 3B will be described.
[0106]
(Smoothing by CMP)
The seventh silicon oxide film 76 and, if necessary, the sixth silicon oxide film 74 and the fifth silicon oxide film 72 are polished and smoothed by a CMP method to a predetermined film thickness. With this smoothing treatment, even if the seventh silicon oxide film 74 or the fifth silicon oxide film 72 is partially exposed to the surface by polishing, a flat surface can be obtained, and thus the polishing amount can be easily managed. It is.
[0107]
(H) Next, the process shown in FIG.
[0108]
(Formation of via holes)
CHF_ThreeAnd CF_FourThe second interlayer insulating film I2 and the antireflection film 36 are selectively anisotropically etched by using a reactive ion etcher mainly containing the above, thereby forming a via hole 62 having a diameter of 0.3 to 0.5 μm. The
[0109]
Similar to the contact hole 32, the via hole 62 has a tapered shape whose diameter gradually decreases from the upper end toward the bottom. The taper angle θ cannot be generally defined depending on etching conditions or the like, but has an inclination of, for example, 5 to 15 degrees.
[0110]
(I) Next, the process shown in FIG. 4B will be described.
[0111]
(Degassing treatment)
First, heat treatment including a degassing step will be described.
[0112]
1.5x10 in the lamp chamber^-FourLamp heating (heat treatment D) is performed at a base pressure of Pa or lower and a temperature of 150 to 250 ° C. for 30 to 60 seconds. Then 1 x 10 in another chamber^-1~ 15 × 10^-1Degassing is performed by introducing argon gas at a pressure of Pa and performing a heat treatment (degassing step; heat treatment E) for 30 to 120 seconds at a temperature of 300 to 500 ° C.
[0113]
In this step, first, in the heat treatment D, moisture or the like adhering to the wafer can be removed mainly by heat-treating the entire wafer including the back surface and side surfaces of the wafer.
[0114]
Further, in the heat treatment E, gasification components (H, H in the second interlayer insulating film I2 are mainly used.₂O) can be removed. As a result, generation of gasification components from the second interlayer insulating film I2 can be prevented when forming the wetting layer and the aluminum film in the next step.
[0115]
In the present embodiment, the wetting layer, for example, the Ti film has a gasification component (O, H, H of several tens of atomic percent).₂O, N) is dissolved, so that the gasification component in the second interlayer insulating film I2 is removed before the formation of this film, so that the aluminum film is favorably formed in the via hole. Above, it is extremely effective. If the gasification component in the second interlayer insulating film I2 below the wetting layer is not sufficiently removed, the second interlayer insulating film I2 is formed at the temperature at which the wetting layer is formed (usually 300 ° C. or more). The gasified components therein are released and this gas is taken into the wetting layer. Furthermore, since this gas is detached from the wetting layer and formed at the interface between the wetting layer and the aluminum film when the aluminum film is formed, the adhesion and fluidity of the aluminum film are adversely affected.
[0116]
(Wetting layer deposition)
A titanium film having a thickness of 20 to 70 nm is formed as a film constituting the wetting layer 63 by sputtering. The sputtering temperature is selected in the range of 200 to 450 ° C. depending on the film thickness.
[0117]
(Degassing treatment before aluminum film formation and wafer cooling)
First, before cooling the wafer, in the lamp chamber, 1.5 × 10^-FourA heat treatment (heat treatment F) is performed at a base pressure of Pa or lower and a temperature of 150 to 250 ° C. for 30 to 60 seconds to remove substances such as water attached to the substrate. Thereafter, before the aluminum film is formed, the substrate temperature is lowered to 100 ° C. or lower, preferably from room temperature to 50 ° C. This cooling step is important for lowering the substrate temperature raised by the heat treatment F. For example, a wafer is placed on a stage having a water cooling function to lower the wafer temperature to a predetermined temperature.
[0118]
By cooling the wafer in this way, when the first aluminum film is formed, the amount of gas released from the second interlayer insulating film I2 and the wetting layer 63 and the entire wafer surface can be minimized. it can. As a result, it is possible to prevent the influence of gas that is adsorbed on the interface between the wetting layer 63 and the first aluminum film 64 and is harmful to coverage and adhesion.
[0119]
(Deposition of aluminum film)
First, at a temperature of 200 ° C. or less, more preferably 30 to 100 ° C., aluminum containing 0.2 to 1.0% by weight of copper is formed at a high speed by sputtering with a film thickness of 150 to 300 nm. An aluminum film 64 is formed. Subsequently, the substrate temperature is heated to 420 to 460 ° C. in the same chamber, and similarly, aluminum containing copper is formed at a low speed by sputtering to form a second aluminum film 65 having a thickness of 300 to 600 nm. .
[0120]
As the sputtering apparatus, the same apparatus as that shown in FIG. 5 can be used. The configuration of the sputtering apparatus, wafer temperature control, and sputtering power are the same as in the case of the first metal wiring layer 40, and thus detailed description thereof is omitted.
[0121]
By continuously forming the first aluminum film 64 and the second aluminum film 65 in the same chamber, the temperature and power can be strictly controlled, and the aluminum film is stable at a lower temperature than in the prior art. Can be formed efficiently.
[0122]
The film thickness of the first aluminum film 64 is such that a continuous layer can be formed with good step coverage, and the gasification component from the wetting layer 63 and the second interlayer insulating film I2 below the aluminum film 64 An appropriate range is selected in consideration of the ability to suppress the release of selenium, for example, 100 to 300 nm is desirable. The second aluminum film 65 is determined by the size of the via hole 62 and the aspect ratio thereof. For example, in order to fill a hole having an aspect ratio of about 3 and 0.5 μm or less, a film of 300 to 800 nm is used. Thickness is necessary.
[0123]
(Formation of antireflection film)
Further, TiN is deposited by sputtering in another sputtering chamber, whereby an antireflection film 66 having a film thickness of 30 to 80 nm is formed. Then Cl₂And BCl_ThreeThe deposited layer composed of the wetting layer 63, the first aluminum film 64, the second aluminum film 65, and the antireflection film 66 is selectively etched with an anisotropic dry etcher mainly composed of a second gas. The metal wiring layer 60 is patterned.
[0124]
In the metal wiring layer 60 thus formed, aluminum is formed with good step coverage without generating voids in a via hole having an aspect ratio of 0.5 to 3 and a diameter of 0.2 to 0.8 μm. It was confirmed to be embedded.
[0125]
Thereafter, as required, third, fourth,... Multilayer wiring regions can be formed in the same manner as the second wiring region L2.
[0126]
In the present embodiment, the reason why the first and second interlayer insulating films I1 and I2 have excellent flatness is considered as follows.
[0127]
(A) The first silicon oxide film 22 and the fifth silicon oxide film 72 formed in the steps shown in FIGS. 1B and 3A are formed by a reaction between a silicon compound and hydrogen peroxide. Since the reaction product containing silanol has high fluidity, the irregularities on the wafer surface are highly planarized when these films are formed.
[0128]
(B) Each silicon oxide film constituting the first and second interlayer insulating films I1 and I2, particularly the first, second and third silicon oxide films 22, 24 and 26, and the fifth, sixth and seventh Since the silicon oxide films 72, 74, and 76 have the same polishing rate in CMP, good flatness can be obtained even when different silicon oxide films partially coexist on the surface.
[0129]
In the present embodiment, the reason why the first and second aluminum films 34 and 35 and the first and second aluminum films 64 and 65 are satisfactorily embedded in the contact hole 32 and the via hole 62 is as follows. The following can be considered.
[0130]
(A) By performing a degassing step, the water and nitrogen contained in each of the interlayer insulating films I1 and I2 are gasified and sufficiently released, and then the first aluminum films 34 and 64 and the second aluminum are subsequently formed. In the formation of the films 35 and 65, by preventing the generation of gas from the interlayer insulating films I1 and I2, the barrier layer 33, or the wetting layer 63, the barrier layer 33, the first aluminum film 34, and the wetting layer 63 and the first It was possible to improve the adhesion with the aluminum film 64 and to form a film with good step coverage.
[0131]
(B) In the formation of the first aluminum films 34 and 64, the moisture contained in the interlayer insulating films I1 and I2, the barrier layer 33, and the wetting layer 63 is set by setting the substrate temperature to a relatively low temperature of 200 ° C. or less. In addition to the effect of the degassing step, the adhesion of the first aluminum films 34 and 64 is improved by preventing the release of nitrogen and nitrogen.
[0132]
(C) Further, since the first aluminum films 34 and 64 themselves serve to suppress the generation of gas from the lower layer when the substrate temperature rises, the following second aluminum films 35 and 65 are formed. Can be performed at a relatively high temperature, and the flow diffusion of the second aluminum film can be performed satisfactorily.
[0133]
With the above method, a semiconductor device according to the present invention (see FIG. 4B) can be formed. This semiconductor device has a silicon substrate 11 including at least a MOS element, and a first wiring region L1 formed on the silicon substrate 11.
[0134]
The first wiring region L1 includes a fourth silicon oxide film 20 serving as a base layer, a first silicon oxide film 22 formed by a polycondensation reaction between a silicon compound and hydrogen peroxide, and the first silicon oxide film. A second silicon oxide film 24 formed on the film 22 and containing impurities such as phosphorus, and a third silicon oxide film formed on the second silicon oxide film 24 and planarized by CMP. A first interlayer insulating film I1 made of 26, a contact hole 32 formed in the interlayer insulating film I1, a barrier layer 33 formed on the surface of the interlayer insulating film I1 and the contact hole 32, and the barrier layer 33 Aluminum films 34 and 35 made of aluminum or an alloy containing aluminum as a main component are formed. The aluminum film 34 is connected to the titanium silicide layer 19 through the barrier layer 33.
[0135]
The second wiring region L2 formed on the first wiring region L1 includes an eighth silicon oxide film 70 serving as a base layer, and a fifth condensation region formed by a polycondensation reaction between a silicon compound and hydrogen peroxide. Formed on the silicon oxide film 72, the fifth silicon oxide film 72, formed on the sixth silicon oxide film 74 containing impurities such as phosphorus, and the sixth silicon oxide film 74; The second interlayer insulating film I2 made of the seventh silicon oxide film 76 planarized by the above, the via hole 62 formed in the interlayer insulating film I2, the wetting formed on the surface of the interlayer insulating film I2 and the via hole 62 Layer 63 and aluminum films 64 and 65 made of aluminum or an alloy containing aluminum as a main component formed on the wetting layer 63. That.
[0136]
As described above, according to the present embodiment, a silicon oxide film containing silanol, which is obtained by a gas phase reaction between a silicon compound and hydrogen peroxide, is formed, and further planarized by CMP on the uppermost layer. By forming the film, an interlayer insulating film having extremely good flatness can be formed. In particular, since the first interlayer insulating film can be formed at a considerably lower temperature than the conventional BPSG film, the characteristics can be improved in terms of punch-through and junction leakage. And a contact structure with high reliability can be achieved, and the manufacturing process is also advantageous. In addition, since the interlayer insulating film has a high level of flatness, the process margin including the processing of the wiring layer can be increased, and the quality and yield can be improved.
[0137]
Furthermore, in the present embodiment, at least a degassing step and a cooling step are included before the sputtering of the aluminum film, and more preferably, by continuously forming the aluminum film in the same chamber, the thickness is reduced to about 0.2 μm. Contact holes and via holes can be filled only with aluminum or an aluminum alloy, improving reliability and yield. In addition, it was confirmed that there is no segregation of copper or the like in the aluminum film constituting the contact portion or abnormal growth of crystal grains, and that the reliability including migration is good.
[0138]
(Other embodiments)
The present invention is not limited to the above embodiment, and a part thereof can be replaced by the following means.
[0139]
(A) In the above embodiment, dinitrogen monoxide is used as the oxygen-containing compound when the second silicon oxide film 24 is formed by plasma CVD, but ozone can be used instead. Then, it is desirable to expose the wafer to an ozone atmosphere before forming the second silicon oxide film 24.
[0140]
For example, using the belt furnace shown in FIG. 8, the wafer W is placed on the transport belt 80 heated to 400 to 500 ° C. by the heater 82 and moved at a predetermined speed. At this time, ozone is supplied from the first gas head 86a, and the wafer W is passed through the ozone atmosphere of 2 to 8% by weight over 5 minutes. Next, ozone, TEOS, and TMP (P (OCH) are supplied from the second and third gas heads 86b and 86c._Three)_Three) Is supplied at substantially normal pressure, and a PSG film (second silicon oxide film) 24 having a phosphorus concentration of 3 to 6% by weight is formed to a thickness of 100 to 600 nm. In FIG. 8, reference numeral 84 denotes a cover.
[0141]
Thus, by using ozone instead of dinitrogen monoxide, a silicon oxide film made of TEOS can be formed by atmospheric pressure CVD. Further, by using a belt furnace, film formation can be performed continuously and efficiently.
[0142]
Further, by exposing the wafer W in an ozone atmosphere, the first silicon oxide film 22 has sufficiently low moisture absorption and moisture due to thermal desorption spectrum (TDS) and infrared spectroscopy (FTIR). As in the case of using dinitrogen monoxide, it was confirmed that the flatness of the interlayer insulating film I1 and the characteristics of the MOS transistor were good, and no crack was generated in the first silicon oxide film 22.
[0143]
(B) Although the silicon oxide film using TEOS by plasma CVD is used as the fourth silicon oxide film 20 in the embodiment, another silicon oxide film may be used instead. For example, such a fourth silicon oxide film may be a film formed by a low pressure thermal CVD method using monosilane and dinitrogen monoxide. This silicon oxide film is formed faithfully to the surface shape of the underlying silicon substrate, and not only has good coverage, but also has a high passivation function because it is dense. The silicon oxide film 22 is not easily cracked. Further, since the thermal CVD method is used, there is an advantage that there is no plasma damage.
[0144]
However, the film formation by this method requires the wafer temperature to be set to about 750 to 800 ° C., and therefore cannot be used when a film that is easily oxidized such as titanium silicide is used as the salicide structure. It is necessary to use molybdenum silicide.
[0145]
(C) In the above embodiment, the first interlayer insulating film I1 is composed of four layers of silicon oxide film, but the present invention is not limited to this, and another silicon oxide film may be added. For example, a 100-300 nm thick PSG film (phosphorus concentration: 1-6 wt%) formed by plasma CVD between the fourth silicon oxide film 20 and the first silicon oxide film 22 is used. It may be formed. By inserting this PSG film, it was confirmed that the gettering function of mobile ions was further improved, and the threshold characteristics of the transistor and fluctuations in quiescent current were reduced.
[0146]
In the above embodiment, the semiconductor device including the two-layer wiring region has been described. However, the present invention can be applied to a semiconductor device including three or more wiring regions, and includes an N-channel MOS element. The present invention can be applied not only to a semiconductor device but also to a semiconductor device including various elements such as a P-channel type or a CMOS type element.
[0147]
[Brief description of the drawings]
FIGS. 1A, 1B, and 1C are cross-sectional views schematically showing an example of a method for manufacturing a semiconductor device of the present invention in the order of steps.
2A and 2B are cross-sectional views schematically showing an example of a method for manufacturing a semiconductor device performed following the step shown in FIG.
FIGS. 3A and 3B are cross-sectional views schematically showing an example of a method of manufacturing a semiconductor device performed following the step shown in FIG.
4A and 4B are cross-sectional views schematically showing an example of a method of manufacturing a semiconductor device performed following the step shown in FIG. 3 in the order of steps.
FIG. 5 is a diagram schematically showing an example of a sputtering apparatus used in an embodiment according to the present invention.
6 is a diagram showing the relationship between time and substrate temperature when the substrate temperature is controlled using the sputtering apparatus shown in FIG.
7A to 7C are cross-sectional views showing an example of a conventional method for manufacturing a semiconductor device.
FIG. 8 is a diagram schematically showing a belt furnace used for manufacturing a semiconductor device.
[Explanation of symbols]
11 Silicon substrate
12 Field insulating film
13 Gate oxide film
14 Gate electrode
15 Low concentration impurity layer
16 High concentration impurity layer
17 Side wall spacer
18 Silicon oxide film
19 Titanium silicide layer
20 Fourth silicon oxide film
22 First silicon oxide film
24 Second silicon oxide film
26 Third silicon oxide film
32 Contact hole
33 Barrier layer
34 First aluminum film
35 Second aluminum film
62 Beer Hall
63 Wetting layer
64 First aluminum film
65 Second aluminum film
70 Eighth silicon oxide film
72 Fifth silicon oxide film
74 Sixth silicon oxide film
76 Seventh silicon oxide film
I1, I2 interlayer insulation film
L1, L2 wiring area

Claims (11)

Forming an interlayer insulating film on a semiconductor substrate including an element; forming a through hole in the interlayer insulating film; forming a barrier layer on a surface of the interlayer insulating film and the through hole; and the barrier layer Forming a conductive film on the surface of the substrate, and forming the interlayer insulating film,
(A) forming a first silicon oxide film by reacting a silicon compound and hydrogen peroxide by chemical vapor deposition;
(B) A plasma chemical vapor deposition method using a silicon compound, at least one of oxygen and a compound containing oxygen, and a compound containing phosphorus as an impurity under conditions of a temperature of 300 to 450 ° C. and a frequency of 200 to 600 kHz. Reacting to form a second silicon oxide film containing phosphorus in a proportion of 2 to 6% by weight;
(C) performing an annealing process at a temperature of 600 to 850 ° C .;
(D) reacting at least one of a silicon compound and a compound containing oxygen and oxygen with a chemical vapor deposition method to form a third silicon oxide film; and (e) the third silicon oxide film. And flattening by chemical mechanical polishing,
The step (b) includes a step of forming a porous second silicon oxide film from which the gas component generated from the first silicon oxide film in the step (c) can be released,
At least the steps (a) to (e) are sequentially performed. A method for manufacturing a semiconductor device, comprising: In claim 1,
The method for manufacturing a semiconductor device, wherein the oxygen-containing compound used in the step (b) is dinitrogen monoxide. Forming an interlayer insulating film on a semiconductor substrate including an element; forming a through hole in the interlayer insulating film; forming a barrier layer on a surface of the interlayer insulating film and the through hole; and the barrier layer Forming a conductive film on the surface of the substrate, and forming the interlayer insulating film,
(A) forming a first silicon oxide film by reacting a silicon compound and hydrogen peroxide by chemical vapor deposition;
(B) A silicon compound, ozone, and a compound containing phosphorus as an impurity are reacted by a normal pressure chemical vapor deposition method at a temperature of 400 to 500 ° C., and phosphorus is added at a ratio of 3 to 6% by weight. Forming a second silicon oxide film including:
(C) performing an annealing process at a temperature of 600 to 850 ° C .;
(D) reacting at least one of a silicon compound and a compound containing oxygen and oxygen with a chemical vapor deposition method to form a third silicon oxide film; and (e) the third silicon oxide film. And flattening by chemical mechanical polishing,
The step (b) includes a step of forming a porous second silicon oxide film from which the gas component generated from the first silicon oxide film in the step (c) can be released,
At least the steps (a) to (e) are sequentially performed. A method for manufacturing a semiconductor device, comprising: In claim 3,
A method of manufacturing a semiconductor device, wherein the first silicon oxide film is exposed to an ozone atmosphere before forming the second silicon oxide film in the step (b). In any one of Claim 1 thru | or 4,
The silicon compound used in the step (a) is at least one selected from an inorganic silane compound containing monosilane, disilane, SiH ₂ Cl ₂ and SiF ₄ and an organic silane compound containing tripropylsilane and tetraethoxysilane. A method of manufacturing a semiconductor device. In any one of Claims 1 thru | or 5,
In the step (a), the silicon compound is an inorganic silane compound, and the semiconductor device is manufactured by a low pressure chemical vapor deposition method under a temperature condition of 0 to 20 ° C. In any one of Claims 1 thru | or 5,
In the step (a), the silicon compound is an organosilane compound, and the semiconductor device is manufactured by a low pressure chemical vapor deposition method under a temperature condition of 100 to 150 ° C. In any one of Claims 1 thru | or 7,
Before the step (a), a semiconductor device is manufactured in which at least one of a silicon compound and a compound containing oxygen and oxygen is reacted by a chemical vapor deposition method to form a fourth silicon oxide film serving as a base layer. Method. In any one of Claims 1 thru | or 8,
The method of manufacturing a semiconductor device, wherein the annealing process in the step (c) is performed by continuously or intermittently increasing the temperature. In any one of Claims 1 thru | or 9,
The through hole is a method for manufacturing a semiconductor device, wherein the diameter of the through hole gradually decreases from the upper end to the bottom. In any one of Claims 1 thru | or 10,
The step of forming a conductive film on the surface of the barrier layer includes the step of forming a first aluminum film made of aluminum or an alloy containing aluminum as a main component at a temperature of 200 ° C. or lower.
Forming a second aluminum film made of aluminum or an alloy containing aluminum as a main component on the first aluminum film at a temperature of 300 ° C. or higher. .

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