JPH1174351A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device comprising an interlayer insulating film which can be formed at a low temperature in comparison with a conventional interlayer insulating film using a BPSG film, is excellent in flatness and enables the formation of a highly reliable contact structure on a semiconductor substrate, and a method of manufacturing the device. SOLUTION: A process of forming an interlayer insulating film 11 comprises a process wherein a hydrogen-containing silicon compound and hydrogen peroxide are reacted with each other by a chemical vapor deposition method to form a first silicon oxide film 22, a process wherein at least one kind of the compound or the element among a silicon compound, oxygen and an oxygen-containing compound and an impurities-containing compound are reacted with each other by the chemical vapor deposition method to form a second porous silicon oxide film 24, a process wherein an annealing treatment is performed at a temperature of 600 to 850 deg.C and the first and second silicon oxide films are highly refined, a process wherein at least one kind of the compound or the element among a silicon compound, oxygen and an oxygen- containing compound and an impurities-containing compound are reacted with each other by the chemical vapor deposition method to form a third silicon oxide film 26, and a process of flattening the film 26 by a chemical and mechanical polishing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device which can be miniaturized to half a micron or less and has an interlayer insulating film and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a semiconductor device such as an LSI, with the miniaturization, high density, and multi-layering of elements, it is important to lower the film forming temperature of an interlayer insulating film, to flatten it, and to form a metal wiring. It has become a challenge.

An interlayer insulating film is formed, for example, by first growing a silicon oxide film at low temperature by a chemical vapor deposition method on a substrate on which an element is formed, and then forming a silane compound, oxygen or ozone, and phosphorus or boron. A gas containing impurities is caused to react in a gas phase to form a BPSG film with a thickness of about several hundred nm to 1 μm. Thereafter, the BPSG film is fluidized and flattened by so-called high-temperature flow of annealing at a high temperature in a nitrogen atmosphere. A through hole (contact hole) is formed in the interlayer insulating film thus formed, a barrier layer made of titanium or titanium nitride is formed, and then a metal wiring layer is formed.

[0004] The flattening of the interlayer insulating film using such a BPSG film is performed utilizing the high-temperature flow characteristics of the BPSG film. The higher the impurity concentration in the BPSG film and the higher the annealing temperature, the more the flattening proceeds. In order to obtain sufficient flatness and denseness of the BPSG film, the annealing temperature is required to be 850 ° C. or higher.

However, in order to prevent punch-through from occurring in a miniaturized MOS transistor, it is important to suppress excessive spread of the source and drain impurity layers due to annealing. It is desired to process with. Further, when a silicide layer such as titanium is formed on the surface of the source / drain impurity layers constituting the MOS transistor, the high-temperature annealing causes the region of the silicide layer to expand more than necessary, which is a factor of deteriorating the junction characteristics. ing. For these reasons,
There is a demand for the development of a technique for forming an interlayer insulating film at a low temperature.

In order to further flatten the interlayer insulating film, after annealing the BPSG film, a silicon oxide film is further laminated by about 1 to 2 μm by a chemical vapor deposition method.
Thereafter, a method of performing a flattening process by chemical mechanical polishing (CMP) is also being performed. However, in this method, when a part of the BPSG film is exposed by polishing, it is difficult to control the film thickness and the flatness because the polishing rates of the uppermost silicon oxide film and the BPSG film are different. Furthermore, if a through-hole is formed with the upper silicon oxide film remaining, it is difficult to form a well-shaped through-hole because the etching rates of the silicon oxide film and the BPSG film are different. Also, there is a problem that it is not possible to achieve good embedding of the conductive film into the through holes.

[0007] For example, in Japanese Patent Application Laid-Open No. 7-86284, in order to planarize an interlayer insulating film, FIG.
(C) are disclosed. In this technique, a first wiring layer 3 is formed on an insulating film 2 of a semiconductor substrate 1, and a first interlayer insulating film 4 is formed thereon. An SOG layer (spin-on-glass layer) 5 is applied thereon,
A step between the first wiring layers 3 is reduced, and a second interlayer insulating film 6 thicker than the first wiring layer 3 is formed thereon. Then, the surface of the second interlayer insulating film 6 is flattened by the CMP method (see FIG. 7A). Thereafter, a through hole 7 is formed in the second interlayer insulating film 6, the SOG layer 5, and the first interlayer insulating film 4 (see FIG. 7B), and a second metal wiring layer 8 is further formed thereon. Is formed (see FIG. 7C).
In this technique, the SOG layer 5 is formed on the second interlayer insulating film 6
By providing it in the lower layer, the formation of a concave groove in the interlayer insulating film is prevented.

However, the uppermost second interlayer insulating film 6
And the lower SOG layer 5 have different polishing rates,
In order to obtain good flatness, it is necessary to stop the polishing process in the second interlayer insulating film 6, which makes it difficult to control the polishing process and increases the thickness of the second interlayer insulating film 6. This is disadvantageous in terms of cost and throughput. Further, when forming the through hole 7, the etching rate and the amount of generated polymer are different between the second interlayer insulating film 6 and the SOG layer 5, and a step or constriction is formed on the side surface of the through hole 7. As a result, the adhesion of the barrier layer and the metal wiring layer 8 in the through hole 7 becomes poor, and it is particularly difficult to form wiring by embedding aluminum by sputtering.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a contact structure which can be formed at a lower temperature than conventional interlayer insulating films using a BPSG film, is excellent in flatness, and has high reliability. It is an object of the present invention to provide a semiconductor device including an interlayer insulating film on a semiconductor substrate and a method for manufacturing the same, which can form a semiconductor device.

[0010]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming an interlayer insulating film on a semiconductor substrate including an element; forming a through hole in the interlayer insulating film; The step of forming a barrier layer on the surface of a film and the through hole and the step of forming a conductive film on the surface of the barrier layer, and the step of forming the interlayer insulating film includes at least the following steps (a) to (a). e).

(A) a step of forming a first silicon oxide film by reacting a silicon compound with hydrogen peroxide by chemical vapor deposition, and (b) at least one of a silicon compound, oxygen and a compound containing oxygen. Forming a porous second silicon oxide film by reacting a compound containing impurities with a chemical vapor deposition method, and (c) 600-
Performing an annealing treatment at a temperature of 850 ° C., (d) reacting at least one of a silicon compound and oxygen and a compound containing oxygen by a chemical vapor deposition method to form a third silicon oxide film, and (E) the third
Flattening the silicon oxide film by chemical mechanical polishing.

According to this method of manufacturing a semiconductor device, in the step (a), the silicon compound and the hydrogen peroxide are reacted by the chemical vapor deposition method to form the first silicon oxide film, thereby achieving the flatness. Can be formed. That is, the first formed in this step (a)
Has a high fluidity by itself and has excellent self-planarization characteristics. The mechanism is that when a silicon compound is reacted with hydrogen peroxide by a chemical vapor deposition method, silanol is formed in the gas phase, and this silanol is deposited on the wafer surface to form a film with good fluidity. It is thought to be possible.

For example, when monosilane is used as a silicon compound, silanol is formed by a reaction represented by the following formulas (1) and (1) ′.

Formula (1) SiH ₄ + 2H ₂ O ₂ → Si (OH) ₄ + 2H ₂ Formula (1) ′ SiH ₄ + 3H ₂ O ₂ → Si (OH) ₄ + 2H ₂ O + H ₂ and formulas (1) and (1) The silanol formed in 1) ′ becomes a silicon oxide as water is eliminated by a polycondensation reaction represented by the following formula (2).

Formula (2) Si (OH) ₄ → SiO ₂ + 2H ₂ O Examples of the silicon compound include inorganic silane compounds such as monosilane, disilane, SiH ₂ Cl ₂ , SiF ₄ and CH ₃ SiH ₃ , and tripropyl. Examples thereof include organic silane compounds such as silane and tetraethoxysilane.

In the film forming step of the step (a), when the silicon compound is an inorganic silicon compound, 0 to
In the case where the silicon compound is an organic silicon compound at a temperature of 20 ° C., it is preferable to perform the low pressure chemical vapor deposition at a temperature of 100 to 150 ° C. In this film forming step, if the temperature is higher than the upper limit, the polycondensation reaction of the formula (2) proceeds too much, and
The fluidity of the silicon oxide film is low, and it is difficult to obtain good flatness. Further, when the temperature is lower than the lower limit, adsorption of decomposed moisture in the chamber and dew condensation outside the chamber occur, which makes it difficult to control the film forming apparatus.

The first silicon oxide film formed in the step (a) is desirably formed to a thickness that can sufficiently cover a step on the surface of the silicon substrate. The lower limit of the thickness of the first silicon oxide film depends on the height of the irregularities on the surface of the silicon substrate including the element.
0 to 1000 nm. If the thickness of the first silicon oxide film exceeds the upper limit, cracks may occur due to stress of the film itself.

In the step (b), a silicon compound, at least one of oxygen and a compound containing oxygen, and a compound containing impurities are reacted by a chemical vapor deposition method,
A porous second silicon oxide film is formed on the first silicon oxide film.

The second silicon oxide film not only functions as a cap layer but also is porous, and is capable of removing a gas component generated from the first silicon oxide film in the annealing process in the step (c). It can be released gradually. Further, in addition to being porous, the second silicon oxide film is doped with an impurity such as phosphorus or boron, preferably phosphorus, to thereby form a silicon oxide Si-O By weakening the intermolecular bonding force, the stress of the film can be relieved, so that a layer that is appropriately soft and hard to crack can be formed. Further, as an important role of the second silicon oxide film, there is a function as a getter for mobile ions in which impurities such as phosphorus contained in the silicon oxide film adversely affect the reliability characteristics of the device such as alkali ions. The concentration of the impurity contained in the second silicon oxide film is:
In consideration of the gettering function and the stress relaxation of the film, the content is preferably 1 to 6% by weight.

The second silicon oxide film has a thickness of 100 to
Since the first silicon oxide film has a compressive stress of 600 MPa, the first silicon oxide film has a function of preventing an increase in tensile stress and cracking when polycondensed. Further, the second silicon oxide film also has a function of preventing the first silicon oxide film from absorbing moisture.

Preferably, the step (b) is performed by a plasma chemical vapor deposition method using a high frequency of 1 MHz or less under a temperature condition of 300 to 450 ° C. By performing the film formation under these temperature conditions, the gas components are easily released at the initial stage of the annealing in the annealing in the step (c), and the reliability of the device is improved.

The compound containing oxygen used in the step (b) is preferably dinitrogen monoxide (N ₂ O). By using nitrous oxide as a reaction gas, nitrous oxide in a plasma state easily reacts with a hydrogen bond (-H) of a silicon compound constituting the first silicon oxide film, and thus the second silicon oxide film is used. Can promote the desorption of gasification components (hydrogen, water) from the first silicon oxide film during the film formation.

The step (b) may be performed by a normal pressure chemical vapor deposition method at a temperature of 300 to 550 ° C. instead of the plasma chemical vapor deposition method. In this case, the compound containing oxygen used in the step (b) is desirably ozone.

Further, it is preferable that the first silicon oxide film is exposed to an ozone atmosphere before the second silicon oxide film is formed in the step (b). Through this step, ozone is converted into a hydrogen bond (-H) and a hydroxyl group (-) of the silicon compound constituting the first silicon oxide film.
OH), which facilitates the elimination of hydrogen and water in the first silicon oxide film.

The thickness of the second silicon oxide film is preferably 1 in consideration of flatness and prevention of cracks.
00 nm or more.

In the step (c), the first and second silicon oxide films formed in the steps (a) and (b) are densified by annealing at a temperature of 600 to 850 ° C. , Insulation and moisture resistance are improved.

That is, regarding the first silicon oxide film, the polycondensation reaction according to the above-mentioned formula (2) is completed in the early stage of this annealing treatment, and water and hydrogen generated by this reaction are removed from the second silicon oxide film. The first silicon oxide film is released to the outside through the holes of the oxide film, and is formed densely in a state where gasification components are sufficiently removed. Further, the second silicon oxide film is changed from a porous to a dense film by the annealing treatment.

In this annealing process, the temperature is set to 600
By setting the temperature to not less than ° C., the first and second silicon oxide films can be made sufficiently dense and, for example, the impurities of the source and drain diffusion layers constituting the MOS element can be sufficiently activated. . By setting the annealing temperature to 850 ° C. or lower, the interlayer insulating film can be flattened at a temperature lower than that required for the conventional BPSG film, and the first and second silicon oxide films can be formed. Can be sufficiently densified. On the other hand, if the annealing temperature is higher than 850 ° C., the source and drain diffusion layers expand more than necessary, causing problems such as punch-through, and it becomes difficult to miniaturize the device.

By forming a porous second silicon oxide film on the first silicon oxide film, the step (c)
In the annealing process at 600 to 850 ° C.
Even if there is a sudden change in temperature as in the case where the second silicon oxide film is directly placed under the temperature, the second silicon oxide film has a moderate softness and can absorb the stress of the first silicon oxide film.
Without generating cracks in the first silicon oxide film,
An annealing treatment can be performed.

The annealing treatment in the step (c) includes:
In order to more reliably prevent cracks from occurring in the first silicon oxide film, it is desirable that the first silicon oxide film be subjected to ramping annealing in which the temperature is increased continuously or intermittently.

Further, following the annealing treatment in the step (c), a third silicon oxide film is formed by a chemical vapor deposition method in a step (d), and the third silicon oxide film is further formed in a step (e). The silicon oxide film is planarized by chemical mechanical polishing.

In this flattening step, since the first, second and third silicon oxide films have almost the same polishing rate, even if a plurality of silicon oxide films are partially present on the final polished surface. An interlayer insulating film having good flatness can be obtained, and the amount of polishing can be easily controlled.

In the present invention, before the step (a), a silicon compound and at least one of oxygen and a compound containing oxygen are reacted by a chemical vapor deposition method to form a fourth silicon layer serving as a base layer. It is desirable to form an oxide film. The base layer has a passivation function that prevents moisture and unnecessary impurities from moving from the first silicon oxide film to the underlying silicon substrate, and a function of increasing the adhesion between the silicon substrate and the first silicon oxide film.

In the manufacturing method according to the present invention,
In the interlayer insulating film obtained by the above-described manufacturing method, a tapered through hole whose diameter gradually decreases from the upper end to the bottom is obtained. That is, the first silicon oxide film has a slightly lower etching rate than the second silicon oxide film, and the first silicon oxide film and the second silicon oxide film are in good contact with each other at the interface between them. As a result, a through hole having no step and an appropriate linear taper is formed. In such a tapered through hole, for example, an aluminum film or an aluminum alloy film can be embedded by sputtering, and a contact structure having excellent conductivity can be formed.

The through hole may be formed by anisotropic dry etching, or may be formed by combining isotropic wet etching and anisotropic dry etching so that the upper end of the through hole is further curved and tapered. May be formed.

In the through hole, first, 2
A first aluminum film made of aluminum or an alloy containing aluminum as a main component is formed at a temperature of 00 ° C. or less, and then a second aluminum film made of aluminum or an alloy containing aluminum as a main component is formed at a temperature of 300 ° C. or more.
It is desirable to form an aluminum film.

Examples of the alloy containing aluminum as a main component include binary or ternary alloys with at least one selected from copper, silicon, germanium, magnesium, cobalt, beryllium and the like. .

The semiconductor device formed by the above-described manufacturing method includes a semiconductor substrate including elements, an interlayer insulating film formed on the semiconductor substrate, a through hole formed in the interlayer insulating film, the interlayer insulating film, A barrier layer formed on the surface of the through hole, and a conductive film formed on the barrier layer, wherein the interlayer insulating film is formed by a polycondensation reaction between a silicon compound and hydrogen peroxide. A silicon oxide film, a second silicon oxide film formed on the first silicon oxide film and containing impurities,
And a third silicon oxide film formed on the second silicon oxide film and planarized by chemical mechanical polishing,
including.

[0039]

1 to 4 are schematic cross-sectional views illustrating a semiconductor device manufacturing method and a semiconductor device according to an embodiment of the present invention. 1 (A) to 1 (C) and FIGS. 2 (A) and 2 (B) show the first layer wiring region L1, and FIGS. 3 (A) and 3 (B) and FIGS. 4 (A) and 4 (B) A step for manufacturing a two-layer wiring region L2 will be described.

The following is an example of a method for manufacturing a semiconductor device.

(A) The step shown in FIG. 1A will be described.

(Formation of Element) First, a MOS element is formed on the silicon substrate 11 by a generally used method. Specifically, for example, a field insulating film 12 is formed on a silicon substrate 11 by selective oxidation, and a gate oxide film 13 is formed in an active region. After adjusting the threshold voltage by channel implantation, tungsten silicide is sputtered on the polysilicon film grown by thermally decomposing SiH ₄ , a silicon oxide film 18 is further laminated, and further etched into a predetermined pattern. Thereby, the gate electrode 14 is formed. At this time, a wiring layer 37 made of a polysilicon film and a tungsten silicide film is formed on the field insulating film 12 as needed.

Next, the low concentration impurity layer 15 in the source region or the drain region is implanted by ion-implanting phosphorus.
Is formed. Next, after a sidewall spacer 17 made of a silicon oxide film is formed on the side of the gate electrode 14,
Arsenic is ion-implanted, and impurities are activated by annealing using a halogen lamp, whereby the high-concentration impurity layer 16 in the source region or the drain region is formed.

Next, vapor-phase grown silicon of 100 nm or less
An oxide film is formed, and the film is made of HF and NH_FourWith a mixed aqueous solution of F
By selectively etching, a predetermined silicon base
Expose the plate area. Then, for example, 30 to 1 titanium
Sputter with a thickness of about 00 nm, and oxygen
650-750 ° C. in a nitrogen atmosphere controlled below
By performing instantaneous annealing for several seconds to about 60 seconds at a temperature
Titanium monosilicon on the open silicon substrate surface.
A titanium-rich titanium layer on the silicon oxide film 18.
A nitride (TiN) layer is formed. Then N
H_FourOH and H_TwoO _TwoWhen immersed in a mixed aqueous solution of
The tan nitride layer is etched away and becomes silicon-based.
A monosilicide layer of titanium remains only on the plate surface. Further
750-850 ° C. lamp annealing,
The monosilicide layer is converted to a disilicide,
The titanium silicide layer 1 is self-aligned with the surface of the pure layer 16.
9 is formed.

When the gate electrode 14 is formed only of polysilicon and is exposed by selective etching, a titanium salicide structure in which both the gate electrode and the source and drain regions are separated by a sidewall spacer.

The salicide structure may be made of tungsten silicide or molybdenum silicide instead of titanium silicide.

(B) Next, the step shown in FIG. 1B will be described.

(Formation of First Interlayer Insulating Film I1) The first interlayer insulating film I1 is composed of four silicon oxide films, that is, a fourth silicon oxide film 20, a first silicon oxide film in order from the bottom. 22, a second silicon oxide film 24 and a third silicon oxide film 26.

A. Formation of Fourth Silicon Oxide Film 20 First, tetraethoxysilane (TEOS) and oxygen are added for 30 minutes.
The fourth silicon oxide film 20 having a thickness of 100 to 200 nm is formed by reacting at 0 to 500 ° C. by a plasma chemical vapor deposition (CVD) method. This silicon oxide film 20 has no oxidation or casping of the silicide layer 19,
The film has a higher insulating property than the film grown from SiH _4, has a lower etching rate with respect to the aqueous solution of hydrogen fluoride, and becomes a dense film.

Here, the silicon oxide film 20 is formed directly on the titanium silicide layer 19, but if the film formation temperature is high at this time, the oxidizing gas and titanium silicide react at the initial stage of film formation to cause cracks and peeling. Since the temperature is easily generated, the processing temperature is preferably 600 ° C. or less, more preferably 250 to 4 ° C.
It is desirable to carry out at 00 ° C. After the silicon oxide film is formed on the titanium silicide layer 19 with a thickness of about 100 nm at the above-mentioned relatively low temperature, if the annealing or the gas phase oxidation treatment is performed by exposing to an oxidizing atmosphere other than water vapor, the temperature is reduced. There is no problem even if the temperature is raised to about 900 ° C.

B. Next, nitrogen gas is used as a carrier under a reduced pressure of preferably 2.5 × 10 ² Pa or less, more preferably 0.3 × 10 ^{2 to} 2.0 × 10 ² Pa. , SiH ₄ and H ₂ O ₂
Is reacted by the CVD method to form a first silicon oxide film 22. First silicon oxide film 22
Has a thickness at least larger than the step of the lower fourth silicon oxide film 20, that is, is formed with a film thickness sufficiently covering the step. Also, the first silicon oxide film 2
The upper limit of the film thickness of No. 2 is set to such an extent that cracks do not occur in the film. Specifically, the thickness of the first silicon oxide film 22 is desirably thicker than the lower step, and preferably 300 to 1000 n, in order to obtain better flatness.
m.

The temperature at which the first silicon oxide film 22 is formed is
The temperature at the time of film formation is preferably from 0 to 20 ° C., more preferably 0 to 20 ° C., because it is involved in the fluidity of the film at the time of film formation. Set to -10 ° C.

The flow rate of H ₂ O ₂ is not particularly limited, but is preferably at least twice the flow rate of SiH ₄ .
From the viewpoint of the uniformity of the film and the throughput, it is desirable to set the flow rate in the range of, for example, 100 to 1000 SCCM in gas conversion.

The first silicon oxide film 22 formed in this step is in a silanol polymer state, has good fluidity, and has high self-flattening characteristics. Further, the first silicon oxide film 22 has a high hygroscopicity because it contains many hydroxyl groups (-OH).

C. Formation of Second Silicon Oxide Film 24 Next, in the presence of SiH ₄ , PH ₃ and N ₂ O,
By reacting a gas at a temperature of 300 to 450 ° C. at a high frequency of 200 to 600 kHz by a plasma CVD method, a PSG film (second silicon oxide film) 24 having a thickness of 100 to 600 nm is formed. The second silicon oxide film 24 is formed continuously after the formation of the first silicon oxide film 22 in consideration of the high hygroscopicity of the first silicon oxide film 22, or Alternatively, it is desirable that the first silicon oxide film 22 is formed after being stored in an atmosphere containing no moisture.

In the second silicon oxide film 24, gasification components such as water and hydrogen contained in the first silicon oxide film 22 are easily and sufficiently removed by the annealing treatment performed later. In consideration of this, it is necessary to be porous. For this purpose, the second silicon oxide film 24 is formed, for example, at a temperature of preferably 450
The film is formed by a plasma CVD method at a temperature of 300C or lower, more preferably 300 to 400C, preferably 1 MHz or lower, and more preferably 200 to 600 kHz, and desirably contains impurities such as phosphorus. Second silicon oxide film 24
Since the second silicon oxide film 24 contains such impurities, the second silicon oxide film 24 becomes more porous and can not only relieve stress on the film but also have a gettering effect on alkali ions and the like. The concentration of such an impurity is set in consideration of the gettering effect, stress resistance, and the like. For example, when the impurity is phosphorus, it is desirable that the impurity be contained at a ratio of 2 to 6% by weight.

In the plasma CVD, the use of N ₂ O as a compound containing oxygen facilitates the desorption of hydrogen bonds in the first silicon oxide film 22. As a result, gasified components such as moisture and hydrogen contained in the first silicon oxide film 22 can be more reliably removed.

The thickness of the second silicon oxide film 24 is
The role of adjusting the thickness of the interlayer insulating film is required, N ₂
In consideration of the function of O plasma for desorbing hydrogen bonds, it is preferably 100 nm or more, more preferably 100 to 60 nm.
It is set to 0 nm.

D. Annealing Next, annealing is performed at a temperature of 600 to 850 ° C. in a nitrogen atmosphere. By this annealing process, the first silicon oxide film 22 and the second silicon oxide film 24 are densified, and have good insulating properties and water resistance. That is, by setting the annealing temperature to 600 ° C. or higher, the condensation polymerization reaction of silanol in the first silicon oxide film 22 is almost completely performed, and the water and hydrogen contained in the film are sufficiently released. A dense film can be formed. Further, by setting the annealing temperature to 850 ° C. or less, it is possible to achieve the miniaturization of the element without giving an adverse effect such as punch-through or junction leak to the diffusion layer of the source region or the drain region constituting the MOS transistor. Can be.

In the annealing process, in order to reduce the influence of thermal strain on the first silicon oxide film 22, the temperature of the wafer is increased stepwise or continuously.
It is desirable to perform a ramping anneal. For example, after keeping the wafer at about 400 ° C., the annealing temperature (600
(850 ° C.), the second silicon oxide film 2
4 can be considerably reduced in impurity concentration. For example, in the case where the impurity is phosphorus, aside from the gettering effect of mobile ions, even if the phosphorus concentration is 2% by weight or less, the first
It is confirmed that no crack occurs in the silicon oxide film 22 of FIG.

E. Formation of Third Silicon Oxide Film 26 Next, a third silicon oxide film 26 having a thickness of 1000 to 1500 nm is formed by plasma CVD at 350 to 400 ° C. using TEOS and oxygen.

The TEOS-oxygen silicon oxide film formed by the plasma CVD method is almost the same as or slightly different from the first silicon oxide film 22 and the second silicon oxide film 24 which have been annealed at a high temperature, even when the annealing is not performed. It has a fast dry etching rate. This is a factor in obtaining a contact hole having a good shape without forming a constriction or a step on the side surface of the hole in forming a contact hole described later.

(C) Next, the step shown in FIG. 1C will be described.

(Smoothing by CMP) Next, the third
Silicon oxide film 26, and, if necessary, the second silicon oxide film 24 and the first silicon oxide film 22.
Is polished to a predetermined thickness by a CMP method, and is smoothed. The first silicon oxide film 22, the second silicon oxide film 24, and the third silicon oxide film 26
Since the polishing rates are almost the same, the second silicon oxide film 24 or the first silicon oxide film 22 is polished by polishing.
Even if a part of the surface is exposed, a flat surface can be obtained, and therefore, the amount of polishing can be easily controlled.

For example, according to the study of the present inventors, the polishing rate of each silicon oxide film was as follows.

First silicon oxide film (annealing temperature 800 ° C.); 250 nm / min. Second silicon oxide film (annealing temperature 800 ° C.); 250 nm / min. Third silicon oxide film (no anneal); 250 nm / min. (Annealing temperature 900 ° C.); 350 nm / min. (D) Next, the step shown in FIG. 2A will be described.

(Formation of Contact Hole) Next, CH
A silicon oxide film 20 constituting a first interlayer insulating film I1 by a reactive ion etcher using F ₃ and CF ₄ as main gases;
By selectively anisotropically etching 22, 24 and 26, contact holes 32 having a diameter of 0.2 to 0.5 μm are formed.

The contact hole 32 has a tapered shape in which the diameter decreases linearly from the upper end to the bottom. The angle θ of the taper cannot be specified unconditionally depending on etching conditions and the like, but has, for example, an inclination of 5 to 15 degrees. The reason that such a tapered through hole can be obtained is firstly that the silicon oxide films 20 and 2
2, 24 and 26 have basically the same etching rate, and further, the first silicon oxide film 22 has a slightly lower etching rate than the second silicon oxide film 24; This is because the interface between the silicon oxide films is extremely well adhered. In such a tapered contact hole 32, an excellent deposition of an aluminum film is possible as described later.

The dry etching rate of each silicon oxide film measured by the present inventors will be described below. Note that dry etching has a power of 800 W, an atmospheric pressure of 20 P
a, etchant gas; CF ₄ : CHF ₃ : He = 1:
The test was performed under the condition of 2: 9.

First silicon oxide film (annealing temperature 800 ° C.); 525 nm / min. Second silicon oxide film (annealing temperature 800 ° C.); 550 nm / min. Third silicon oxide film (no annealing); 565 nm / min. BPSG film (annealing temperature 900 ° C.); 750 nm / min. (E) Next, the step shown in FIG. 2B will be described.

(Degassing Treatment) First, the heat treatment including the degassing step will be described.

In a lamp chamber, a base pressure of 1.5 × 10 ⁻⁴ Pa or less, a temperature of 150 to 250 ° C. and a temperature of 30 to 60 ° C.
The lamp is heated for 2 seconds (heat treatment A). Then, argon gas is introduced into another chamber at a pressure of 1 × 10 ⁻¹ to 15 × 10 ⁻¹ Pa, and at a temperature of 150 to 550 ° C., 30 to 1 ° C.
Degassing is performed by performing a heat treatment (degassing step; heat treatment B) for 20 seconds.

In this step, first, in heat treatment A, the entire wafer, including the back surface and side surfaces of the wafer, is subjected to a heat treatment, whereby moisture and the like adhering to the wafer can be removed.

Further, in the heat treatment B, the first silicon oxide film 2 mainly forming the first interlayer insulating film I1 is formed.
2 can remove gasification components (H, H ₂ O). As a result, at the time of forming the barrier layer and the aluminum film in the next step, generation of gasification components from the first interlayer insulating film I1 can be prevented.

In the present embodiment, the barrier layer 33
Is composed of a multilayer film including a barrier film having a barrier function and a conductive film. The conductive film is formed between the barrier film and the impurity diffusion layer in order to increase the conductivity between the barrier film and the impurity diffusion layer formed on the silicon substrate, that is, the source region or the drain region. As the barrier film, a general substance, for example, titanium nitride or titanium tungsten can be preferably used. Also,
As the conductive film, a high melting point metal such as titanium, cobalt, or tungsten can be used. These titanium,
Cobalt and tungsten react with silicon constituting the substrate to form silicide.

Since a barrier layer, for example, a TiN film / Ti film forms a solid solution of several tens of atomic% of gasification components (O, H, H ₂ O, N), the first layer is formed before these films are formed. It is extremely effective to remove the gasification component in the interlayer insulating film I1 in order to form the aluminum film in the contact hole satisfactorily. First interlayer insulating film I below barrier layer
If the gasification component in the first interlayer insulating film I1 is not sufficiently removed, the gasification component in the first interlayer insulating film I1 is released at the temperature (normally 300 ° C. or higher) at the time of forming the barrier layer, Is taken into the barrier layer. Further, since this gas is separated from the barrier layer and comes out at the interface between the barrier layer and the aluminum film during the formation of the aluminum film, the gas adversely affects the adhesion and the fluidity of the aluminum film.

(Formation of Barrier Layer) A titanium film was formed as a conductive film for forming the barrier layer 33 by a sputtering method.
Next, a TiN film is formed in a thickness of 30 to 150 nm as a barrier film in another chamber. The temperature of the sputtering is 200 to 45 depending on the film thickness.
It is selected in the range of 0 ° C.

Next, 0.1 × 10 ^{2 to} 1.5 × 10 ² Pa
Exposure to oxygen plasma for 10 to 100 seconds at a pressure of 4
10-60 in nitrogen or hydrogen atmosphere at 50-700 ° C
By performing the annealing treatment for minutes, titanium oxide can be formed in an island shape in the barrier layer. It has been confirmed that the barrier property of the barrier layer can be improved by this treatment.

This annealing treatment can also be performed by a heat treatment at 400 to 800 ° C. in a lamp annealing furnace containing at least several hundred ppm to several percent of oxygen.
Similarly, the barrier properties of the barrier layer can be improved.

Although not shown, a wetting layer made of titanium, cobalt, silicon or the like may be formed on the surface of the barrier layer 33 for the purpose of improving the wettability to an aluminum film described later. By providing such a wetting layer, the fluidity of the first aluminum film can be increased. The thickness of the wetting layer may be usually several tens nm or more.

(Degassing Process and Cooling of Wafer Before Deposition of Aluminum Film) First, before cooling the wafer, a base pressure of 1.5 × 10 ⁻⁴ Pa or less, 150 to 250 A heat treatment (heat treatment C) is performed at a temperature of ° C. for 30 to 60 seconds to remove substances such as water attached to the substrate. Thereafter, before forming the aluminum film, the substrate temperature is set to 100 ° C. or lower, preferably room temperature to 50 ° C.
Lower the temperature. This cooling step is important for lowering the substrate temperature raised by the heat treatment C. For example, a wafer is placed on a stage having a water cooling function, and the wafer temperature is lowered to a predetermined temperature.

By cooling the wafer in this manner, when forming the first aluminum film, the amount of gas released from the first interlayer insulating film I1, the barrier layer 33, and the entire surface of the wafer is minimized. can do. As a result, it is possible to prevent the gas adsorbed at the interface between the barrier layer 33 and the first aluminum film 34 from being harmful to the coverage and adhesion.

(Formation of Aluminum Film) First, at 200 ° C.
Below, more preferably at a temperature of 30 to 100 ° C, 0.2
Aluminum containing 1.0% by weight of copper to a thickness of 150
A first aluminum film 34 is formed by sputtering at a high speed at 300 nm. Subsequently, the substrate was heated to 420 to 460 ° C. in the same chamber, and aluminum containing copper was similarly formed at a low speed by sputtering.
A second aluminum film 35 having a thickness of 300 to 600 nm is formed. Here, in forming the aluminum film,
“High speed” cannot be unconditionally defined by the film formation conditions or the design items of the device to be manufactured, but is approximately 10 nm.
Per second or more, and "low speed" means a sputtering speed of about 3 nm / second or less.

FIG. 5 shows an example of a sputtering apparatus for forming the first and second aluminum films 34 and 35. This sputtering apparatus has a target 51 serving as an electrode and an electrode 52 serving as a stage in a chamber 50, and a substrate (wafer) W to be processed is set on the electrode 52. A first gas supply path 53 is connected to the chamber 50, and a second gas supply path 54 is connected to the electrode 52. Gas supply paths 53, 5
4 supplies an argon gas. The temperature of the wafer W is controlled by the gas supplied from the second gas supply path 54. The chamber 50
The means for exhausting the gas inside is not shown.

FIG. 6 shows an example in which the substrate temperature is controlled by using such a sputtering apparatus. In FIG.
The horizontal axis indicates elapsed time, and the vertical axis indicates substrate (wafer) temperature. In FIG. 6, the line indicated by a represents the substrate temperature change when the temperature of the stage 52 of the sputtering apparatus is set to 350 ° C., and the line indicated by b represents the high-temperature argon through the second gas supply path 54. This shows a change in the substrate temperature when the temperature of the stage 52 is increased by supplying gas into the chamber.

For example, the temperature control of the substrate is performed as follows. First, the temperature of the stage 52 is set in advance to a temperature (350 to 500) for forming the second aluminum film.
° C). When the first aluminum film is formed, no gas is supplied from the second gas supply path 54, and the substrate temperature is controlled by heating by the stage 52 as shown in FIG.
Gradually rises as shown by the symbol a. When the second aluminum film is formed, the heated gas is supplied through the second gas supply path 54, so that the substrate temperature rises rapidly as shown by the symbol b in FIG. It is controlled to be constant at a predetermined temperature.

In the example shown in FIG.
The first aluminum film 34 is formed while the substrate temperature is set at 125 ° C. and the substrate temperature is set at 125 to 150 ° C., and immediately thereafter, the second aluminum film 35 is formed.

In forming an aluminum film, it is important to control the power applied to the sputtering apparatus as well as the film forming speed and the substrate temperature. In other words, although related to the film formation rate, the first aluminum film 34 is formed with a high power, the second aluminum film 35 is formed with a low power, and when the power is switched from a higher power to a lower power, the power is reduced. It is important not to set to zero. When the power is set to zero, an oxide film is formed on the surface of the first aluminum film even under reduced pressure, and the wettability of the second aluminum film to the first aluminum film is reduced, and the adhesion between the two is deteriorated. In other words, by constantly applying power, active aluminum can be continuously supplied to the surface of the aluminum film being formed, and the formation of an oxide film can be suppressed. The magnitude of the power depends on the sputtering apparatus and film forming conditions and cannot be specified unconditionally. For example, in the case of the temperature condition shown in FIG.
It is desirable that the low power be set between 300 W and 1 kW.

As described above, by continuously forming the first aluminum film 34 and the second aluminum film 35 in the same chamber, the temperature and the power can be strictly controlled, and the temperature and power can be controlled strictly. It is possible to efficiently form a low-temperature and stable aluminum film.

The thickness of the first aluminum film 34 is
Considering that a continuous layer can be formed with good step coverage and that the gasification component can be suppressed from being released from the barrier layer 33 below the aluminum film 34 and the first interlayer insulating film I1, etc. Although a suitable range is selected, for example, 200 to 400 nm is desirable.
The second aluminum film 35 is determined by the size of the contact hole and the aspect ratio thereof. For example, in order to fill a hole having an aspect ratio of about 3 and 0.5 μm or less, a film of 300 to 1000 nm is required. Thickness is required.

(Formation of Anti-Reflection Film) Further, in another sputtering chamber, TiN is deposited by sputtering to form an anti-reflection film 36 having a thickness of 30 to 80 nm. Thereafter, the deposited layer composed of the barrier layer 33, the first aluminum film 34, the second aluminum film 35, and the antireflection film 36 is selectively formed by an anisotropic dry etcher mainly containing Cl ₂ and BCl ₃ gas. Etch first
Of the metal wiring layer 40 is performed.

The metal wiring layer 40 formed as described above
Then, the aspect ratio is 0.5-3 and the aperture is 0.2-
It was confirmed that aluminum was buried in the 0.8 μm contact hole with good step coverage without generating voids.

(F) Next, the step shown in FIG. 3A will be described.

(Formation of Second Interlayer Insulating Film I2) The second interlayer insulating film I2 is basically formed of the first interlayer insulating film I1.
Has the same configuration as That is, the second interlayer insulating film I
Reference numeral 2 denotes a four-layered silicon oxide film, that is, an eighth silicon oxide film 70, a fifth silicon oxide film 72,
It comprises a sixth silicon oxide film 74 and a seventh silicon oxide film 76. These silicon oxide films 70, 72, 74 and 76 are formed in the same manner as the silicon oxide films 20, 22, 24 and 26 except for the annealing process. The main parts will be described below, but description of common items will be omitted.

A. Formation of Eighth Silicon Oxide Film 70 First, tetraethoxysilane (TEOS) and oxygen are mixed for 30 minutes.
By reacting at 0 to 500 ° C. by a plasma enhanced chemical vapor deposition (CVD) method, an eighth silicon oxide film 70 having a thickness of 50 to 200 nm is formed.

B. Formation of Fifth Silicon Oxide Film 72 Next, under a reduced pressure of preferably 2.5 × 10 ² Pa or less, more preferably 0.3 × 10 ² to 2 × 10 ² Pa,
Using nitrogen gas as a carrier, SiH ₄ and H ₂ O ₂
The fifth silicon oxide film 72 is formed by reacting at a temperature of ℃ 10 ° C. by a CVD method. Like the first silicon oxide film 22, the fifth silicon oxide film 72 has a thickness at least larger than the step of the lower eighth silicon oxide film 70, that is, sufficiently covers the step. It is formed with a film thickness. The upper limit of the thickness of the fifth silicon oxide film 72 is set to such an extent that cracks do not occur in the film. Specifically, the fifth silicon oxide film 72
Is preferably thicker than the step of the lower layer in order to obtain better flatness, preferably 500 to 1000.
Set to nm.

The film forming temperature of the fifth silicon oxide film 72 is
Preferably it is set to 0 to 20 ° C, more preferably to 0 to 10 ° C.

The fifth silicon oxide film 72 formed in this step has high fluidity and excellent flattening characteristics.

C. Formation of a silicon oxide film 74 of the sixth Then, in the presence of SiH4, PH ₃ and N ₂ O,
By reacting by a plasma CVD method at a temperature of 300 to 450 ° C. and a high frequency of 200 to 600 kHz,
A PSG film (sixth silicon oxide film) 74 having a thickness of 100 to 600 nm is formed.

Further, similarly to the second silicon oxide film 24, the sixth silicon oxide film 74 is formed by gasification components such as water contained in the fifth silicon oxide film 72 by an annealing process performed later. It is necessary to be porous (porous) in consideration of easy and sufficient desorption of the metal. For this purpose, the sixth silicon oxide film 74 is used.
Is a high-frequency plasma CV having a temperature of preferably 450 ° C. or lower, more preferably 300 to 400 ° C., preferably 1 MHz or lower, and more preferably 200 to 600 kHz.
It is desirable that the film be formed by the method D and contain impurities such as phosphorus. By including such impurities in the second silicon oxide film 74, the second silicon oxide film 7
No. 4 is in a more porous state and can reduce stress on the film. The concentration of such an impurity is set in consideration of stress resistance, gettering effect, and the like.
For example, when the impurity is phosphorus, it is desirable that the impurity be contained at a ratio of 1 to 6% by weight.

In plasma CVD, the use of N ₂ O as a compound containing oxygen promotes the desorption of hydrogen bonds in the fifth silicon oxide film 72. As a result, gasified components such as moisture contained in the fifth silicon oxide film 72 can be more reliably removed.

The thickness of the sixth silicon oxide film 74 is
Preferably 100 nm or more, more preferably 200 to 6
It is set to 00 nm.

D. Annealing treatment Next, annealing treatment is performed at a temperature of 350 to 450 ° C. By this annealing process, the fifth silicon oxide film 7
The second and sixth silicon oxide films 74 are densified and have good insulating properties and water resistance. That is, by setting the annealing temperature to 350 ° C. or higher, the condensation polymerization reaction of silanol in the fifth silicon oxide film 72 is almost completely performed, and the moisture contained in the film is sufficiently released, and A film can be formed. Also, if the annealing temperature is 4
By setting the temperature to 50 ° C. or lower, the aluminum film forming the first wiring layer 40 is not adversely affected.

E. Formation of Seventh Silicon Oxide Film 76 Next, a third silicon oxide film 76 having a thickness of 1000 to 1500 nm is formed by plasma CVD at 350 to 400 ° C. using TEOS and oxygen.

(G) Next, the step shown in FIG. 3B will be described.

(Smoothing by CMP) The seventh silicon oxide film 76 and, if necessary, the sixth silicon oxide film 74 and the fifth silicon oxide film 72 are
It is polished to a predetermined film thickness by a method and smoothed. By this smoothing process, the seventh silicon oxide film 74 is polished by polishing.
Alternatively, even if a part of the fifth silicon oxide film 72 is exposed on the surface, a flat surface can be obtained, so that the amount of polishing can be easily controlled.

(H) Next, the step shown in FIG. 4A will be described.

(Formation of Via Hole) The second interlayer insulating film I2 and the antireflection film 36 are selectively anisotropically etched with a reactive ion etcher using CHF ₃ and CF ₄ as main gases, so that the diameter is reduced. Via holes 62 of 0.3 to 0.5 μm are formed.

Like the contact hole 32, the via hole 62 has a tapered shape whose diameter gradually decreases from the upper end toward the bottom. Taper angle θ
Can not be specified unconditionally depending on etching conditions and the like, but has, for example, an inclination of 5 to 15 degrees.

(I) Next, the step shown in FIG. 4B will be described.

(Degassing Treatment) First, the heat treatment including the degassing step will be described.

In a lamp chamber, a base pressure of 1.5 × 10 ⁻⁴ Pa or less, a temperature of 150 to 250 ° C. and a temperature of 30 to 60 ° C.
The lamp is heated (heat treatment D) for 2 seconds. Then, in another chamber, argon gas is introduced at a pressure of 1 × 10 ⁻¹ to 15 × 10 ⁻¹ Pa, and at a temperature of 300 to 500 ° C., 30 to 1 ° C.
Degassing is performed by performing a heat treatment (degassing step; heat treatment E) for 20 seconds.

In this step, first, in the heat treatment D, the water and the like adhering to the wafer can be removed mainly by heating the entire wafer including the back and side surfaces of the wafer.

Further, in the heat treatment E, gasification components (H, H ₂ O) in the second interlayer insulating film I2 can be mainly removed. As a result, at the time of forming the wetting layer and the aluminum film in the next step, generation of gasification components from the second interlayer insulating film I2 can be prevented.

In the present embodiment, the wetting layer, for example, a Ti film is composed of several tens atomic% of gasification components (O, H,
Since H ₂ O, N) forms a solid solution, removing the gasification component in the second interlayer insulating film I2 before forming this film makes it possible to form an aluminum film in the via hole satisfactorily. It is extremely effective in performing Unless gasification components in the second interlayer insulating film I2 below the wetting layer are sufficiently removed, the temperature at the time of forming the wetting layer (usually 3
(00 ° C. or higher), gasification components in the second interlayer insulating film I2 are released, and this gas is taken into the wetting layer. Further, this gas is separated from the wetting layer and formed at the interface between the wetting layer and the aluminum film during the formation of the aluminum film, which adversely affects the adhesion and fluidity of the aluminum film.

(Formation of Wetting Layer) A titanium film having a thickness of 20 to 70 nm is formed as a film constituting the wetting layer 63 by a sputtering method. The temperature of the sputtering is selected in the range of 200 to 450 ° C. according to the film thickness.

(Degassing Process and Cooling of Wafer Before Deposition of Aluminum Film) First, before cooling the wafer, a base pressure of 1.5 × 10 ⁻⁴ Pa or less, 150 to 250 A heat treatment (heat treatment F) is performed at a temperature of ° C. for 30 to 60 seconds to remove substances such as water attached to the substrate. Thereafter, before forming the aluminum film, the substrate temperature is set to 100 ° C. or lower, preferably room temperature to 50 ° C.
Lower the temperature. This cooling step is important for lowering the substrate temperature raised by the heat treatment F. For example, a wafer is placed on a stage having a water cooling function and the wafer temperature is lowered to a predetermined temperature.

By cooling the wafer in this manner, when the first aluminum film is formed, the amount of gas released from the second interlayer insulating film I2, the wetting layer 63, and the entire surface of the wafer is minimized. can do. As a result, it is possible to prevent the influence of a gas harmful to the coverage and adhesion, which is adsorbed on the interface between the wetting layer 63 and the first aluminum film 64.

(Formation of Aluminum Film) First, at 200 ° C.
Below, more preferably at a temperature of 30 to 100 ° C, 0.2
Aluminum containing 1.0% by weight of copper to a thickness of 150
A first aluminum film 64 is formed at a high speed by sputtering at 300 nm. Subsequently, the substrate was heated to 420 to 460 ° C. in the same chamber, and aluminum containing copper was similarly formed at a low speed by sputtering.
A second aluminum film 65 having a thickness of 300 to 600 nm is formed.

As a sputtering apparatus, the same apparatus as shown in FIG. 5 can be used. Since the configuration of the sputtering apparatus, the temperature control of the wafer, and the power at the time of sputtering are the same as in the case of the first metal wiring layer 40,
Detailed description is omitted.

First aluminum film 6 in the same chamber
By continuously forming the fourth and second aluminum films 65, temperature and power can be strictly controlled, and a stable and low-temperature aluminum film can be efficiently formed. Become.

The film thickness of the first aluminum film 64 is
Considering that a continuous layer can be formed with good step coverage, and that the release of gasification components from the wetting layer 63 and the second interlayer insulating film I2 below the aluminum film 64 can be suppressed, Although a suitable range is selected, for example, 100 to 300 nm is desirable. The second aluminum film 65 is determined by the size of the via hole 62 and the aspect ratio thereof. For example, in order to fill a hole having an aspect ratio of about 3 and 0.5 μm or less, a film of 300 to 800 nm is required. Thickness is required.

(Formation of Antireflection Film) Further, in another sputtering chamber, TiN is deposited by sputtering to form an antireflection film 66 having a thickness of 30 to 80 nm. Thereafter, the deposited layer composed of the wetting layer 63, the first aluminum film 64, the second aluminum film 65, and the antireflection film 66 is selectively formed by an anisotropic dry etcher mainly containing Cl ₂ and BCl ₃ gases. The second metal wiring layer 60 is patterned by etching.

The thus formed metal wiring layer 60
Then, the aspect ratio is 0.5-3 and the aperture is 0.2-
It was confirmed that aluminum was buried in 0.8 μm via holes with good step coverage without generating voids.

Thereafter, if necessary, the second wiring region L2
, And the third, fourth,... Multilayer wiring regions can be formed.

In this embodiment, the reason why the first and second interlayer insulating films I1 and I2 have excellent flatness is considered as follows.

(A) The first silicon oxide film 22 and the fifth silicon oxide film 22 formed in the steps shown in FIGS.
The silicon oxide film 72 is formed by a reaction between a silicon compound and hydrogen peroxide, and a reaction product containing silanol has a high fluidity. Flattened.

(B) First and second interlayer insulating films I1,
Each silicon oxide film constituting I2, in particular, the first, second and third silicon oxide films 22, 24 and 26, and fifth, sixth and seventh silicon oxide films 72, 74 and 76
Has the same polishing rate in CMP, so that good flatness can be obtained even when different silicon oxide films partially coexist on the surface.

In this embodiment, the reason why first and second aluminum films 34 and 35 and first and second aluminum films 64 and 65 are satisfactorily embedded in contact hole 32 and via hole 62, respectively. The following can be considered.

(A) By performing a degassing step, water and nitrogen contained in each of the interlayer insulating films I1 and I2 are gasified and sufficiently released, so that the subsequent first aluminum films 34 and 64 and the second In the formation of the aluminum layers 35 and 65, by preventing generation of gas from the interlayer insulating films I1 and I2, the barrier layer 33 or the wetting layer 63, the barrier layer 33, the first aluminum film 34, and the wetting layer are prevented. That the adhesion between the first aluminum film 63 and the first aluminum film 64 is improved, and that good step coverage can be formed.

(B) In forming the first aluminum films 34 and 64, the substrate temperature is set at a relatively low temperature of 200 ° C. or less, so that the interlayer insulating films I1 and I2, the barrier layer 33 and the wetting layer 63 are formed. The first aluminum films 34 and 64 are improved in adhesion in addition to the effect of the degassing step so as not to release contained moisture and nitrogen.

(C) Further, the first aluminum film 3
4, 64 themselves serve to suppress the generation of gas from the lower layer when the substrate temperature rises, so that the next second aluminum films 35, 65 can be formed at a relatively high temperature. And that the flow and diffusion of the second aluminum film can be performed favorably.

By the above method, a semiconductor device according to the present invention (see FIG. 4B) can be formed. This semiconductor device has a silicon substrate 11 including at least a MOS element, and a first wiring region L1 formed on the silicon substrate 11.

The first wiring region L1 includes a fourth silicon oxide film 20 serving as a base layer, a first silicon oxide film 22 formed by a polycondensation reaction between a silicon compound and hydrogen peroxide, A second silicon oxide film 24 formed on the second silicon oxide film 22 and containing impurities such as phosphorus, and a third silicon oxide film 24 formed on the second silicon oxide film 24 and planarized by CMP. A first interlayer insulating film I1 made of a silicon oxide film 26, a contact hole 32 formed in the interlayer insulating film I1, a barrier layer 33 formed on the surface of the interlayer insulating film I1 and the contact hole 32, and the barrier Aluminum films 34 and 35 made of aluminum or an alloy containing aluminum as a main component are formed on layer 33. The aluminum film 34 is formed on the barrier layer 33.
Is connected to the titanium silicide layer 19 via the.

The second wiring region L2 formed on the first wiring region L1 was formed by an eighth silicon oxide film 70 serving as a base layer and a polycondensation reaction between a silicon compound and hydrogen peroxide. A fifth silicon oxide film 72, a sixth silicon oxide film 74 formed on the fifth silicon oxide film 72 and containing an impurity such as phosphorus, and formed on the sixth silicon oxide film 74; And a second silicon oxide film 76 made flat by CMP.
An interlayer insulating film I2, a via hole 62 formed in the interlayer insulating film I2, a wetting layer 63 formed on the surface of the interlayer insulating film I2 and the via hole 62, and aluminum formed on the wetting layer 63. Alternatively, it has aluminum films 64 and 65 made of an alloy containing aluminum as a main component.

As described above, according to the present embodiment, a silicon oxide film containing silanol, which is obtained by a gas phase reaction between a silicon compound and hydrogen peroxide, is formed, and the uppermost layer is planarized by CMP. By forming the silicon oxide film, an interlayer insulating film having extremely good flatness can be formed. In particular, since the first interlayer insulating film can be formed at a considerably lower temperature than the conventional BPSG film, characteristics such as punch-through and junction leakage can be improved, and therefore, the fineness of the element can be reduced. And a highly reliable contact structure can be achieved, and it is also advantageous in the manufacturing process. In addition, since the interlayer insulating film has a high degree of flatness, a process margin including processing of a wiring layer and the like can be increased, and quality and yield can be improved.

Furthermore, in the present embodiment, at least a degassing step and a cooling step are included before the aluminum film is sputtered, and more preferably, the aluminum film is continuously formed in the same chamber to obtain a 0.2 μm It is possible to fill contact holes and via holes to a certain extent only with aluminum or an aluminum alloy, thereby improving reliability and yield.
Further, it was confirmed that there was no segregation of copper or the like and abnormal growth of crystal grains in the aluminum film constituting the contact portion, and that the reliability including the migration was good.

(Other Embodiments) The present invention is not limited to the above embodiments, and some of them can be replaced by the following means.

(A) In the above embodiment, when the second silicon oxide film 24 is formed by plasma CVD,
Although nitrous oxide was used as the compound containing oxygen, ozone may be used instead. It is desirable that the wafer be exposed to an ozone atmosphere before the second silicon oxide film 24 is formed.

For example, using a belt furnace shown in FIG. 8, a wafer W is placed on a transfer belt 80 heated to 400 to 500 ° C. by a heater 82 and moved at a predetermined speed. At this time, ozone is supplied from the first gas head 86a, and the wafer W is passed through an ozone atmosphere of 2 to 8% by weight over 5 minutes or more. Next, ozone and TEO are supplied from the second and third gas heads 86b and 86c.
S and TMP (P (OCH ₃ ) ₃ ) are supplied at substantially normal pressure, and a PSG film (second silicon oxide film) 24 having a phosphorus concentration of 3 to 6% by weight is formed in a thickness of 100 to 600 nm. I do. In FIG. 8, reference numeral 84 denotes a cover.

By using ozone instead of dinitrogen monoxide, a silicon oxide film can be formed by TEOS by normal pressure CVD. Further, by using a belt furnace, film formation can be continuously and efficiently performed.

When the wafer W is exposed to an ozone atmosphere, the first silicon oxide film 22 is subjected to thermal desorption spectroscopy (TDS) and infrared spectroscopy (FTIR).
Are that the hygroscopicity and water content are sufficiently low, that the flatness of the interlayer insulating film I1 and the characteristics of the MOS transistor are good as in the case where dinitrogen monoxide is used as the reaction gas, and that the first silicon oxide film 22 It was confirmed that no cracks occurred.

(B) In the above embodiment, a silicon oxide film using TEOS by plasma CVD is used as the fourth silicon oxide film 20, but another silicon oxide film may be used instead. For example, such a fourth
The silicon oxide film may be a film formed by a low pressure thermal CVD method using monosilane and dinitrogen monoxide. This silicon oxide film is formed with a good shape following the surface shape of the underlying silicon substrate and has good coverage and high density, so that the passivation function is high. Cracks hardly occur in the silicon oxide film 22 of FIG. Further, since the thermal CVD method is used, there is an advantage that there is no plasma damage.

However, film formation by this method requires setting the wafer temperature at about 750 to 800 ° C.
It cannot be used when a film that is easily oxidized like titanium silicide is used as the salicide structure, and it is necessary to use tungsten silicide or molybdenum silicide.

(C) In the above embodiment, the first interlayer insulating film I1 is composed of four silicon oxide films, but is not limited to this, and another silicon oxide film may be added.
For example, a PSG film (phosphorus concentration; 100 to 300 nm) formed between the fourth silicon oxide film 20 and the first silicon oxide film 22 by a plasma CVD method.
(1 to 6% by weight). It was confirmed that the provision of the PSG film further improved the gettering function of mobile ions, and reduced the fluctuation of the threshold characteristics and the quiescent current of the transistor.

In the above embodiment, a semiconductor device including two-layered wiring regions has been described. However, the present invention can of course be applied to a semiconductor device including three or more-layered wiring regions.
Further, the present invention can be applied to not only a semiconductor device including an N-channel MOS device but also a semiconductor device including various devices such as a P-channel or CMOS device.

[0147]

[Brief description of the drawings]

FIGS. 1A, 1B and 1C are cross-sectional views schematically showing an example of a method for manufacturing a semiconductor device according to the present invention in the order of steps.

FIGS. 2A and 2B are cross-sectional views schematically illustrating an example of a method of manufacturing a semiconductor device performed after the step illustrated in FIG. 1 in the order of steps;

FIGS. 3A and 3B are cross-sectional views schematically showing an example of a method for manufacturing a semiconductor device performed after the step shown in FIG. 2 in the order of steps;

FIGS. 4A and 4B are cross-sectional views schematically illustrating an example of a method for manufacturing a semiconductor device performed after the step illustrated in FIG. 3 in the order of steps;

FIG. 5 is a diagram schematically illustrating an example of a sputtering apparatus used in an embodiment according to the present invention.

6 is a diagram showing the relationship between time and substrate temperature when the substrate temperature is controlled using the sputtering apparatus shown in FIG.

7A to 7C are cross-sectional views illustrating an example of a conventional method for manufacturing a semiconductor device.

FIG. 8 is a diagram schematically showing a belt furnace used for manufacturing a semiconductor device.

[Explanation of symbols]

 Reference Signs List 11 silicon substrate 12 field insulating film 13 gate oxide film 14 gate electrode 15 low-concentration impurity layer 16 high-concentration impurity layer 17 sidewall spacer 18 silicon oxide film 19 titanium silicide layer 20 fourth silicon oxide film 22 first silicon oxide film 24 Second silicon oxide film 26 Third silicon oxide film 32 Contact hole 33 Barrier layer 34 First aluminum film 35 Second aluminum film 62 Via hole 63 Wetting layer 64 First aluminum film 65 Second aluminum film 70 First 8 silicon oxide film 72 fifth silicon oxide film 74 sixth silicon oxide film 76 seventh silicon oxide film I1, I2 interlayer insulating film L1, L2 wiring region

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 21/90 PB (72) Inventor Kazumi Matsumoto 3-5-5 Yamato, Suwa-shi, Nagano Pref. Seiko Epson Corporation (72) Inventor Naohiro Moriya 3-5-5 Yamato, Suwa City, Nagano Prefecture Inside Seiko Epson Corporation

Claims (18)

[Claims] 1. A semiconductor substrate including an element, an interlayer insulating film formed on the semiconductor substrate, a through hole formed in the interlayer insulating film, a barrier formed on a surface of the interlayer insulating film and a surface of the through hole. A first silicon oxide film formed by a polycondensation reaction between a silicon compound and hydrogen peroxide, the first silicon A second silicon oxide film formed on the oxide film and containing impurities, and a third silicon oxide film formed on the second silicon oxide film and planarized by chemical mechanical polishing. Including semiconductor devices. 2. The semiconductor device according to claim 1, wherein the impurity contained in the second silicon oxide film is phosphorus. 3. The semiconductor device according to claim 1, wherein the through hole has a tapered shape in which a diameter gradually decreases from an upper end to a bottom. 4. The semiconductor device according to claim 1, wherein the conductive film formed in the through hole is made of aluminum or an alloy containing aluminum as a main component. 5. A step of forming an interlayer insulating film on a semiconductor substrate including an element, a step of forming a through hole in the interlayer insulating film, and a step of forming a barrier layer on the surface of the interlayer insulating film and the through hole. And a step of forming a conductive film on the surface of the barrier layer, wherein the step of forming the interlayer insulating film includes at least the following steps (a) to (e). (A) reacting a silicon compound with hydrogen peroxide by a chemical vapor deposition method to form a first silicon oxide film; (b) silicon compound, at least one of oxygen and a compound containing oxygen, and impurities Forming a porous second silicon oxide film by reacting a compound containing, by a chemical vapor deposition method, (c) performing an annealing treatment at a temperature of 600 to 850 ° C., (d) a silicon compound, and Reacting at least one of oxygen and a compound containing oxygen by a chemical vapor deposition method to form a third silicon oxide film; and (e) planarizing the third silicon oxide film by chemical mechanical polishing. Process. 6. The method according to claim 5, wherein the silicon compound used in the step (a) is monosilane, disilane, SiH ₂ Cl ₂ , SiF ₄ , or CH ₃ SiH.
_{3. A} method of manufacturing a semiconductor device which is at least one selected from inorganic silane compounds such as ₃ and organic silane compounds such as tripropyl silane and tetraethoxy silane. 7. The method according to claim 5, wherein the step (a) is performed by a low pressure chemical vapor deposition method under a temperature condition of 0 to 20 ° C., wherein the silicon compound is an inorganic silane compound. A method for manufacturing a semiconductor device. 8. The method according to claim 5, wherein the step (a) is performed by a reduced pressure chemical vapor deposition method under a temperature condition of 100 to 150 ° C., wherein the silicon compound is an organic silane compound. A method for manufacturing a semiconductor device. 9. The method for manufacturing a semiconductor device according to claim 5, wherein the step (b) is performed by a plasma enhanced chemical vapor deposition method under a temperature condition of 300 to 450 ° C. 10. The method according to claim 9, wherein the compound containing oxygen used in the step (b) is nitrous oxide. 11. The method of manufacturing a semiconductor device according to claim 5, wherein the step (b) is performed by atmospheric pressure chemical vapor deposition under a temperature condition of 300 to 550 ° C. 12. The method according to claim 11, wherein the compound containing oxygen used in the step (b) is ozone. 13. The semiconductor device according to claim 5, wherein the first silicon oxide film is exposed to an ozone atmosphere before forming the second silicon oxide film in the step (b). Production method. 14. The method according to claim 5, wherein at least one of a silicon compound and oxygen and a compound containing oxygen is reacted by a chemical vapor deposition method before the step (a). A method for manufacturing a semiconductor device in which a fourth silicon oxide film serving as a base layer is formed. 15. The method according to claim 5, wherein the annealing in the step (c) is performed by continuously or intermittently increasing the temperature. 16. The method for manufacturing a semiconductor device according to claim 5, wherein the through hole has a tapered shape in which a diameter gradually decreases from an upper end to a bottom. 17. The conductive film according to claim 5, wherein the conductive film forms a first aluminum film made of aluminum or an alloy containing aluminum as a main component at a temperature of 200 ° C. or lower. Forming a second aluminum film made of aluminum or an alloy containing aluminum at a temperature of 300 ° C. or more. 18. The method according to claim 5, wherein the impurity used in the step (b) is phosphorus.