JPH05218030A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve yield, long term reliability by flattening an interlayer insulating film of a semiconductor device having a multilayer interconnection structure through a buried conductive material formed by etching back in a through hole. CONSTITUTION:Desired amounts of first, second silicon oxide films 17, 18 plasma and thermally grown by using organic silane on a first metal interconnection 13 are etched back, spin-coated with first coating glass 22, then a desired amount is etched back, a third silicon oxide film 19 is then formed then spin-coated with second coating glass 23, then a desired amount is formed back, subsequently a fourth silicon oxide film 20 is formed, and then a through hole is opened. Further a tungsten film 16 vapor-grown on the entire surface is etched back to allow it to remain in the through hole, and then a second metal interconnection 14 is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a connection technique in a multi-layered wiring structure which is made finer than submicron, and has a flatness of an interlayer insulating film and a metal in a through hole portion This is aimed at improving the wire coverage.

[0002]

2. Description of the Related Art Generally, a semiconductor device uses multi-layered wiring from the viewpoint of multi-function and integration. For example, an impurity layer of a Si substrate, an impurity-doped PolySi or a silicide layer made of Al or an alloy thereof is used. The contact is taken out by the first metal wiring, and further, through the through hole formed in the interlayer insulating film such as a silicon oxide film, Al
Connection is made to a second metal wiring made of a metal such as an alloy. As miniaturization progresses and the through holes become half micron or less, it becomes difficult to keep the wiring material around the through holes due to an increase in the aspect ratio, and it is difficult to secure the electrical characteristics and reliability of the semiconductor device such as hole resistance and migration. Therefore, as an improvement measure, PolyS by the vapor phase method is used.
A method of filling a through hole with a conductive material such as a refractory metal such as i or W (tungsten) or its silicide has been proposed.

A conventional method for manufacturing such a semiconductor device is shown in FIG.
As will be described later, for example, a CMOS-LSI having a two-layer wiring structure using an Al alloy is a silicon oxide film using selective oxidation or vapor phase growth on a Si substrate 11 in which semiconductor elements such as transistors and resistors are formed. A first metal wiring 13 made of an Al alloy or the like is formed through the contact hole of the field insulating film 12 by. Next, as an interlayer insulating film, for example, SiH4 and O2 or N2O similar to Japanese Patent Publication No. 51-21753 is used.
A silicon oxide film 25 obtained by subjecting an oxidizing gas such as the above to plasma or thermal reaction to vapor-phase grow about 500 nm to 800 nm,
Further, from the necessity of flattening in the fine structure, the coated glass 21 in which silanol and P2 O5 are dissolved in alcohols is used.
Is spin-coated and annealed at a temperature that does not hinder the first metal wiring 13. At this time, the concentration of P2 O5 mixed in the coated glass 21 at a concentration of 1 to 5 mol% is for improving the stress relaxation and the crack resistance effect of the coated glass thin film.
Next, the coated glass 21 and the silicon oxide film 25 are removed with CF4.
, CHF3 or C2 F6 gas is used for dry etching to open a through hole, and then thin TiN or TiW is grown as an adhesion layer 15 by sputtering or a vapor phase method. Is grown over the entire surface to about 400 nm. Then, W16 is etched back by a dry etcher in which Ar and He are added to SF6 and Cl2 (FIG. 2A). At this time, if the film thickness of the vapor-grown W16 is simply etched back, the first metal wiring 1
W16 also remains as a residue 26 on a step such as the space of 3. If this residue 26 is not removed, the lateral direction of the second metal wiring formed thereon will be electrically short-circuited. Therefore, in consideration of the film thickness variation of W16 and the uniformity of the etcher, overetching is performed so as to eliminate the residue 26, and the adhesion layer 15 is also removed by dry etching. After that, a second metal wiring 14 of Al alloy is applied (FIG. 2B), a passivation film such as a plasma silicon nitride film is further vapor-deposited, and finally a bonding pad portion is taken out to take out an electrode to the outside. It has a hole.

[0004]

However, in the prior art, the silicon oxide film 25 vapor-deposited with SiH4 and an oxidizing gas is cusped when the space of the first metal wiring 13 becomes finer. And a void 27 is formed in a space of submicron or less, and it becomes a contamination trap. The space size of the LSI wiring is
Even if the minimum value is limited, the wide area is not limited. Therefore, since the aspect ratio becomes about 0.7 or more, even if the vapor-grown silicon oxide film 25 has good coverage, it is not selectively filled, and the space portion of the first metal wiring 13 has
Since a U-shaped groove corresponding to the wiring thickness is formed, a liquid pool of the coating glass 21 can be formed here, for example, 1.0 to 1.
In a specific space of 5 μm, the coated glass 21 is 500 n
It becomes thicker than m and cracks 28 occur. On the other hand, the space of the first metal wiring 13 is 1.6 to 2.0 μ.
In the area of about m, the amount of accumulated glass is reduced,
The surface is depressed and the flatness is poor. This means that when W16 completely grown by the vapor phase method is etched back and buried in the through hole, the W16 remains in the through hole, but the W residue 26 remains in the region where the surface flatness of the interlayer insulating film is poor. Will occur. If over-etching is performed to remove the residue 26, the flat portion W16 is removed this time, so that the etching rate may rapidly increase and it is difficult to control the end point. As a result, the surface of the W16 in the through hole is suddenly dropped, and the second metal wiring 14 is poorly distributed in the through hole region, which lowers the initial yield, increases the hole resistance, and causes disconnection due to electromigration. There are many sex problems, which have been a hindrance to stable supply in terms of practical use and mass production. These are not limited to the problem of through holes between the two-layer wirings using the Al alloy, but are not limited to the impurity layer or Po of the Si substrate.
The same problem occurs when the lead wiring is formed from a gate electrode containing lySi or silicide through an embedded conductive material formed in the contact hole by etching back with an Al alloy or the like. Furthermore, the second metal wiring 14
Has a structure in which it comes into contact with the coated glass that easily absorbs moisture, and phosphoric acid is formed by water and P2 O5 that have entered during the process.
There has been a problem that the metal wiring such as the 1-alloy is corroded, or hydrogen ions, OH ions, and moisture in this reaction process enter the field oxide film to change the field inversion withstand voltage for element isolation. In addition to this, a direct overcoating method or a thick coating method in which the viscosity is increased has been proposed irrespective of the inorganic or organic coating glass, but it is not practical due to many problems such as crack generation and heat resistance.

The present invention, however, solves the above-mentioned problems. The plasma silicon oxide film of organic silane and the coated glass are used to improve the void-freeness of the interlayer insulating film and the surface flatness, and to improve the metal content in the through hole. Improve the reliability and reliability of a fine semiconductor device that has a structure that secures the connection of wiring, measures against corrosion, and further improves the transistor characteristics, and in particular, makes a multilayer wiring through an embedded conductive material formed by etchback. This is intended to be achieved.

[0006]

A method of manufacturing a semiconductor device according to the present invention provides a semiconductor device having a multilayer wiring structure,
At least a step of forming a first metal wiring layer on a semiconductor substrate having a device surface formed on a desired surface, and a step of forming a first silicon oxide film by plasma vapor phase reaction of a gas containing organic silane and O2. A step of laminating a second silicon oxide film obtained by subjecting an organic silane and a gas containing O3 to a gas reaction in a hot gas phase, a step of etching back a predetermined thickness of the laminated insulating film, a step of laminating a first coated glass, A step of etching back a predetermined thickness of the coated glass, a step of laminating a third silicon oxide film, a step of laminating a second coated glass,
Etching back a predetermined thickness of the coated glass, fourth
And a step of forming a second metal wiring after opening a through hole.

In addition, according to the method of manufacturing a semiconductor device of the present invention, after the formation of the interlayer insulating film of the multi-layer wiring structure or the water washing treatment,
The coated glass is spin-coated after heat treatment or plasma treatment in an oxidizing atmosphere in an atmosphere containing 3.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic sectional view of a process for explaining one embodiment of a semiconductor device according to the present invention.
When applied to a half-micron Si gate CMOS-LSI having a two-layer wiring structure using an alloy, silicon oxidation by vapor oxidation or selective oxidation on a silicon substrate 11 on which semiconductor elements such as MOS transistors and resistors are formed. A contact hole is formed in the field insulating film 12 having the films laminated, and a barrier metal, an Al alloy containing 0.5% Cu, and TiN to be the antireflection film 24 are laminated by a spatter, and then Cl2 and BCl3 gas are added. The laminated film was selectively etched with the dry etcher used, and the total thickness was 7,000 Å
The metal wiring 13 was applied. This antireflection film 24 is made of Al
Conductive TiN was used to prevent halation in the photolithography process of the alloy itself and the through holes formed on the alloy. Next, as an interlayer insulating film, first, TEOS [Si (OC
2 H5) 4] and O2 are subjected to plasma vapor phase reaction at 380 ° C. and about 9 torr to form a first silicon oxide film 1 having a thickness of about 500 nm.
7 to O2 carrier for 60 to 100 tons of O3 and TEOS
The second silicon oxide film 1 is subjected to a reduced pressure thermal reaction at r and 380 ° C.
8 was laminated to 400 nm (FIG. 1 (a)). These silicon oxide films have almost no cusping as compared with the conventional one using SiH4. In particular, the first silicon oxide film 17 is dense and excellent in contamination resistance, and has a compressive stress (for example, a warp in a convex shape when grown on a Si wafer). 60%. Further, the second silicon oxide film 18 has a good covering power on the side wall of the step and the bottom of the groove of about 100%, but has a tensile stress and is dense and contains a large amount of OH groups and water. Then CH
About 4 with plasma etcher using F3, CF4 and Ar
Anisotropic etch back corresponding to 50 nm is performed, the flat portion of the second silicon oxide film 18 is entirely removed, and the first metal wiring 13 is removed.
Leave as a side wall in the space. Subsequently, the first coated glass 22 was spin-coated and then annealed for 30 minutes in an N 2 atmosphere at about 450 ° C., the flat portion on the region of the first metal wiring 13 was about 5 to 70 nm, and the step portion was formed. The first coated glass 21 having a thickness of about 300 nm is accumulated in the groove and the groove.
Next, 400 W in an Ar atmosphere of about 0.1 mtorr.
Of the first coated glass 21 on at least the region of the first metal wiring 13 by applying a high frequency bias of
Are removed (FIG. 1 (b)). In the step of removing the coated glass 22, a reactive ion etcher or the like may be used, but since the etching rate of the coated glass is generally much higher than that of the vapor-phase grown silicon oxide film, the selectivity is low. I like the etcher. Next, after vapor-depositing the third silicon oxide film 19 to a thickness of 150 nm, the second coated glass 23 was spin-coated and then N 2 at 400 ° C.
After annealing and again removing the coated glass 23 on the flat portion by dry etching, a fourth silicon oxide film 20 was vapor-grown (FIG. 1C). At this time, the third
The fourth silicon oxide films 19 and 20 were grown by the same method as the first silicon oxide film 17. When the annealing temperature of the second coated glass 22 is lower than that of the first coated glass 21, there are less problems with cracks due to degassing and field reverse breakdown voltage. Then CHF3, C
The silicon oxide films 17, 19 and 20 on the first metal wiring 13 are anisotropically dry-etched by using F4 and He gas at a pressure of 300 mtorr to open through holes of 0.5 μm square, and at the same time, inside the holes. The antireflection film 24 was also removed. The antireflection film 24 may be left as it is, but the hole resistance becomes lower when it is removed. Next, as the adhesion layer 15, T
After iN was grown to a thickness of about 100 nm, W400 and H2 or SiH4 was used as a main gas, and W16 was grown to a total thickness of about 400 nm by a low pressure vapor phase method so that the through holes were also filled with W16. Next, SF6 and Ar gas are introduced, and high frequency 200 W,
The etch back of W was performed under the condition of 0.2 torr, and the TiN of the adhesion layer 15 was also etched back and removed by using Cl2 and Ar. Incidentally, it is also possible to leave the TiN of the adhesion layer 15 as it is without etching and pattern it simultaneously with the etching of the second metal wiring. Since the flatness of the interlayer film surface is good, the plasma emission wavelength is monitored at the end point of the etch back, and the film thickness of W16 vapor-grown is equivalent to 1 /
The overetching of 5% was performed, and as a result, the residue 26 of W16 was formed in the space region and the step portion on the first metal wiring 13.
Moreover, in the through hole portion, the W16 surface did not drop largely from the interlayer insulating film surface as in the conventional case, and the reproducibility was good. Then, the same Al alloy as that of the first metal wiring 13 is applied to the antireflection film 2 having a thickness of 800 nm.
4, TiN was sputter-grown to a thickness of 50 nm, the laminated film was selectively etched to form the second metal wiring 14 (FIG. 1 (d)), and the passivation film was vapor-phase grown.
Finally, a bonding pad portion was opened to take out the electrode to the outside.

The semiconductor device manufactured as described above is not limited to a specific space of the first metal wiring, and can be planarized as a whole without any cracks or voids in the interlayer insulating film. -When the W embedded in the hole is formed by etch back, the residue 26 and the drop of W16 in the hole are also no problem, and the covering property and contact property of the second metal wiring at the hole edge portion are improved. The characteristics and long-term reliability were improved. Furthermore, it has a structure where there is no contact between the coated glass and the metal wiring, and it is strong against corrosion.
Due to the generation of contamination due to hydrogen ions and the first silicon oxide film 17 formed by TEOS plasma reaction, there is a shielding effect against contamination and the problem of lowering the field inversion breakdown voltage as in the conventional case is eliminated.
The thickness of the third and fourth silicon oxide films 19 and 20 is
1000 Å or more is suitable from the viewpoint of film thickness controllability, etc., but it is possible to adjust the thickness with these films according to the need for the interlayer capacitance of the wiring, and the structure is formed on the coated glass, so it is flat. The conventional SiH 4
A silicon oxide film using is not a big problem.

On the other hand, the process of etching back the second silicon oxide film 18 may be changed in some cases because it may be used in common with the process of etching a contact or a through hole in the photoresist mask due to the generation of etching polymer or the use efficiency of the device. Since redeposition of the photoresist causes particle defects to reduce the yield, it is necessary to perform resist stripping with an organic chemical or washing with water as a post process. However,
If surface cleaning and drying are not sufficient, the wettability is poor in the subsequent coating glass step, and sometimes the liquid is repelled, the film thickness becomes nonuniform, and annealing causes cracks. As a countermeasure against this, as a result of various experiments, it is possible to mix O2 with 3% or more of O3 for 30 seconds or more in a lamp heating furnace of 350 ° C. or more, or to perform O2 plasma treatment, for example, 5 to 80 in a single wafer processing apparatus. 200W heated to ℃, 20 at 0.5 torr
It turns out that it is effective to do cleaning for a second,
Problems with the coating glass process have been resolved. These treatments are not limited to the lamps in the single-wafer type, the batch type, or the heating method, and may be those using a heater or the like.

In addition, the wiring structure is not limited to the two-layer wiring of the Al alloy shown in the embodiment, but can be applied to the case of using a refractory metal, a semiconductor, or a compound thereof.

[0012]

As described above, according to the present invention, particularly in an integrated circuit having a multi-layer wiring structure, the wiring interlayer film is flattened without being restricted by the design rule, and the through holes are formed by etching back. By improving the coverage of the multi-layered wiring through the embedded conductive material and preventing the corrosion of the metal wiring, it is possible to stabilize the electric characteristics and to stably supply a high-quality fine semiconductor device with a high yield.

[Brief description of drawings]

1A to 1D are schematic cross-sectional views of processes showing a method for manufacturing a semiconductor device according to the present invention.

2A to 2B are schematic cross-sectional views related to a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 11 Si Substrate 12 Field Insulating Film 13 First Metal Wiring 14 Second Metal Wiring 15 Adhesion Layer 16 W 17 First Silicon Oxide Film 18 Second Silicon Oxide Film 19 Third Silicon Oxide Film 20 Fourth Silicon Oxide film 21,22,23 Coating glass 24 Antireflection film 25 Silicon oxide film 26 Residue 27 Void 28 Crack

Claims (3)

[Claims] 1. In a semiconductor device having a multi-layer wiring structure, at least a step of forming a first metal wiring layer on a semiconductor substrate having a device surface formed on a desired surface, a gas containing organic silane and O2. A step of forming a first silicon oxide film which has been subjected to a plasma vapor phase reaction, a step of laminating a second silicon oxide film which has undergone a thermal vapor phase reaction of a gas containing organic silane and O3, and a predetermined thickness of the laminated insulating film. Etching back, laminating the first coated glass, etching back a predetermined thickness of the coated glass, laminating a third silicon oxide film, laminating the second coated glass, A step of etching back a predetermined thickness of the coated glass,
A method of manufacturing a semiconductor device, comprising: a step of laminating a fourth silicon oxide film; and a step of forming a second metal wiring after opening a through hole. 2. The second metal wiring according to claim 1, wherein at least the through hole is filled with a vapor-phase grown conductive material by etching back, and the second metal wiring is electrically connected to the first wiring layer through the conductive material. And a method for manufacturing a semiconductor device. 3. A semiconductor, characterized in that, after forming an interlayer insulating film of a multi-layer wiring structure or washing with water, heat treatment is performed in an atmosphere containing O3 or plasma treatment in an oxidizing atmosphere is performed, and then the coated glass is spin-coated. Device manufacturing method.