CN1309046C - Memory producing method - Google Patents
Memory producing method Download PDFInfo
- Publication number
- CN1309046C CN1309046C CNB021595690A CN02159569A CN1309046C CN 1309046 C CN1309046 C CN 1309046C CN B021595690 A CNB021595690 A CN B021595690A CN 02159569 A CN02159569 A CN 02159569A CN 1309046 C CN1309046 C CN 1309046C
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- Prior art keywords
- oxide layer
- manufacture method
- lining oxide
- memory
- substrate
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- 238000000034 method Methods 0.000 title claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 claims abstract description 24
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims description 13
- 239000011521 glass Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 4
- 239000000428 dust Substances 0.000 claims 2
- 238000009751 slip forming Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 67
- 239000004020 conductor Substances 0.000 description 11
- 238000000151 deposition Methods 0.000 description 10
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000002950 deficient Effects 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000004062 sedimentation Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- WVLBCYQITXONBZ-UHFFFAOYSA-N trimethyl phosphate Chemical compound COP(=O)(OC)OC WVLBCYQITXONBZ-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 229910000085 borane Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 150000002148 esters Chemical class 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- UORVGPXVDQYIDP-UHFFFAOYSA-N trihydridoboron Substances B UORVGPXVDQYIDP-UHFFFAOYSA-N 0.000 description 1
- WRECIMRULFAWHA-UHFFFAOYSA-N trimethyl borate Chemical compound COB(OC)OC WRECIMRULFAWHA-UHFFFAOYSA-N 0.000 description 1
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Abstract
The present invention relates to a method for producing a memory, which comprises: a substrate is provided, and a gate oxide layer and a character line are formed on the substrate; subsequently, a lining oxide layer is formed on the substrate to cover the substrate and the character line by the chemical vapor deposition technique without a plasma source; finally, a dielectric layer is formed on the lining oxide layer, wherein the lining oxide layer and the dielectric layer are continuously formed in the same reaction chamber.
Description
Technical field
The invention relates to a kind of manufacture method of memory, and particularly relevant for a kind of method that on memory component, forms lining oxide layer.
Background technology
Because read-only memory has non-volatile (Non-Volatile) characteristic of not losing wherein stored data because of power interruptions, therefore all must possess this type of memory in many electric equipment products, the normal running when starting shooting to keep electric equipment products.In the read-only memory the most the basis a kind of promptly be mask-type ROM, general mask-type ROM commonly used is to utilize channel transistor to be used as memory cell, and in sequencing (Program) stage optionally implanting ions to the passage area of appointment, by changing the purpose that start voltage (Threshold Voltage) reaches control store unit conducting in read operation (On) or closes (Off).
Be known in inner layer dielectric layer (the inter-layer dielectric of mask-type ROM, ILD) in the technology, the material of inner layer dielectric layer normally adopts boron-phosphorosilicate glass (borophosposilicateglass, BPSG), with air-breathing (gettering) that be applied to mobility ion (mobile ions) and obtain preferable flatness.Yet the admixture in the boron-phosphorosilicate glass for example is boron or phosphorus, may diffuse in silicon base or the grid by thermal process, and then cause the change of element characteristic or the problem of initiation element reliability.Therefore,, be known in before the deposition boron-phosphorosilicate glass, in substrate, form one deck lining oxide layer (liner oxidelayer) earlier to prevent the diffusion of admixture in the boron-phosphorosilicate glass for fear of the generation of the problems referred to above.Generally speaking, this lining oxide layer adopts plasma enhanced chemical vapor deposition method (plasma enhanced chemical vapordeposition usually, PECVD) deposition undoped silicon glass (Un-doped silicate glass, USG) to form, yet, the employed plasma source of plasma enhanced chemical vapor deposition method can produce infringement or make silicon base produce defective gate oxide, and then causes the generation of leakage current (leakage) and influence the reliability (reliability) of element.
Summary of the invention
Therefore, purpose of the present invention is to form lining oxide layer with the chemical vapour deposition technique that does not use plasma source (non-plasma), thereby can avoids the destruction of plasma source to gate oxide and substrate surface for a kind of manufacture method of memory is provided.
Another object of the present invention is for providing a kind of manufacture method of memory, can be in same reative cell successive sedimentation lining oxide layer and dielectric layer and do not need vacuum breaker, thereby can reduce generation of defects on the sedimentary deposit.
The present invention proposes a kind of manufacture method of memory, the method provides a substrate, and in this substrate, be formed with a gate oxide and a character line at least, then, in substrate, form lining oxide layer to cover substrate and character line with the chemical vapour deposition technique that does not use plasma source, then, form dielectric layer again on lining oxide layer, wherein lining oxide layer and dielectric layer are to form continuously in same reative cell.
As mentioned above, because the present invention adopts the chemical vapour deposition technique that does not use plasma source with the deposition lining oxide layer, therefore when carrying out depositing operation, can avoid plasma source that gate oxide and substrate surface are damaged.
And, because lining oxide layer of the present invention and dielectric layer are that successive sedimentation forms in same cvd reactive chamber, therefore can not increase the complexity and the degree of difficulty of technology.
Moreover, because the depositing operation of lining oxide layer and dielectric layer does not need vacuum breaker, therefore can reduce because the sedimentary deposit that vacuum breaker caused produces the problem of defective.
Description of drawings
Figure 1A to Fig. 1 C is depicted as the manufacturing process generalized section according to a kind of memory of preferred embodiment of the present invention.
100: substrate
102: the flush type drain electrode
104: the strip grid oxide layer
106: strip conductor layer (character line)
108: lining oxide layer
110: dielectric layer
Embodiment
The invention provides a kind of manufacture method of memory.Figure 1A to Fig. 1 C illustrate is the manufacturing process generalized section of a kind of memory of preferred embodiment of the present invention.
At first, please refer to Figure 1A, a substrate 100 is provided, this substrate 100 for example is the semiconductor silicon substrate.And in substrate 100 formed in order to as many flush types drain electrode of bit line (buried drain, BD) 102, even, because the section of Figure 1A, therefore only can be seen a flush type drain electrode 102 along the trend of flush type drain electrode 102 in Figure 1A.
Then, please continue, in substrate 100, form many strip grids oxide layer 104 and many strip conductors layer 106 with reference to Figure 1A.Wherein strip conductor layer 106 is in order to as character line, and its trend is perpendicular to flush type drain electrode 102, and the method that forms these a little strip conductor layers 106 and strip grid oxide layer 104 for example is to utilize a thermal oxidation method to form a thin oxide layer (not illustrating) on the surface of substrate 100 earlier, on thin oxide layer, form a doped polysilicon layer (not illustrating) in the mode of mixing when participating in the cintest more afterwards, utilize this doped polysilicon layer of lithography art pattern CADization and thin oxide layer then, to form strip conductor layer 106 and strip grid oxide layer 104.Wherein the strip conductor layer 106 between per two flush types drain electrode 102 promptly is considered as a grid structure with gate oxide 104, and this grid structure is implanted technology to determine whether it forms transistor with follow-up coding.
Then, please refer to Figure 1B, forming thin lining oxide layer 108 in the substrate 100 with on the strip conductor layer (character line) 106, wherein the material of this lining oxide layer 108 for example is a silicon dioxide, be preferably undoped silicon glass (USG), and its thickness for example is 500 dusts～2000 Izod right sides.And the method that forms this lining oxide layer 108 for example is substrate 100 to be inserted in the reative cell (do not illustrate), and not use the chemical vapour deposition technique of plasma source, for example be to use aumospheric pressure cvd method (atmospheric pleasure chemical vapor deposition, APCVD) or inferior aumospheric pressure cvd method (sub-atmospheric chemical vapordeposition, SACVD), (tetraethylorthosilicate is TEOS) with ozone (O with tetraethyl-metasilicate
3) be reacting gas source, and be to deposit about 60 holder (Torr)～450 holders, on substrate 100 and strip conductor layer 106, to form lining oxide layer 108 in operating pressure.
Because in the technology of Figure 1B, lining oxide layer 108 is to deposit to form with the aumospheric pressure cvd method of not using plasma source or inferior aumospheric pressure cvd method, therefore in the time of can avoiding known use plasma enhanced chemical vapor deposition method to deposit lining oxide layer, plasma source can damage gate oxide 104 and substrate 100 surfaces.
Then, please refer to Fig. 1 C, form one dielectric layer 110 to cover lining oxide layer 108 on lining oxide layer 108, wherein the material of this dielectric layer 110 for example is a silica, and is preferably boron-phosphorosilicate glass (BPSG).The method that wherein forms this dielectric layer 110 for example is with chemical vapour deposition technique, with tetraethyl-metasilicate, ozone, trimethyl borine acid esters (trimethylborate) and trimethyl phosphate (trimethylphosphate) as reacting gas source, and use the reative cell identical with depositing lining oxide layer 108, under the situation of substrate 100 not being taken out, that is be under the condition of vacuum breaker not, to deposit continuously to form in same reative cell.Even the follow-up technology of finishing mask-type ROM is known by being familiar with this skill person, does not repeat them here.
In the technology of above-mentioned Fig. 1 C, because lining oxide layer 108 can form in same cvd reactive chamber with dielectric layer 110 in successive sedimentation, so depositing operation do not need vacuum breaker, thereby can reduce because the sedimentary deposit that vacuum breaker caused produces the problem of defective.
In addition, in above-mentioned preferred embodiment, both sides in strip conductor layer 106 (character line) do not form clearance wall, yet can also look technologic needs, both sides at strip conductor layer 106 form clearance wall, again according to the technology of above-mentioned Figure 1B, on substrate 100, strip conductor layer 106 and clearance wall, form lining oxide layer 108 afterwards.
Moreover, though in preferred embodiment of the present invention, be to explain with mask-type ROM, yet the technology of lining oxide layer-inner layer dielectric layer of the present invention does not limit and is applied to mask-type ROM, can also be applied to other any element that has been formed with grid structure, for example be to be applied to dynamic randon access read-only memory (DRAM) or flash memory memory components such as (Flashmemory), its technology for example is after forming grid structure on the semiconductor element, technology according to Figure 1B, on the semiconductor-based end and grid structure, form lining oxide layer, and then, in same reative cell and on lining oxide layer, form dielectric layer continuously according to the technology of Fig. 1 C.
In sum, because the present invention is not to use the chemical vapour deposition technique of plasma source, it for example is the deposition that aumospheric pressure cvd method or inferior aumospheric pressure cvd method are carried out lining oxide layer, therefore when carrying out depositing operation, can not use plasma source, thereby can avoid known plasma source that the structure of gate oxide and substrate surface is damaged, and then can avoid the change and the reliability that improves element of element characteristic.
And, because lining oxide layer of the present invention and dielectric layer are that successive sedimentation forms in same reative cell, therefore can't increase the complexity and the degree of difficulty of technology.
Moreover, because the depositing operation of lining oxide layer of the present invention and dielectric layer does not need vacuum breaker, therefore can reduce, and then improve the reliability of element because the sedimentary deposit that vacuum breaker caused produces the problem of defective.
Claims (15)
1. the manufacture method of a memory is characterized in that, this method comprises the following steps:
One substrate is provided, and in this substrate, is formed with a character line at least;
With a chemical vapour deposition technique that does not use plasma source, in this substrate, form a lining oxide layer to cover this substrate and this character line; And
Form a dielectric layer on this lining oxide layer, wherein this lining oxide layer and this dielectric layer are to form continuously in same reative cell.
2. the manufacture method of memory as claimed in claim 1 is characterized in that, the material of this lining oxide layer comprises undoped silicon glass.
3. the manufacture method of memory as claimed in claim 1 is characterized in that, the thickness of this lining oxide layer is between 500 dust to 2000 dusts.
4. the manufacture method of memory as claimed in claim 1 is characterized in that, this does not use the chemical vapour deposition technique of plasma source to comprise to be selected from aumospheric pressure cvd and time aumospheric pressure cvd one of them.
5. the manufacture method of memory as claimed in claim 1 is characterized in that, deposits the employed reacting gas source of this lining oxide layer and comprises tetraethyl-metasilicate and ozone.
6. the manufacture method of memory as claimed in claim 1 is characterized in that, this operating pressure that does not use the chemical vapour deposition technique of plasma source is that 60 holders are between 450 holders.
7. the manufacture method of memory as claimed in claim 1 is characterized in that, the material of this dielectric layer comprises boron-phosphorosilicate glass.
8. the manufacture method of memory as claimed in claim 1 is characterized in that, more forms a gate oxide between this character line and this substrate.
9. the manufacture method of a semiconductor element is applicable in the semiconductor substrate, and this semiconductor-based end comprises that at least a grid structure is formed thereon, it is characterized in that, this method comprises the following steps:
With a chemical vapour deposition technique that does not use plasma source, form a lining oxide layer and cover this semiconductor-based end and this grid structure; And
Form a dielectric layer on this lining oxide layer, wherein this lining oxide layer and this dielectric layer are to form continuously in same reative cell.
10. the manufacture method of semiconductor element as claimed in claim 9 is characterized in that, the material of this lining oxide layer comprises undoped silicon glass.
11. the manufacture method of semiconductor element as claimed in claim 9 is characterized in that, the thickness of this lining oxide layer is between 500 dust to 2000 dusts.
12. the manufacture method of semiconductor element as claimed in claim 9 is characterized in that, this does not use the chemical vapour deposition technique of plasma source to comprise to be selected from aumospheric pressure cvd method and time aumospheric pressure cvd method one of them.
13. the manufacture method of semiconductor element as claimed in claim 9 is characterized in that, deposits the employed reacting gas source of this lining oxide layer and comprises tetraethyl-metasilicate and ozone.
14. the manufacture method of semiconductor element as claimed in claim 9 is characterized in that, this operating pressure that does not use the chemical vapour deposition technique of plasma source is that 60 holders are between 450 holders.
15. the manufacture method of semiconductor element as claimed in claim 9 is characterized in that, the material of this dielectric layer comprises boron-phosphorosilicate glass.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021595690A CN1309046C (en) | 2002-12-25 | 2002-12-25 | Memory producing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021595690A CN1309046C (en) | 2002-12-25 | 2002-12-25 | Memory producing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1510739A CN1510739A (en) | 2004-07-07 |
| CN1309046C true CN1309046C (en) | 2007-04-04 |
Family
ID=34237535
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021595690A Expired - Lifetime CN1309046C (en) | 2002-12-25 | 2002-12-25 | Memory producing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1309046C (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08255791A (en) * | 1995-03-17 | 1996-10-01 | Nec Corp | Formation of interlayer insulating film of semiconductor device |
| CN1157483A (en) * | 1996-02-14 | 1997-08-20 | 台湾茂矽电子股份有限公司 | Method for making dielectric layer of integrated circuit |
| US5731241A (en) * | 1997-05-15 | 1998-03-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned sacrificial oxide for shallow trench isolation |
| US5811345A (en) * | 1997-09-18 | 1998-09-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Planarization of shallow- trench- isolation without chemical mechanical polishing |
| US5854114A (en) * | 1997-10-09 | 1998-12-29 | Advanced Micro Devices, Inc. | Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide |
| US6040227A (en) * | 1998-05-29 | 2000-03-21 | Taiwan Semiconductor Manufacturing Company | IPO deposited with low pressure O3 -TEOS for planarization in multi-poly memory technology |
| US6136642A (en) * | 1998-12-23 | 2000-10-24 | United Microelectronics Corp. | Method of making a dynamic random access memory |
| US6294483B1 (en) * | 2000-05-09 | 2001-09-25 | Taiwan Semiconductor Manufacturing Company | Method for preventing delamination of APCVD BPSG films |
| US6350662B1 (en) * | 1999-07-19 | 2002-02-26 | Taiwan Semiconductor Manufacturing Company | Method to reduce defects in shallow trench isolations by post liner anneal |
| US6489254B1 (en) * | 2000-08-29 | 2002-12-03 | Atmel Corporation | Method of forming pre-metal dielectric film on a semiconductor substrate including first layer of undoped oxide of high ozone:TEOS volume ratio and second layer of low ozone doped BPSG |
-
2002
- 2002-12-25 CN CNB021595690A patent/CN1309046C/en not_active Expired - Lifetime
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08255791A (en) * | 1995-03-17 | 1996-10-01 | Nec Corp | Formation of interlayer insulating film of semiconductor device |
| CN1157483A (en) * | 1996-02-14 | 1997-08-20 | 台湾茂矽电子股份有限公司 | Method for making dielectric layer of integrated circuit |
| US5731241A (en) * | 1997-05-15 | 1998-03-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned sacrificial oxide for shallow trench isolation |
| US5811345A (en) * | 1997-09-18 | 1998-09-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Planarization of shallow- trench- isolation without chemical mechanical polishing |
| US5854114A (en) * | 1997-10-09 | 1998-12-29 | Advanced Micro Devices, Inc. | Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide |
| US6064105A (en) * | 1997-10-09 | 2000-05-16 | Vantis Corporation | Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide |
| US6040227A (en) * | 1998-05-29 | 2000-03-21 | Taiwan Semiconductor Manufacturing Company | IPO deposited with low pressure O3 -TEOS for planarization in multi-poly memory technology |
| US6136642A (en) * | 1998-12-23 | 2000-10-24 | United Microelectronics Corp. | Method of making a dynamic random access memory |
| US6350662B1 (en) * | 1999-07-19 | 2002-02-26 | Taiwan Semiconductor Manufacturing Company | Method to reduce defects in shallow trench isolations by post liner anneal |
| US6294483B1 (en) * | 2000-05-09 | 2001-09-25 | Taiwan Semiconductor Manufacturing Company | Method for preventing delamination of APCVD BPSG films |
| US6489254B1 (en) * | 2000-08-29 | 2002-12-03 | Atmel Corporation | Method of forming pre-metal dielectric film on a semiconductor substrate including first layer of undoped oxide of high ozone:TEOS volume ratio and second layer of low ozone doped BPSG |
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| Publication number | Publication date |
|---|---|
| CN1510739A (en) | 2004-07-07 |
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