JPH09199614A - Semiconductor storage and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the increase in the resistance of a wiring layer by suppressing the diffusion of an impurity from a flattening insulation film in a contact hole to the wiring layer. SOLUTION: A polycrystalline Si layer 54 is machined to the pattern of the gate electrode of a thin-film transistor at a memory cell array part 32 and is machined to a pattern connected to a P<+> diffusion layer 44 via a contact hole 53 at a surrounding circuit part 33. Then, after SiO2 film 55 as a gate oxide film is deposited, oxidation is made at a low temperature, thus fojming a thin SiO2 film 74 from the polycrystalline Si layer 54 on the inner side surface of the contact hole 53 and suppressing the diffusion of phosphor to the polycrystalline Si layer 54 from BPSG film 47.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device called a TFT load type SRAM and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIG. 13 shows an equivalent circuit of a memory cell of a TFT load type SRAM. The flip-flop 11 of this memory cell includes a driving NMOS transistor 1
The flip-flop 11 and the transfer NMOS transistors 16 and 17 constitute a memory cell.

A ground line 21 is connected to the sources of the NMOS transistors 12 and 13, and a power supply line 22 is connected to the sources of the PMOS transistors 14 and 15. The word line 23 is connected to the NMOS transistor 16,
The gate electrodes of the NMOS transistors 17 are connected to the source / drain of each of the NMOS transistors 16 and 17, and the bit lines 24 and 25 are connected to each other.

Of the transistors 12 to 17, the NMO
The S transistors 12, 13, 16 and 17 are bulk transistors in which a channel region is formed in a semiconductor substrate, while the PMOS transistors 14 and 15 are polycrystalline Si stacked on top of the NMOS transistors 12 and 13 and the like.
It is a thin film transistor (TFT) in which a channel region is formed in a layer.

FIG. 14 shows a T having the equivalent circuit as described above.
1 shows a conventional example of an FT load type SRAM. In this conventional example, an N type Si substrate 31 is used.
4 shows a memory cell array section 32 and a contact section 34 for connecting the power supply line 22 and the diffusion layer of the Si substrate 31 in the peripheral circuit section 33.

On the surface of the Si substrate 31, Si for element isolation is formed.
An O ₂ film 35 is selectively formed, and a P well 36 is formed in the Si substrate 31 of the memory cell array section 32. Further, a SiO ₂ film 37 as a gate oxide film is formed on the surface of the element active region surrounded by the SiO ₂ film 35.

The polycide layer 38 on the Si substrate 31 is NM
The gate electrodes of the OS transistors 12 and 13 and the word line 2
3 and the like are formed, and the N ⁻ diffusion layer 41 is formed in self-alignment with the polycide layer 38 and the SiO ₂ film 35 of the memory cell array portion 32.

Side wall spacers made of the SiO ₂ film 42 are formed in the polycide layer 38, and the N ⁺ diffusion layer 43 is formed in a self-aligned manner with respect to the SiO ₂ film 42 of the memory cell array portion 32, thereby forming an LDD structure. NMOS transistors 12, 13, 16 and 17 are formed. A P ⁺ diffusion layer 44 is formed in the peripheral circuit section 33. Polycide layer 38 and the like are covered with the SiO ₂ film 45 as an interlayer insulating film, a polycide layer 4 on the SiO ₂ film 45
A ground wire 21 is formed at 6.

The polycide layer 46 and the like are covered with a BPSG film 47 as a flattening insulating film.
A SiO ₂ film 51 is formed on top. A contact hole 52 reaching the polycide layer 38 as the gate electrode of the NMOS transistors 12 and 13 and the N ⁺ diffusion layer 43 is formed in the BPSG film 47 of the memory cell array portion 32, and the BPSG film 47 of the peripheral circuit portion 33. And so on, P ⁺
A contact hole 53 reaching the diffusion layer 44 is formed.

The SiO ₂ film 51 of the memory cell array portion 32
An N ⁺ -type polycrystalline Si layer 54 is formed thereon as the gate electrodes of the PMOS transistors 14 and 15.
This polycrystalline Si layer 54 is connected to both the polycide layer 38 and the N ⁺ diffusion layer 43 via the contact hole 52,
So-called shared contacts are formed.

A P ⁺ -type polycrystalline Si layer 54 is also formed on the SiO ₂ film 51 of the peripheral circuit portion 33, and this polycrystalline Si layer 54 is provided with a P ⁺ diffusion layer through the contact hole 53. Connected to 44.

The polycrystalline Si layer 54 and the like are covered with a SiO ₂ film 55 as a gate oxide film of the PMOS transistors 14 and 15, and contact holes 56 and 57 reaching the polycrystalline Si layer 54 are formed in the memory cell array portion 32 and the periphery. Circuit part 3
3 is formed on each of the SiO ₂ films 55.

The SiO ₂ film 55 of the memory cell array portion 32
A P ⁺ -type polycrystalline Si layer 61 is formed on the active layers of the PMOS transistors 14 and 15 and the power supply line 22, and the polycrystalline Si layer 61 is formed through the contact hole 56. It is connected to 54. Power line 22
The P ⁺ -type polycrystalline Si layer 61 as a layer extends up to the SiO ₂ film 55 of the peripheral circuit section 33.
Layer 61 is connected to polycrystalline Si layer 54 via contact hole 57.

[0014] polycrystalline Si layer 61 and the like are covered with the SiO ₂ film 62, BPSG film 63 is formed as a flattening insulating film on the SiO ₂ film 62. Peripheral circuit section 33
A contact hole 64 reaching the P ⁺ diffusion layer 44 is formed in the BPSG films 63, 47, etc., and the contact hole 64 is filled with a barrier metal layer 65 and a tungsten layer 66.

Barrier metal layer 65 and tungsten layer 6
A wiring composed of a barrier metal layer 67, an Al layer 71 and an antireflection film 72 is connected to the wiring 6, and the Al layer 7
1 and the like are covered with a surface protective film (not shown).

By the way, when an optical system having a large numerical aperture and a high resolution is used for lithography in order to form the polycrystalline Si layers 54 and 61 in a fine pattern, conversely, the depth of focus of this optical system is the numerical aperture. It decreases in inverse proportion to the square of. Therefore, it is necessary to form the BPSG film 47 as a flattening insulating film in the lower layer of the polycrystalline Si layers 54 and 61 so that the polycrystalline Si layers 54 and 61 have the same height.

[0017]

However, as the planarizing insulating film, a reflow film such as a PSG film or an AsSG film is generally used in addition to the BPSG film 47, and any reflow film contains N-type impurities. Contains. In the conventional example described above, since the P ⁺ -type polycrystalline Si layer 54 is in contact with the BPSG film 47 on the inner surface of the contact hole 53 of the peripheral circuit portion 33, the N-type impurity in the BPSG film 47 is The resistance of the polycrystalline Si layer 54 in the contact hole 53 was increased by diffusing into the polycrystalline Si layer 54.

Polycrystalline Si layer 5 in contact hole 53
When the resistance of No. 4 increases, the potential drop in the polycrystalline Si layer 54 increases, so that low voltage operation becomes difficult, and the power supply voltage supplied to the memory cell array unit 32 decreases and the data retention characteristic deteriorates. To do.

The BPSG film 47 to the polycrystalline Si layer 5
In order to suppress the diffusion of the N-type impurity into 4, the entire surface of the deposited SiO ₂ film or the like is etched back,
Forming side wall spacers on the inner surface of the contact hole 53 in a self-aligned manner is also considered.

However, in this method, the contact hole 53
Sidewall spacers are also formed on the inner side surfaces of the contact holes 52 for which a finer design rule is used, and the contact area in the contact holes 52 is reduced by the width of the bottom surface of the sidewall spacers. For this reason, the contact resistance in the contact hole 52 increases, which again makes it difficult to operate at low voltage and deteriorates the data retention characteristic.

[0021]

According to another aspect of the present invention, there is provided a semiconductor memory device, wherein a memory cell is formed by using a flip-flop having a thin film transistor as a load element, and the memory cell is formed on a flattening insulating film above a semiconductor substrate. A thin film transistor is formed, a contact hole reaching a diffusion layer of a peripheral circuit portion penetrates the flattening insulating film, and a wiring layer forming the thin film transistor is connected to the diffusion layer through the contact hole. In this semiconductor memory device, an oxide film of the wiring layer is formed on the inner side surface of the contact hole.

A semiconductor memory device according to a second aspect of the present invention is the semiconductor memory device according to the first aspect, wherein the flattening insulating film is a reflow film containing an impurity of a conductivity type opposite to that of the thin film transistor. There is.

A method of manufacturing a semiconductor memory device according to claim 3 is
A memory cell is configured using a flip-flop having a thin film transistor as a load element, the thin film transistor is formed on a planarization insulating film that is an upper layer than a semiconductor substrate, and a contact hole reaching a diffusion layer of a peripheral circuit portion is formed. A method of manufacturing a semiconductor memory device, wherein a wiring layer that penetrates through the planarization insulating film and that constitutes the thin film transistor is connected to the diffusion layer through the contact hole, after forming the wiring layer. By depositing a gate oxide film of the thin film transistor and performing an oxidation process after depositing the gate oxide film, an oxide film of the wiring layer is formed between the inner surface of the contact hole and the wiring layer. And a step of forming.

A method of manufacturing a semiconductor memory device according to claim 4 is
The method of manufacturing a semiconductor memory device according to claim 3, wherein a reflow film containing an impurity having a conductivity type opposite to that of the thin film transistor is used as the planarization insulating film.

A method of manufacturing a semiconductor memory device according to claim 5 is
The method of manufacturing a semiconductor memory device according to claim 3, wherein the temperature of the oxidation treatment is 700 to 750 ° C.

In the semiconductor memory device according to the present invention, the oxide film of the wiring layer is formed on the inner side surface of the contact hole connecting the wiring layer forming the thin film transistor which is the load element of the memory cell to the diffusion layer of the peripheral circuit section. Therefore, even if the flattening insulating film in which the contact hole is formed contains impurities, the diffusion of impurities from the flattening insulating film to the wiring layer is suppressed by the oxide film.

In the method of manufacturing a semiconductor memory device according to the present invention, the oxidation treatment is performed after depositing the gate oxide film of the thin film transistor which is the load element of the memory cell, and the contact for the wiring layer forming the thin film transistor is performed. In the hole, a thin oxide film of the wiring layer can be formed only on the inner surface of the contact hole by the oxidation treatment.

Therefore, in addition to the contact hole connecting the wiring layer forming the thin film transistor to the diffusion layer of the peripheral circuit portion, the contact hole connecting the wiring layer to the diffusion layer of the memory cell array portion or the like is formed. Even if they are formed, it is possible to form a thin oxide film of the wiring layer only on the inner side surfaces of these contact holes and not form this oxide film on the bottom surface of the contact holes.

Moreover, since the oxidation process after depositing the gate oxide film is a process generally performed to improve the film quality of the gate oxide film, a thin oxide film of the wiring layer is formed on the inner surface of the contact hole. No additional steps need to be performed to do this.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS. Also in the TFT load type SRAM of this embodiment, the equivalent circuit of the memory cell is the same as that already shown in FIG. In the TFT load type SRAM of the present embodiment, FIG. 1 shows a memory cell array section 32 and a peripheral circuit section 33 including a power supply line 22 and a Si.
The contact portion 34 for connecting to the P ⁺ diffusion layer 44 of the substrate 31 is shown.

In order to manufacture the TFT load type SRAM of this embodiment, as shown in FIG. 2, an element isolation SiO ₂ film 35 having a film thickness of about 400 nm is formed on the N type Si substrate 3.
It is selectively formed on the surface of No. 1 by the LOCOS method. And
As shown in FIG. 3, the Si substrate 3 of the memory cell array unit 32
1 is selectively ion-implanted with B to form a P well 36, and then a SiO ₂ film 37 as a gate oxide film is formed on the surface of the element active region surrounded by the SiO ₂ film 35.

After that, a polycide layer 38 is formed by sequentially depositing a polycrystalline Si layer and a silicide layer, both of which have a film thickness of about 70 to 150 nm, on the Si substrate 31 by the CVD method or the sputtering method. , 13 gate electrodes, the word line 23, and the like are formed.

Then, NMOS transistor formation regions (not shown) of the memory cell array section 32 and the peripheral circuit section 33.
Using the polycide layer 38 and the SiO ₂ film 35 as a mask to ion-implant As into the Si substrate 31, the N ⁻ diffusion layer 4
Form one. In addition, the contact portion 3 of the peripheral circuit portion 33
4 and the polycide layer 38 and the SiO ₂ film 35 in the PMOS transistor formation region (not shown) as a mask.
B is ion-implanted into the substrate 31 to form a P ⁻ diffusion layer 73.

Next, as shown in FIG. 4, RIE is performed on the entire surface of the SiO ₂ film 42 deposited on the entire surface, and this SiO ₂ film is formed.
Sidewall spacers of film 42 are formed in polycide layer 38. Then, the memory cell array unit 32 and the peripheral circuit unit 3
Polycide layer 3 with NMOS transistor formation region 3
8 and the SiO ₂ films 35 and 42 as a mask and the Si substrate 3
1 is ion-implanted with As to form an N ⁺ diffusion layer 43,
LDD structure NMOS transistors 12, 13, 16,
17 is formed.

Further, the contact portion 34 of the peripheral circuit portion 33
And the polycide layer 38 in the PMOS transistor formation region
And the Si substrate 31 using the SiO ₂ films 35 and 42 as a mask
Is ion-implanted with B to form a P ⁺ diffusion layer 44.

Next, as shown in FIG. 5, a SiO ₂ film 45 as an interlayer insulating film is deposited to a film thickness of 30-100.
CVD of a polycrystalline Si layer and a silicide layer having a thickness of about nm
The ground line 21 is formed by a polycide layer 46 formed by sequentially depositing on the SiO ₂ film 45 by a sputtering method or a sputtering method.

Next, as shown in FIG. 6, the film thickness is 200-5.
A BPSG film 47 or the like having a thickness of about 00 nm is deposited on the reflow film, and BP is annealed at a temperature of about 850 to 900 ° C.
The SG film 47 is reflowed to flatten the surface of the BPSG film 47. Then, SiO is formed on the BPSG film 47.
_{2 The} film 51 is formed.

Next, as shown in FIG. 7, a polycide layer 38 as a gate electrode of the NMOS transistors 12 and 13 is formed.
And the contact hole 52 reaching the N ⁺ diffusion layer 43 is formed in the BPSG film 47 or the like of the memory cell array portion 32, and at the same time, the contact hole 53 reaching the P ⁺ diffusion layer 44 is formed in the BPSG film 47 or the like of the peripheral circuit portion 33.

Next, as shown in FIG.
The polycrystalline Si layer 54 having a thickness of about 00 nm is formed on the SiO ₂ film 51.
The polycrystalline Si layer 5 formed on the memory cell array portion 32
4 is ion-implanted with Phos or As to make this polycrystalline Si layer 54 an N ⁺ type, and the polycrystalline Si layer of the peripheral circuit portion 33 is formed.
BF ₂ is ion-implanted into the layer 54 to form the polycrystalline Si layer 5
Make 4 a P ⁺ type.

Then, in the memory cell array portion 32, the PMOS transistors 14 and 1 connected to both the polycide layer 38 and the N ⁺ diffusion layer 43 through the contact hole 52.
The polycrystalline Si layer 54 is processed into the pattern of the gate electrode of No. 5 to form a so-called shared contact. In the peripheral circuit portion 33, the polycrystalline Si layer 54 is processed into a pattern connected to the P ⁺ diffusion layer 44 via the contact hole 53.

Next, as shown in FIG. 9, a SiO ₂ film 55 as a gate oxide film of the PMOS transistors 14 and 15 is formed.
Is deposited by the CVD method, and the temperature at the time of entering the furnace is set to 700 as well as the gate oxidation for improving the film quality of the SiO ₂ film 55.
Wet oxidation is performed at a low temperature of about 750 ° C. at a heating temperature of about 750 ° C.

After this low temperature oxidation, the contact hole 53
Since the contact resistance at B is rather low, a thin SiO ₂ film 74 is formed from the polycrystalline Si layer 54 on the inner surface of the contact hole 53, as shown in FIG.
The diffusion of phosphorus from the PSG film 47 to the polycrystalline Si layer 54 is suppressed, and moreover, S is formed on the bottom surface of the contact hole 53.
It is considered that the iO ₂ film 74 is not formed. Also,
Even the contact hole 52 has a thin SiO ₂ film only on its inner surface.
It is considered that the film 74 is formed.

Next, as shown in FIG. 10, a polycrystalline Si layer 5 is formed.
4 are formed in the SiO ₂ film 55 of each of the memory cell array section 32 and the peripheral circuit section 33.

Next, an amorphous Si layer having a film thickness of about 10 to ₂₀ nm is deposited on the SiO ₂ film 55 by the CVD method,
Of the amorphous Si layer, the PMOS transistor 14,
B is ion-implanted into a portion other than the channel region of 15.
Then, as shown in FIG. 11, the amorphous Si layer is converted into a P ⁺ -type polycrystalline Si layer 61 by crystal growth by annealing.
To

Thereafter, in the memory cell array section 32, P
Active layers of MOS transistors 14 and 15 and power supply line 22
The polycrystalline Si layer 61 is processed into the pattern of, and the polycrystalline Si layer 61 is connected to the polycrystalline Si layer 54 through the contact hole 56. The polycrystalline Si layer 61 as the power supply line 22 extends up to the SiO ₂ film 55 of the peripheral circuit portion 33, and the polycrystalline Si layer 61 is connected to the polycrystalline Si layer 54 via the contact hole 57.

Next, as shown in FIG. 12, a SiO ₂ film 62 is formed.
Is further deposited, and a reflow film such as the BPSG film 63 is further deposited, and the BPSG film 63 is reflowed by annealing.
Is flattened.

Next, as shown in FIG. 1, contact holes 64 reaching the P ⁺ diffusion layer 44 are formed in the BPSG films 63, 47, etc. of the peripheral circuit section 33, and the contact holes are formed by the barrier metal layer 65 and the tungsten layer 66. Fill 64. Then, the wiring including the barrier metal layer 67, the Al layer 71, and the antireflection film 72 is connected to the barrier metal layer 65 and the tungsten layer 66.
Then, the Al layer 71 and the like are covered with a surface protective film (not shown) to complete the TFT load type SRAM.

In the above embodiments, the BPSG films 47 and 63 are used as the flattening insulating film.
A PSG film, an AsSG film, or the like may be used instead of the films 47 and 63. Further, although the PMOS transistors 14 and 15 are of the bottom gate type in the above-described embodiments, the top gate type PMOS transistor is replaced by the flip-flop 11.
The invention of the present application can be applied to a TFT load type SRAM which is used as a load element of the above.

[0049]

According to the semiconductor memory device of the present invention,
Even if impurities are contained in the flattening insulating film in which the contact holes are formed, the diffusion of the impurities from the flattening insulating film to the wiring layer is suppressed by the oxide film. Therefore, even if the conductivity type of the impurities contained in the planarization insulating film and the conductivity type of the impurities contained in the wiring layer are opposite to each other, the increase in the resistance of the wiring layer in the contact hole is suppressed. Therefore, low voltage operation is possible and the data retention characteristic is excellent.

In the method of manufacturing a semiconductor memory device according to the invention of the present application, a contact hole connecting the wiring layer forming the thin film transistor to the diffusion layer of the peripheral circuit portion, the wiring layer of the diffusion layer of the memory cell array portion, etc. It is possible to form a thin oxide film of the wiring layer only on the inner side surface of the contact hole connected to the contact hole and not form this oxide film on the bottom surface of the contact hole.

Therefore, even if impurities are contained in the flattening insulating film in which the contact holes are formed, the diffusion of impurities from the flattening insulating film to the wiring layer can be suppressed by the oxide film, and the contact can be suppressed. It is possible to prevent the contact area from decreasing at the bottom surface of the hole.

Therefore, even if the conductivity type of the impurities contained in the planarization insulating film and the conductivity type of the impurities contained in the wiring layer are opposite to each other, an increase in the resistance of the wiring layer in the contact hole is suppressed. In addition, it is possible to prevent the contact resistance from increasing due to the reduction of the contact area at the bottom surface of the contact hole, and it is possible to manufacture a semiconductor memory device capable of low voltage operation and excellent data retention characteristics. .

Moreover, since it is not necessary to perform an additional step for forming a thin oxide film of the wiring layer on the inner surface of the contact hole, a low voltage operation can be performed without increasing the manufacturing cost and the data retention characteristic can be obtained. It is possible to manufacture an excellent semiconductor memory device.

[Brief description of drawings]

FIG. 1 is a side sectional view showing an embodiment of the present invention.

FIG. 2 is a side sectional view showing a first step for manufacturing one embodiment.

FIG. 3 is a side sectional view showing a step following FIG. 2;

FIG. 4 is a side sectional view showing a step following FIG. 3;

FIG. 5 is a side sectional view showing a step following FIG. 4;

FIG. 6 is a side sectional view showing a step following FIG. 5;

FIG. 7 is a side sectional view showing a step following FIG. 6;

8 is a side sectional view showing a step that follows FIG. 7. FIG.

9 is a side sectional view showing a step that follows FIG.

10 is a side sectional view showing a step that follows FIG.

FIG. 11 is a side sectional view showing a step following FIG. 10;

12 is a side sectional view showing a step that follows FIG. 11. FIG.

FIG. 13 is a TFT load type SRA to which the present invention can be applied.
FIG. 3 is an equivalent circuit diagram of an M memory cell.

FIG. 14 is a side sectional view showing a conventional example of the present invention.

[Explanation of symbols]

11 flip-flop 14 PMOS transistor 15 PMOS transistor 31 Si substrate 32 memory cell array section 33 peripheral circuit section 44 P ⁺ diffusion layer 47 BPSG film 53 contact hole 54 polycrystalline Si layer 55 SiO ₂ film 74 SiO ₂ film

Claims (5)

[Claims] 1. A memory cell is configured by using a flip-flop having a thin film transistor as a load element, the thin film transistor is formed on a planarization insulating film above a semiconductor substrate, and a diffusion layer of a peripheral circuit portion is formed. A contact hole penetrating through the planarization insulating film, and a wiring layer forming the thin film transistor is connected to the diffusion layer through the contact hole. A semiconductor memory device, wherein an oxide film of the wiring layer is formed on a side surface. 2. The semiconductor memory device according to claim 1, wherein the flattening insulating film is a reflow film containing impurities of a conductivity type opposite to that of the thin film transistor. 3. A memory cell is formed by using a flip-flop having a thin film transistor as a load element, the thin film transistor is formed on a flattening insulating film above a semiconductor substrate, and a diffusion layer of a peripheral circuit portion is formed. A contact hole penetrating the flattening insulating film, and a wiring layer forming the thin film transistor is connected to the diffusion layer via the contact hole. A step of depositing a gate oxide film of the thin film transistor after forming a layer; and an oxidation treatment after depositing the gate oxide film to form a wiring between the inner surface of the contact hole and the wiring layer. And a step of forming a layer oxide film. 4. The method of manufacturing a semiconductor memory device according to claim 3, wherein a reflow film containing an impurity having a conductivity type opposite to that of the thin film transistor is used as the planarization insulating film. 5. The temperature of the oxidation treatment is 700 to 750 ° C.
The method of manufacturing a semiconductor memory device according to claim 3, wherein