CN206259355U - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- CN206259355U CN206259355U CN201621053980.2U CN201621053980U CN206259355U CN 206259355 U CN206259355 U CN 206259355U CN 201621053980 U CN201621053980 U CN 201621053980U CN 206259355 U CN206259355 U CN 206259355U
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- gate electrode
- interlayer dielectric
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Abstract
The utility model provides semiconductor device, makes the stable conductivity of gate electrode.The semiconductor device of trench gate has：Drift region (10)；Base (20), its configuration is on drift region (10)；Launch site (30), its configuration is on base (20)；Inner wall insulation film (40), it configures the inwall in groove, and the groove extends and insertion launch site (30) and base (20) from the upper surface of launch site (30)；Gate electrode (50), it is opposed to configure on the inner wall insulation film (40) of the side of groove with the side of base (20)；And the interlayer dielectric (70) on gate electrode (50), gate electrode (50) is made up of polysilicon film, and interlayer dielectric (70) has：1st interlayer dielectric (71), its material changes the electric conductivity of gate electrode (50) when being contacted with gate electrode (50)；And the 2nd interlayer dielectric (72), its configuration is between gate electrode (50) and the 1st interlayer dielectric (71) so that the electric conductivity of gate electrode (50) is constant.
Description
Technical field
The utility model is related to the semiconductor device of trench gate.
Background technology
As the switch element (power semiconductor) of the switch motion for carrying out high current, using power MOSFET and absolutely
Edge grid-type bipolar transistor (IGBT) etc..Using groove-shaped gate electrode construction (trench gate) in these switch elements, i.e.,
Gate insulating film and gate electrode are formed in the groove (groove) for being formed at semiconductor substrate.But, filled in the semiconductor of trench gate
In putting, the electric capacity (electric capacity between gate-to-drain) between gate electrode and drain region, the electric capacity (grid-collection between gate electrode and collecting zone
Interelectrode capacitance) etc. feedback capacity it is larger.Therefore, switching speed declines, and problem is produced in high frequency mo.
It is used to reduce the various methods of feedback capacity in research.For example, it has been disclosed that following construction：Match somebody with somebody in the side of groove
Gate electrode is put, in the electrode that the bottom surface configuration of groove is connected with emission electrode (for example, referring to patent document 1).
【Prior art literature】
【Patent document】
【Patent document 1】Japanese Unexamined Patent Publication 2015-201615 publications
Utility model content
The utility model problem to be solved
But, the impurity included in interlayer dielectric becomes the electric conductivity of the gate electrode being made up of polysilicon inside groove
Change, thus the electrical characteristic that can not be stablized.Therefore, the purpose of this utility model is, there is provided make the electric conductivity of gate electrode
The semiconductor device of the trench gate of stabilization.
The means used to solve the problem
A mode of the present utility model provides semiconductor device, and the semiconductor device has：The 1st half of 1st conductivity type
Conductive region；2nd semiconductor regions of the 2nd conductivity type, its configuration is on the 1st semiconductor regions；Lead the 3rd half of 1st conductivity type
Body region, its configuration is on the 2nd semiconductor regions；Inner wall insulation film, in the inwall of groove, the groove is from the 3rd semiconductor region for its configuration
The upper surface in domain extends and the semiconductor regions of insertion the 3rd and the 2nd semiconductor regions；Coordination electrode, itself and the 2nd semiconductor regions
Side is opposed to configuration on the inner wall insulation film of the side of groove；And the interlayer dielectric in coordination electrode, coordination electrode by
Polysilicon film is constituted, and interlayer dielectric has：1st interlayer dielectric, the material of the 1st interlayer dielectric connects with coordination electrode
Change the electric conductivity of coordination electrode when tactile；And the 2nd interlayer dielectric, its configuration is in coordination electrode and the 1st interlayer dielectric
Between so that the electric conductivity of coordination electrode is constant.
In the semiconductor device, the semiconductor device also has bottom-side electrodes, the bottom-side electrodes and the control
Electrode insulation is discretely configured on the inner wall insulation film of the bottom surface of the groove, and the interlayer dielectric is electric by the control
Insulated between pole and the bottom-side electrodes.
In the semiconductor device, the 1st interlayer dielectric is made up of bpsg film, the 2nd interlayer dielectric by
NSG films are constituted.
In the semiconductor device, the semiconductor device also has configuration in the 2nd interlayer dielectric and described
Heat oxide film between coordination electrode.
Another mode of the present utility model provides semiconductor device, and the semiconductor device has：The 1st of 1st conductivity type
Semiconductor regions；2nd semiconductor regions of the 2nd conductivity type, its configuration is on the 1st semiconductor regions；The of 1st conductivity type
3 semiconductor regions, its configuration is on the 2nd semiconductor regions；Inner wall insulation film, in the inwall of groove, the groove is from institute for its configuration
The upper surface for stating the 3rd semiconductor regions extends and the 3rd semiconductor regions and the 2nd semiconductor regions described in insertion；Control electricity
Pole, it is opposed to configuration on the inner wall insulation film of the side of the groove, by many with the side of the 2nd semiconductor regions
Crystal silicon film is constituted；Bottom-side electrodes, the inwall that it is configured in the bottom surface of the groove with the coordination electrode insulated separation is exhausted
On velum；1st interlayer dielectric, its landfill is made up of, by the coordination electrode and the bottom in the inside of the groove bpsg film
Insulated between the electrode of face；And the 2nd interlayer dielectric, its configuration between the coordination electrode and the 1st interlayer dielectric,
Suppress the diffusion of phosphorus, from least a portion of the lower surface of the coordination electrode to the distance of the bottom surface of the groove, than from
Distance of at least a portion of the lower surface of the bottom-side electrodes to the bottom surface of the groove.
In the semiconductor device, the 2nd interlayer dielectric is made up of NSG films.
In the semiconductor device, the semiconductor device also has configuration in the 2nd interlayer dielectric and described
Heat oxide film between coordination electrode.
In the semiconductor device, the upper table of the position than the bottom-side electrodes of the lower surface of the coordination electrode
The position in face is on the lower.
In the semiconductor device, the lower surface of the coordination electrode is formed as wedge surface as follows：It is described
The distance between the lower surface of coordination electrode and described bottom surface of the groove become with the side close to the groove
It is short.
In the semiconductor device, the bottom-side electrodes are following trapezoidal shape：The thickness of the bottom-side electrodes with
It is thinning close to the side of the groove.
In the semiconductor device, the distance of the bottom surface from the lower surface of the bottom-side electrodes to the groove
It is long in neighboring area in middle section ratio in the lower surface of the bottom-side electrodes.
In the semiconductor device, in top view, the length on the bearing of trend of the groove is wider than the groove
Degree length, and the width of the groove is wider than the interval of the adjacent groove.
In the semiconductor device, the area of the thickness of the inner wall insulation film in the bottom surface for being configured in the groove
The region of the side in domain, than being configured in the groove is thick.
In the semiconductor device, in the entire surface of the lower surface of the coordination electrode, from the control electricity
The lower surface of pole is to the distance of the bottom surface of the groove, than from the lower surface of the bottom-side electrodes to the groove
The distance of the bottom surface.
In the semiconductor device, from a part for the bottom-side electrodes side of the lower surface of the coordination electrode
Distance to the bottom surface of the groove, the distance than the bottom surface from the lower surface of the bottom-side electrodes to the groove
It is long, distance from another part of the lower surface of the coordination electrode to the bottom surface of the groove and from the bottom surface
The distance of the lower surface of electrode to the bottom surface of the groove is identical.
In the semiconductor device, the lower surface of the coordination electrode it is at least opposed with the bottom-side electrodes
The position of side, the position than the upper surface of the coordination electrode side of the bottom-side electrodes is upper.
Utility model effect
According to the utility model, using the teaching of the invention it is possible to provide make the semiconductor device of the trench gate of the stable conductivity of gate electrode.
Brief description of the drawings
Fig. 1 is the generalized section of the construction of the semiconductor device for showing implementation method of the present utility model.
Fig. 2 is the in-built schematic diagram of the groove of the semiconductor device for showing implementation method of the present utility model.
Fig. 3 is for illustrating that the operation section of the manufacture method of the semiconductor device of implementation method of the present utility model is illustrated
One of figure ().
Fig. 4 is for illustrating that the operation section of the manufacture method of the semiconductor device of implementation method of the present utility model is illustrated
Figure (two).
Fig. 5 is for illustrating that the operation section of the manufacture method of the semiconductor device of implementation method of the present utility model is illustrated
Figure (three).
Fig. 6 is for illustrating that the operation section of the manufacture method of the semiconductor device of implementation method of the present utility model is illustrated
Figure (four).
Fig. 7 is for illustrating that the operation section of the manufacture method of the semiconductor device of implementation method of the present utility model is illustrated
Figure (five).
Fig. 8 is for illustrating that the operation section of the manufacture method of the semiconductor device of implementation method of the present utility model is illustrated
Figure (six).
Fig. 9 is for illustrating that the operation section of the manufacture method of the semiconductor device of implementation method of the present utility model is illustrated
Figure (seven).
Figure 10 is for illustrating that the operation section of the manufacture method of the semiconductor device of implementation method of the present utility model shows
It is intended to (eight).
Figure 11 is showing for another construction of the inside of the groove of the semiconductor device for showing implementation method of the present utility model
It is intended to.
Figure 12 is another construction of the interlayer dielectric of the semiconductor device for showing implementation method of the present utility model
Schematic diagram.
Figure 13 is the generalized section of the construction of the semiconductor device of the variation for showing implementation method of the present utility model.
Figure 14 is the generalized section of the construction of the semiconductor device for showing other embodiment of the present utility model.
Figure 15 is the generalized section of the construction of the semiconductor device for showing other embodiment of the present utility model.
Figure 16 is the generalized section of the construction of the semiconductor device for showing other embodiment of the present utility model.
Figure 17 is showing for another construction of the inside of the groove of the semiconductor device for showing implementation method of the present utility model
It is intended to.
Figure 18 is showing for another construction of the inside of the groove of the semiconductor device for showing implementation method of the present utility model
It is intended to.
Label declaration
10 drift regions；20 bases；30 launch sites；40 inner wall insulation films；50 gate electrodes；60 collecting zones；65 termination area；
70 interlayer dielectrics；71 the 1st interlayer dielectrics；72 the 2nd interlayer dielectrics；73 heat oxide films；80 collecting electrodes；90 transmitting electricity
Pole；100 grooves；150 bottom-side electrodes.
Specific embodiment
Below, it is described with reference to implementation method of the present utility model.In following accompanying drawing, to same or similar
Part marks same or similar label.It should however be noted that accompanying drawing is schematical figure, the pass of thickness and planar dimension
System, the ratio of the length of each several part etc. are different from actual product.Therefore, specific size should be sentenced with reference to the following description
Fixed size.Also, also include the relation of the accompanying drawing size mutual to each other part different with ratio certainly.
Also, implementation method described below be example be used for be embodied technological thought of the present utility model device and
The shape of component parts, construction, configuration etc. are not defined as following sides by the mode of method, technological thought of the present utility model
Formula.Implementation method of the present utility model can carry out various changes in the range of claims.
The semiconductor device of implementation method of the present utility model has as shown in Figure 1：1st semiconductor region of the 1st conductivity type
Domain (drift region 10)；2nd semiconductor regions (base 20) of the 2nd conductivity type, its configuration is on the 1st semiconductor regions；1st is conductive
3rd semiconductor regions (launch site 30) of type, its configuration is on the 2nd semiconductor regions.It is exhausted inwall to be configured with the inwall of groove
Velum 40, the flute profile turns into and extends from the upper surface of the 3rd semiconductor regions and the semiconductor regions of insertion the 3rd and the 2nd semiconductor region
Domain and reach the 1st semiconductor regions.
Groove extends along the interarea of the layered product of above-mentioned semiconductor regions, and the length of the groove in the direction of extension is wider than groove
W is long for degree.Fig. 1 shows the section vertical with the direction of groove extension.
Semiconductor device shown in Fig. 1 is the IGBT of trench gate, and configuration is opposed in groove with the side with base 20
Side inner wall insulation film 40 on coordination electrode (gate electrode 50).As shown in figure 1, the bottom surface electricity of the lower surface of gate electrode 50
The side of pole 150 does not contact with the inner wall insulation film 40 of the bottom surface of groove.In addition, semiconductor device has and the insulated separation of gate electrode 50 ground
Configure the bottom-side electrodes 150 on the inner wall insulation film 40 of the bottom surface of groove.Bottom-side electrodes 150 are electrically connected with launch site 30.
1st conductivity type and the 2nd conductivity type are reciprocal conductivity types.That is, if the 1st conductivity type be N-shaped, if the 2nd lead
Electric type is p-type, if the 1st conductivity type be p-type, if the 2nd conductivity type be N-shaped.Below, illustratively explanation the 1st conductivity type be N-shaped,
2nd conductivity type is the situation of p-type.
As shown in figure 1, between gate electrode 50 and bottom-side electrodes 150 and gate electrode 50 lower surface and inner wall insulation
Between film 40, interlayer dielectric 70 is embedded with the gap of the inside of the groove in bottom-side electrodes 150.By layer insulation
Film 70 is by gate electrode 50 and the insulated separation of bottom-side electrodes 150.In semiconductor devices, from the lower surface of gate electrode 50 to the bottom of groove
The distance (hereinafter referred to as " the 1st apart from d1 ") in face, than the bottom surface from the lower surface of bottom-side electrodes 150 to groove distance (hereinafter referred to as
It is " the 2nd apart from d2 ") grow, or the 1st equal apart from d2 apart from d1 and the 2nd.That is, positioned at the gate electrode 50 of the lower section of gate electrode 50
And the thickness (referring to the thickness sum of inner wall insulation film 40 and interlayer dielectric 70 in Fig. 1) of the dielectric film between drift region 10,
Thickness than the dielectric film between the bottom-side electrodes 150 of the lower section of bottom-side electrodes 150 and drift region 10 (refers to interior in Fig. 1
The thickness of wall dielectric film 40) it is thick or equal.
Drift region 10 is configured on an interarea of the collecting zone 60 of p-type.In addition, between drift region 10 and collecting zone 60
It is configured with the field termination area 65 of the impurity concentration N-shaped higher than drift region 10.Semiconductor is limited in using field termination area 65 to fill
The amount in the hole of drift region 10 is reached under the conducting state put from collecting zone 60.Also, suppress the cut-off shape in semiconductor device
The depletion layer extended from the upper surface of drift region 10 under state reaches collecting zone 60.It is configured with another interarea of collecting zone 60
The collecting electrodes 80 electrically connected with collecting zone 60.
Gate electrode 50 is arranged opposite with base 20 across inner wall insulation film 40.Hair is optionally configured on the top of base 20
Penetrate area 30.Emission electrode 90 is configured on interlayer dielectric 70, and emission electrode 90 is connected with base 20 and launch site 30.By layer
Between dielectric film 70 gate electrode 50 and emission electrode 90 are electrically insulated.
In the semiconductor device shown in Fig. 1, across the surface of the base 20 opposed with gate electrode 50 of inner wall insulation film 40
It is the channel region to form raceway groove.That is, sent out as gate insulating film in the region between the gate electrode 50 and base 20 of inner wall insulation film 40
The effect of waving.Gate electrode 50 is at least arranged opposite with base 20 so that formed from launch site 30 to drift along groove in base 20
The raceway groove in area 10.Also, it is preferred that the end (end of the side of groove) of the corner side of the groove of gate electrode 50 extends to and compares base
20 and the interface of drift region 10 position low with the position that the side of groove is intersected, i.e. drift region 10 on.Thereby, it is possible in base 20
In be reliably formed raceway groove from launch site 30 to drift region 10 along groove, semiconductor device is reliably turned on.
As shown in figure 1, being each configured with gate electrode 50 in the opposed side of the inwall of groove.Also, in the extension side with groove
To in vertical section, gate electrode 50 is continuously configured along the inwall of groove, and gate electrode 50 is configured without in the bottom surface of groove.
Here, the action to the semiconductor device shown in Fig. 1 is illustrated.Between emission electrode 90 and collecting electrodes 80
Apply the collector voltage of regulation, the grid voltage of regulation is applied between emission electrode 90 and gate electrode 50.For example, colelctor electrode
Voltage is approximately 300V~1600V, and grid voltage is approximately 10V~20V.When semiconductor device so is set into conducting state, ditch
Road area is inverted to N-shaped and forms raceway groove from p-type.Electronics passes through in the raceway groove for being formed, and drift is injected into from emission electrode 90
In area 10.Between collecting zone 60 and drift region 10 turn into along biasing, hole (hole) from collecting electrodes 80 via collecting zone 60 successively
Move to drift region 10, base 20.When continuing to increase electric current, the hole from collecting zone 60 increases, hole accumulation
In the lower section of base 20.As a result, conducting voltage is modulated and reduced by conductivity.
In the case where making semiconductor device turn into cut-off state from conducting state, control gate voltage makes it than threshold value electricity
Force down.For example, making grid voltage reach and emitter voltage identical current potential or negative potential.Thus, the raceway groove of base 20 disappears
Lose, stop from emission electrode 90 to the injection of the electronics of drift region 10.The current potential of collecting electrodes 80 is higher than emission electrode 90, thus
Depletion layer extends from the interface of base 20 and drift region 10, and the hole accumulated in drift region 10 is leaked to emission electrode
90.Now, pass through in semiconductor regions of the hole between groove and groove and mobile.That is, the region between groove is the sucking-off in hole
Mouthful.
In the past, in the semiconductor device of trench gate, exist between the end of gate electrode and the end of bottom-side electrodes
Produce and discharge and the problem of malfunction.But, in the semiconductor device shown in Fig. 1, the depth of the width more than groove of groove, groove
Bottom surface it is relatively flat on the whole.Also, the position of the side at least opposed with bottom-side electrodes 150 of the lower surface of gate electrode 50
Put, it is more upper in the position of the upper surface of the side of gate electrode 50 than bottom-side electrodes 150.Also, from the lower surface of gate electrode 50 to
Lack the side opposed with bottom-side electrodes 150 to the distance of the bottom surface of groove, it is more electric than from the bottom surface of the side opposed with gate electrode 50
Distance of the lower surface of pole 150 to the bottom surface of groove.As a result, the end in the end of gate electrode and bottom-side electrodes can be reduced
Produced between portion and discharged and the situation of malfunction.
In addition, in the semiconductor device shown in Fig. 1, being preferably configured without gate electrode 50, gate electrode 50 in the bottom surface of groove
Lower surface it is more long with the distance between groove than the side of gate electrode 50 with the distance between groove.Therefore, it is possible to reduce gate electrode 50
And the feedback capacity (grid-inter-collector electric capacity) between collecting zone 60.
In addition, by the bottom-side electrodes 150 of configuration and the same potential of launch site 30 on the bottom surface of groove, semiconductor device exists
Played a role as field plate under cut-off state, depletion layer can be made to be extended well to drift region 10 from the bottom of groove.In addition, logical
The configuration bottom-side electrodes 150 on the bottom surface of groove are crossed, compared with the situation that gate electrode 50 is set in the entirety in groove, is further reduced
The feedback capacity of grid-inter-collector.In addition, in order to bottom-side electrodes 150 are electrically connected with launch site 30, being such as embedded in
Interlayer dielectric 70 in groove sets through hole, the through hole is filled with electric conductor film, by bottom-side electrodes 150 and emission electrode 90
Electrical connection.Through hole can both be located at least a portion of active region, it is also possible to (partly lead the end located at bottom-side electrodes 150
The outer circumferential side of body device).
In addition, in the semiconductor device shown in Fig. 1, preferably bottom-side electrodes are compared in the 1st of the lower section of gate electrode 50 apart from d1
The 1st of 150 lower section is long apart from d2.That is, the interval of gate electrode 50 and collecting zone 60 expands, thus, it is possible to further reduce grid
The feedback capacity of pole-inter-collector.
As described above, in the semiconductor device shown in Fig. 1, in the feedback capacity reduction that the bottom surface of groove produces.Its result
It is that can shorten the switch time of semiconductor device.
Also, it is the 1st more long apart from d2 than the 1st apart from d1 by making, as shown in Fig. 2 the end 51 of gate electrode 50 and bottom surface electricity
Corner 101 (bottom surface of groove and the border of side of the distance of the end 151 of pole 150 and the end 51 of gate electrode 50 and groove
Portion) distance expand.As a result, can suppress between the end 51 of gate electrode 50 and the end 151 of bottom-side electrodes 150
The generation of electric discharge and the generation of the electric discharge between the end 51 of gate electrode 50 and the corner 101 of groove.Therefore, shown in Fig. 1
Semiconductor device in, can make electrical characteristic stabilization.
Further, since by gate electrode 50 and the separate configuration of bottom-side electrodes 150, in the position away from these electrodes, the angle of groove
The pressure-resistant reduction in portion 101.In order to suppress the pressure-resistant reduction, preferably gate electrode 50 is configured in the vicinity in the corner 101 of groove.Cause
This, as shown in Fig. 2 it is preferred that the position of the lower surface of gate electrode 50 than the upper surface of bottom-side electrodes 150 position on the lower.
Also, as shown in Fig. 2 being preferably formed as following inner wall insulation film 40 so that configure in the region of the bottom surface of groove
It is thickness, thicker than configuring thickness in the side of groove and the region opposed with base 20.With following tendency：In broadening gate electrode
During 50 width, the parasitic capacitance produced between the gate electrode 50 and semiconductor regions in the bottom surface of groove increases.But, pass through
The thickness of inner wall insulation film 40 is thickeied in the bottom surface of groove, the parasitic capacitance can be reduced.
But, because the configuration of inner wall insulation film 40 plays a role in the region of the side of groove as gate insulating film, thus
It is limitary to thicken the thickness of inner wall insulation film 40 in the side of groove.Therefore, with the configuration of inner wall insulation film 40 in groove
The thickness in the region of side is compared, and the thickness by the configuration of inner wall insulation film 40 in the region of the bottom surface of groove thickeies.For example, will be interior
Thickness of the wall dielectric film 40 in the bottom surface of groove is set to about 300nm, and the thickness in the side of groove is set into about 150nm.
Inside is configured with the width W of the groove of gate electrode 50 in width to fixation degree, as described below, semiconductor
The conducting voltage reduction of device, and pressure-resistant raising.E.g., about 3 μm~20 μm of the width W of groove during such case.
First, the reasons why conducting voltage is reduced is illustrated.When semiconductor device is in the conduction state, channel region is being formed at
Raceway groove in by and from emission electrode 90 mainly along groove side movement electronics be injected into drift region 10.In groove
The thickness of the drift region 10 of the lower section of bottom surface is, for example, 30 μm~180 μm, and the width W compared to groove is sufficiently wide.Therefore, even groove
Width W when broadening, the electronics moved along groove is diffused in drift region 10 in the region than groove depth.Thus, not only groove it
Between region underface collecting zone 60 and the interface of drift region 10, and in the scope broader than its collecting zone 60 and drift
The interface for moving area 10 also turns into along biasing, and hole moves in drift region 10 from collecting zone 60.
The movement in the hole for being moved through coming from collecting zone 60 is subject to hindering for the bottom surface of groove, and hole is accumulated in the bottom surface of groove
In neighbouring drift region 10, and conductivity is produced to modulate.When the width W of groove is wider, the bottom surface for being likely to accumulate in groove is got in hole
In neighbouring drift region 10.Therefore, the hole moved to emission electrode 90 is reduced, conducting voltage reduction.
In addition, when the interval S of groove and groove is wider, causes that the lower section of base 20 can not be accumulated in and moved to base 20
The amount in hole increases or chip area increase.Therefore, in order to reduce conducting voltage, the preferably width W of groove is wider than interval S.
Below, illustrate by the width W of enlarged slot, the reasons why the pressure-resistant raising of semiconductor device.Make semiconductor device
When turning into cut-off state from conducting state, depletion layer extends not only from the PN junction with base 20 from the bottom periphery of groove
To in drift region 10.Now, the extended mode of preferably depletion layer is the same and expands to broader scope.Depletion layer extension not
In the case of uniform or narrow, pressure-resistant reduction.In the case where the width W of groove is narrower, as the corner of the groove of electric field concentration point
101 is relatively near each other, thus in the underface of the bottom surface of groove, and depletion layer has good uniformity and expands to scope wide.But,
In the case that the width W of groove is wider, the corner 101 of groove each other farther out, thus the bottom surface of groove between corner 101 underface
Depletion layer it is more uniform or expand to broader scope.Therefore, it is pressure-resistant in the width W of groove semiconductor devices wider
Improve.
Also, by making the interval S-phase of groove and groove to narrowing, the pressure-resistant raising of semiconductor device.This is based on following
Reason.That is, the depth as shallow of the depletion layer of the underface of the depth ratio groove of the depletion layer in region between groove.At interval, S is wider
When, the depletion layer extended with the PN junction of base 20 in the region between groove is further planarized.Therefore, the consumption of the bottom surface of groove
Layer turns into the part being connected with the depletion layer of the sideways expansion from groove further shape obtained from deformation to the greatest extent.Therefore, electric field collection
In depletion layer deformation part be groove corner 101 vicinity, pressure-resistant reduction.It is therefore preferable that interval S is narrow to certain journey
Degree, for example, make interval S narrower than the width W of groove.
As described above, in the semiconductor device shown in Fig. 1, the width W of preferably groove is wider, S is narrower at interval.For example, shape
Into following groove, in top view, the length of the long side direction that groove extends is more long than the width W of groove, and the width W of groove compares phase
Adjacent groove and the interval S of groove are wide.
In the case where the width W of groove is wider, with the increased tendency of feedback capacity between grid-colelctor electrode.But,
In the semiconductor device shown in Fig. 1, configured using the capacitance part of bottom-side electrodes 150 by the bottom surface of groove, grid can be reduced
Feedback capacity between pole-colelctor electrode.
Here, it is preferred that the width of bottom-side electrodes 150 is more than the thickness of bottom-side electrodes 150.Thereby, it is possible to suppress gate electrode 50
The part opposed with bottom-side electrodes 150, makes gate electrode 50 close to the corner 101 of groove.As a result, being capable of suppressor grid-transmitting
Electric capacity between pole, it is ensured that pressure-resistant.
However, because chip area is limitary, thus in the case where chip size fixation is set, in the width of enlarged slot
During degree W, raceway groove bar number is reduced.Now, when the shared ratio in the chip size of semiconductor device of channel region is decreased to necessarily
During degree, the saturation voltage increase between colelctor electrode-emitter stage.Therefore, in the electric conduction caused by the reduction of raceway groove bar number
When the effect of the rising of pressure by the width W of enlarged slot more than the effect that hole is accumulated and conducting voltage is reduced is made, semiconductor dress
The conducting voltage put rises.
Present inventors according to above-mentioned viewpoint studied as a result, it is preferred that the width W of groove is about 3 μm~20
μm.In addition, the width W of more preferably groove is about 5 μm~13 μm.According to the research of present inventors, groove width W about
In the case of for 7 μm, reduce most effectively conducting voltage.Because the depth of groove ordinarily be about 5 μm, thus by the width of groove
Spend that W expands as a result, producing the width W of the groove situations bigger than the depth of groove.
As described above, in the semiconductor device of implementation method of the present utility model, under gate electrode 50
Surface is to the bottom surface of groove the 1st apart from d1, more long apart from d2 than the 2nd of the bottom surface from the lower surface of bottom-side electrodes 150 to groove the.Cause
This, can further reduce the feedback capacity between grid-colelctor electrode.As a result, the switching speed of semiconductor device is improved.
Further, it is possible to suppress the generation of the electric discharge in the inside of semiconductor device.Therefore, electrical characteristic stabilization.In addition, passing through enlarged slot
Width W, high withstand voltage, the semiconductor device of low conducting voltage can be realized.
3~Figure 10 of reference picture illustrates the manufacture method of the semiconductor device of implementation method of the present utility model.Fig. 3~Figure 10
Illustrate comprising a region for groove.In addition, manufacture method described below is an example, can be become using it is included certainly
Shape example is realized in interior various manufacture methods in addition.
As shown in figure 3, using impurity diffusion method or epitaxial growth method in n-P is formed on the drift region 10 of type-The base of type
20, n-The drift region 10 of type is formed at p+The collecting zone 60 and n of type+On the layered product of the field termination area 65 of type.For example, utilizing
Impurity diffusion method is injected in drift region 10 n-type impurity from the upper surface of drift region 10, is then diffused by annealing,
Base 20 is set to be formed as substantially the same thickness.N-type impurity in base 20 is, for example, boron (B).Then, as shown in figure 4, example
N is such as formed selectively using a part for ion implanting and the upper surface for being diffused in base 20+The launch site 30 of type.
Then, extend and insertion launch site 30 and base 20, end from the upper surface of launch site 30 as shown in figure 5, being formed
Reach the groove 100 of drift region 10.Groove 100 can be formed using such as photoetching technique and etching technique.
Then, as shown in fig. 6, forming inner wall insulation film 40 on the internal face of groove 100.For example, using thermal oxidation method shape
Into silica (SiO2) as inner wall insulation film 40.The thickness of inner wall insulation film 40 e.g., about 100nm~300nm.
After inner wall insulation film 40 is formed, the polysilicon film 500 that with the addition of impurity is formed in entire surface.Thus, such as Fig. 7
It is shown, in the inside of groove 100, polysilicon film 500 is configured on inner wall insulation film 40.Now, as shown in fig. 7, the inside of groove 100
Do not filled by polysilicon film 500, polysilicon film 500 is formed along the wall of groove 100.
Then, as shown in figure 8, in the groove side for being formed with gate electrode 50 and the groove bottom for being formed with bottom-side electrodes 150
The surface of polysilicon film 500, mask 510 is formed using photoetching technique and etching technique etc..As shown in figure 8, being configured at groove side
Gap is provided between the mask 510a in face and the mask 510b for being formed at groove bottom.For example, mask 510a and mask 510b are used
Oxide-film etc..
Etching mask is etched by isotropic etching using the mask 510 shown in Fig. 8 to polysilicon film 500.
Now, using the etching mode entered from the gap of mask 510a and mask 510b, to the polysilicon configured in the corner of groove 100
Film 500 is etched.Thus, as shown in figure 9, forming gap between the lower surface and inner wall insulation film 40 of polysilicon film 500.
Processed more than, the gate electrode 50 that formation is made up of polysilicon film 500.Now, it is exhausted in the lower surface and inwall of gate electrode 50
Complete gap is not formed between velum 40, in the lower surface and the situation of the part contact of inner wall insulation film 40 of gate electrode 50
Under, the 1st is equal apart from d2 apart from d1 and the 2nd.Also, work as and formed between the lower surface and inner wall insulation film 40 of gate electrode 50
In the case of full gap, by the operation of Figure 10 below, gap is filled by interlayer dielectric 70, thus the 1st apart from d1 ratios
2nd is long apart from d2.
Also, the region covered by mask 510b of polysilicon film 500 residues in the bottom of groove 100 as bottom-side electrodes 150
Face.In the manufacture method, gate electrode 50 and bottom-side electrodes 150 are formed in same operation, the material of gate electrode 50 and
The material of bottom-side electrodes 150 is identical.
After mask 510 is removed, as shown in Figure 10, the interlayer dielectric 70 of landfill groove 100 is formed in entire surface.So
Afterwards, the emission electrode 90 that formation is connected with launch site 30 and base 20 on interlayer dielectric 70.For example, in interlayer dielectric 70
A part set opening portion, expose launch site 30 and the surface of base 20, formed fill the opening portion emission electrode 90.
In addition, forming collecting electrodes 80 on the back side of collecting zone 60, the semiconductor device shown in Fig. 1 is completed.
The manufacture method of the semiconductor device of implementation method of the present utility model from the description above, can make from grid electricity
The lower surface of pole 50 is to the bottom surface of groove 100 the 1st apart from d1, than the lower surface from bottom-side electrodes 150 to the bottom surface of groove 100
2 is long or same apart from d2.As a result, the electric capacity between grid-colelctor electrode can be reduced.In addition, can suppress
Electric discharge between the end 51 of gate electrode 50 and the end 151 of bottom-side electrodes 150 and in the end 51 of gate electrode 50 and groove
Electric discharge between corner 101.
In addition, making the Film Thickness Ratio in the bottom surface of groove in the thick inner wall insulation film 40 of the thickness of the side of groove, energy to be formed
Enough using following method etc..That is, the inwall in groove 100 is integrally formed oxide-film, then the oxide-film on etching removal side.
Then, oxide-film is formed again on the side of groove and on bottom surface.
In addition, illustrating to form gate electrode 50 and bottom-side electrodes 150 in same operation above exemplarily, making gate electrode
50 material and the material identical situation of bottom-side electrodes 150.But it is also possible to form the He of gate electrode 50 in different operations
Bottom-side electrodes 150.In this case, the material of the material of gate electrode 50 and bottom-side electrodes 150 can also be different.
, it is necessary in the lower section of gate electrode 50 seamlessly in the forming process of the interlayer dielectric 70 of the explanation of reference picture 10
Configuration interlayer dielectric 70.In order to seamlessly bury layer insulation in the corner surrounded by gate electrode 50 and bottom-side electrodes 150
Film 70, preferably interlayer dielectric 70 use the reflow material relatively soft when being formed higher.
For example, interlayer dielectric 70 is adapted to use bpsg film of phosphorus (P) containing high concentration etc..But, in gate electrode 50
In the case of using polysilicon film, when bpsg film and gate electrode 50 are contacted, phosphorus diffuses to gate electrode 50.As a result, grid are electric
The electric conductivity change of pole 50, the deterioration in characteristics of semiconductor device.
Therefore, in order that the electric conductivity of gate electrode 50 is constant, preferably as shown in figure 11, in gate electrode 50 and by bpsg film structure
Into the 1st interlayer dielectric 71 between configure the 2nd interlayer dielectric 72, as the diaphragm of the diffusion for preventing phosphorus.2nd interlayer is exhausted
Velum 72 uses the material of the electric conductivity for not influenceing gate electrode 50.For example, NSG films using TEOS etc. to be suitable for the 2nd interlayer exhausted
Velum 72.In addition, the 2nd interlayer dielectric 72 can also be formed as thinner than the 1st interlayer dielectric 71.By forming thicker interlayer
Dielectric film 71, can seamlessly fill in groove interlayer dielectric 70.
As described above, it is preferred to using by the 1st interlayer of material that is reflow higher but changing the electric conductivity of gate electrode 50
Dielectric film 71 and do not influence gate electrode 50 electric conductivity the interlayer dielectric 70 that is laminated of the 2nd interlayer dielectric 72.By
This, can seamlessly fill the inside of groove until corner, and prevent the characteristic of semiconductor device using interlayer dielectric 70
Deterioration.
Alternatively, it is also possible to by making the surface thermal oxide of gate electrode 50, as shown in figure 12, in the interlayer of gate electrode 50 and the 2nd
Heat oxide film 73 is configured between dielectric film 72.Using the heat oxide film 73 of fine and close and uniform film thickness, can more reliably prevent
Diffusion of the phosphorus from the 1st interlayer dielectric 71 being made up of bpsg film to gate electrode 50.
In addition, in order that interlayer dielectric 70 is easily accessible to corner, as shown in figure 11, making the lower surface shape of gate electrode 50
As connection gate electrode 50 the corner side of groove end, or grid in the side of bottom-side electrodes 150 of end and gate electrode 50
At least a portion missing of the lower surface of electrode 50.Also, wedge surface can also be formed in the lower surface of gate electrode 50 so that connection
Gate electrode 50 the corner side of groove end and gate electrode 50 the side of bottom-side electrodes 150 end.That is, by making gate electrode 50
Lower surface is shortened with the distance of the bottom surface of groove 100 with close to the side of groove 100, and interlayer dielectric 70 is easily accessible to angle
Portion.
Here, in the semiconductor device of Figure 11, from gate electrode 50 the lower surface of the corner side of groove end (gate electrode
50 the corner side of groove end) to the bottom surface of groove apart from d3, than from bottom-side electrodes 150 the side of gate electrode 50 lower surface to
The lower surface of groove it is long apart from d5.Also, (gate electrode 50 is the bottom of in the end of the lower surface of the side of bottom-side electrodes 150 for gate electrode 50
The end of the side of face electrode 150) it is located at than bottom-side electrodes 150 in the upper surface of the side of gate electrode 50 position high, gate electrode 50 is the bottom of at
The end of the lower surface of the side of face electrode 150 is located at than bottom-side electrodes 150 in the top position in the upper surface of the side of gate electrode 50.And
And, from gate electrode 50 the side of bottom-side electrodes 150 end to the bottom surface of groove apart from d4, than from bottom-side electrodes 150 in gate electrode
The upper surface of 50 sides is long apart from d6 to the bottom surface of groove.And, the lower surface of gate electrode 50 is formed as connection gate electrode 50 in groove
Corner side lower surface end and gate electrode 50 the side of bottom-side electrodes 150 end.In the lower surface of gate electrode 50 extremely
Few part missing, for example, be provided with wedge surface in the lower surface of gate electrode 50.In the semiconductor device of Figure 11, being capable of suppressor
Electric discharge of the electrode 50 between the end of the side of bottom-side electrodes 150 and bottom-side electrodes 150, reduces the feelings of semiconductor device malfunction
Condition.
Here, can also be as shown in the semiconductor device of Figure 17, from gate electrode 50 at the end of the lower surface of the corner side of groove
Portion to the bottom surface of groove apart from d3, and bottom-side electrodes 150 from the side opposed with gate electrode 50 lower surface to groove upper table
Face it is identical apart from d5.And, it is also lower surface of the gate electrode 50 in the side of bottom-side electrodes 150 in the semiconductor device of Figure 17
End be located at than bottom-side electrodes 150 in the top position in the upper surface of the side of gate electrode 50, be provided with the lower surface of gate electrode 50
Wedge surface so that from gate electrode 50 the side of bottom-side electrodes 150 lower surface to the bottom surface of groove apart from d4, than to bottom-side electrodes 150
Upper surface it is long apart from d6.Therefore, in the semiconductor device of Figure 17, it is also possible to reduce in the end of gate electrode and bottom surface electricity
Produced between the end of pole and discharged and the situation of malfunction.And, although semiconductor device of the feedback capacity than Figure 11 increases,
But the semiconductor device of Figure 17 is configured in the vicinity in the corner 101 of groove by by gate electrode 50, improve groove corner 101 it is attached
Near is pressure-resistant, thus is preferred mode.
Alternatively, it is also possible to as shown in figure 18, from gate electrode 50 the corner side of groove end to the bottom surface of groove apart from d3,
Than the bottom-side electrodes 150 from the side opposed with gate electrode 50 lower surface to the short apart from d5 of the bottom surface of groove.And, in Figure 18
Semiconductor device in, it is more top than the upper surface of bottom-side electrodes 150 that to be also gate electrode 50 be located in the end of the side of bottom-side electrodes 150
Position, be provided with wedge surface in the lower surface of gate electrode 50 so that from gate electrode 50 the side of bottom-side electrodes 150 end to the bottom of groove
Face apart from d4, it is more long apart from d6 than the bottom surface from the upper surface of bottom-side electrodes 150 to groove.In the semiconductor device of Figure 18,
Also the generation of the electric discharge between the end of gate electrode and the end of bottom-side electrodes can be suppressed, the situation of malfunction is reduced.
And, although semiconductor device of the feedback capacity than Figure 11 increases, but the semiconductor device of Figure 18 is configured by by gate electrode 50
In the vicinity in the corner 101 of groove, further improve the corner 101 of groove vicinity it is pressure-resistant, thus be preferred mode.
Alternatively, it is also possible to as shown in figure 11, bottom-side electrodes 150 are made to be formed as trapezoidal shape so that the following table of bottom-side electrodes 150
More than the upper surface of bottom-side electrodes 150, the thickness of bottom-side electrodes 150 is with thinning close to the side of groove 100 in face.Thus, layer
Between dielectric film 70 be also easily accessible to corner.
Also, as shown in figure 11, the lower surface and gate electrode 50 of bottom-side electrodes 150 are between the end of the corner side of groove
Distance, the distance between the end of the side of bottom-side electrodes 150 of upper surface and gate electrode 50 than bottom-side electrodes 150 is long.Thus, energy
The distortion of the electric field that the gap location enough made in gate electrode 50 and bottom-side electrodes 150 is produced is gentle.
In the case where the width W of groove 100 is expanded, in the top of groove 100, the upper surface generation of interlayer dielectric 70 is recessed
The narrower intervals on the top of hole, emission electrode 90 and gate electrode 50, it is possible to pressure-resistant reduction.Accordingly it is also possible to as shown in figure 11
The upper surface of gate electrode 50 is set to form wedge surface.Reduced with the central portion close to groove 100 by making the upper surface of gate electrode 50,
Can suppress due to the pressure-resistant reduction of the semiconductor device that gate electrode 50 and emission electrode 90 are approached and caused.
<Variation>
Figure 13 shows the variation of the semiconductor device of implementation method of the present utility model.In the semiconductor dress shown in Figure 13
In putting, the middle section of the thickness of inner wall insulation film 40 in the side away from groove is thicker than neighboring area in the side close to groove.
That is, the distance of the bottom surface from the lower surface of bottom-side electrodes 150 to groove, in middle section than in the neighboring area of bottom-side electrodes 150
It is long.Therefore, it is possible to the electric capacity between the emitter stage-colelctor electrode for reducing semiconductor device.
(other embodiment)
The utility model is described using implementation method as described above, but should not be construed the one of composition present disclosure
Partial narration and accompanying drawing is of the present utility model for limiting.It is clear that those skilled in the art can be from the disclosure
Appearance expects alternate embodiments miscellaneous, embodiment and application technology.
Semiconductor device illustrated above is the example of IGBT.But, semiconductor device can also use trench gate
Other construction switch elements.Figure 14 shows that semiconductor device is of the MOSFET of trench gate.Shown in Figure 14 half
Conductor device is the MOSFET of the construction in the drain region 160 that lower surface in drift region 10 is configured with N-shaped.In the following table in drain region 160
Face is configured with the drain electrode 180 electrically connected with drain region 160.
Even the semiconductor device of the MOSFET shown in Figure 14, by making from the lower surface of gate electrode 50 to the bottom surface of groove
The 1st apart from d1, more long apart from d2 than the 2nd of the bottom surface from the lower surface of bottom-side electrodes 150 to groove the, it is also possible to reduce grid-leakage
Feedback capacity between pole.As a result, the switching speed of semiconductor device is improved.Even in addition, trench gate
MOSFET, it is also possible to make interlayer dielectric 70 be formed as the 1st interlayer dielectric 71 and the 2nd interlayer dielectric 72 shown in Figure 11
The construction being laminated.Therefore, it is possible to seamlessly fill the inside of groove until corner using interlayer dielectric 70, and prevent
The deterioration of the characteristic of semiconductor device.
In addition, being shown in the semiconductor device of Fig. 1 in the entire surface of the lower surface of gate electrode 50, being made from gate electrode 50
Lower surface to the distance of the distance than the bottom surface from the lower surface of bottom-side electrodes 150 to groove of the bottom surface of groove situation.But,
In a part for the lower surface of gate electrode 50, make from gate electrode 50 the side of bottom-side electrodes 150 lower surface to the bottom surface of groove
Distance, than the bottom-side electrodes 150 from the side opposed with gate electrode 50 lower surface to the bottom surface of groove distance.In addition,
The position of the side in groove of gate electrode 50 is set to, the upper surface of side than bottom-side electrodes 150 is extended to
Position is on the lower and roughly the same with the position of the lower surface of the side of bottom-side electrodes 150.In this case, it is also possible to
Reduce the feedback capacity between gate-to-drain.Can also be as the semiconductor device of Figure 16~Figure 18, not in the He of gate electrode 50
2nd interlayer dielectric 72/ and heat oxide film 73 being set between the 1st interlayer dielectric 71 be made up of bpsg film used as preventing phosphorus
The diaphragm of diffusion.
For example, in the semiconductor device shown in Figure 15, the 2nd interlayer dielectric 72/ and heat oxide film 73 are not provided with, by
1 interlayer dielectric 71 forms interlayer dielectric 70.Wherein, the end of the bottom-side electrodes side of gate electrode 50 exists than bottom-side electrodes 150
The upper surface of the side of gate electrode 50 is top, from a part (end of the gate electrode 50 in the side of bottom-side electrodes 150 of the lower surface of gate electrode 50
Portion) to groove bottom surface apart from d4, it is more long apart from d6 than the bottom surface from the upper surface of bottom-side electrodes 150 to groove.Also, from grid electricity
Another part (end of the gate electrode 50 in the corner side of groove) of the lower surface of pole 50 to the bottom surface of groove apart from d3, and from bottom surface
The lower surface of electrode 150 is identical apart from d5 to the bottom surface of groove.In the semiconductor device shown in Figure 15, can reduce grid-
Feedback capacity between drain electrode.Further, it is possible to improve in the pressure-resistant of the corner of groove.And, can reduce at the end of gate electrode 50
Produced between the end of portion and bottom-side electrodes 150 and discharged and the situation of malfunction.
In addition, can also be in the semiconductor device shown in Figure 15, from another part (grid of the lower surface of gate electrode 50
End of the electrode 50 in the corner side of groove) to groove bottom surface apart from d3, than from the lower surface of bottom-side electrodes 150 to the bottom surface of groove
It is long apart from d5.Feedback capacity between can also reducing gate-to-drain in the semiconductor device.Further, it is possible to reduce
Produced between the end of gate electrode 50 and the end of bottom-side electrodes 150 and discharged and the situation of malfunction.
In addition, can also be in the semiconductor device shown in Figure 15, from another part (grid of the lower surface of gate electrode 50
End of the electrode 50 in the corner side of groove) to groove bottom surface apart from d3, than from the lower surface of bottom-side electrodes 150 to the bottom surface of groove
It is short apart from d5.In the semiconductor device, it is also possible to reduce between the end of the end of gate electrode 50 and bottom-side electrodes 150
Produce and discharge and the situation of malfunction.Further, it is possible to further improve in the pressure-resistant of the corner of groove.And, by making grid electricity
Pole 50 is located at the position of the adjacent corner until groove, can further relax the electric field of the adjacent corner of groove.
Also, in the semiconductor device of Figure 16~Figure 18, wedge surface is set in the lower surface of gate electrode 50, but it is also possible to no
Wedge surface is set in the lower surface of gate electrode 50, and makes gate electrode 50 in the height and gate electrode of the lower surface of the side of bottom-side electrodes 150
50 the corner side of groove bottom surface it is highly identical.Also, in the semiconductor device of Figure 16~Figure 18, it is also possible to make gate electrode
50 height in the upper surface of the height than bottom-side electrodes 150 of the end of the side of bottom-side electrodes 150 is low.In above-mentioned semiconductor device
In, diffusion of the phosphorus from the 1st interlayer dielectric 71 being made up of bpsg film to gate electrode 50 can be more reliably prevented from.
Also, in the semiconductor device of Figure 16~Figure 18, it is also possible to which adaptation is not provided with bottom-side electrodes 150 and uses known
Trench gate other construction switch elements.In above-mentioned semiconductor device, can be more reliably prevented from phosphorus from by
Bpsg film constitute diffusion from the 1st interlayer dielectric 71 to gate electrode 50.
Also, bottom-side electrodes 150 are set to trapezoidal shape in fig. 11 so that the thickness of bottom-side electrodes 150 is with close to groove
100 side and it is thinning, i.e., the width of the upper surface of bottom-side electrodes 150 less than bottom-side electrodes 150 lower surface width.But
It is, it is also possible to which bottom-side electrodes 150 are set to trapezoidal shape as shown in figure 16 so that the thickness of bottom-side electrodes 150 is with close to groove
100 side and it is thickening.Thus, it is sandwiched in the layer insulation between bottom-side electrodes 150 and gate electrode 50 and inner wall insulation film 40
The part of film 70 is good with the stickiness of bottom-side electrodes 150 and gate electrode 50, in the transmitting being welded on interlayer dielectric 70
During electrode 90, can suppress to produce skew in interlayer dielectric 70.
In addition, the semiconductor device of Figure 16 changes bottom-side electrodes 150 compared with the semiconductor device of Figure 11, otherwise in figure
In the semiconductor device of 17 or Figure 18, it is also possible to ladder being replaced into the bottom-side electrodes 150 of the semiconductor device such as Figure 11
The width of the bottom-side electrodes 150 of shape, the i.e. width of the upper surface of bottom-side electrodes 150 less than the lower surface of bottom-side electrodes 150.
In this case, the lower surface of gate electrode 50 and the distance of bottom-side electrodes 150, thus energy can in a thickness direction be substantially ensured that
Enough electric discharges suppressed well between gate electrode 50 and bottom-side electrodes 150.
In addition, illustratively illustrate that semiconductor device is the situation of n-channel type, but when semiconductor device is p-channel type,
Obviously effect of the present utility model can also be obtained.
So, the utility model is certainly comprising various implementation methods described not herein etc..Therefore, it is of the present utility model
Technical scope can only be utilized and determined according to the specific item of relevant utility model that above-mentioned explanation is appropriate claims.
Claims (16)
1. a kind of semiconductor device, it is characterised in that the semiconductor device has：
1st semiconductor regions of the 1st conductivity type；
2nd semiconductor regions of the 2nd conductivity type, its configuration is on the 1st semiconductor regions；
3rd semiconductor regions of the 1st conductivity type, its configuration is on the 2nd semiconductor regions；
Inner wall insulation film, it configures the inwall in groove, and the groove extends described in simultaneously insertion from the upper surface of the 3rd semiconductor regions
3rd semiconductor regions and the 2nd semiconductor regions；
Coordination electrode, it is exhausted that it is opposed to the inwall of the configuration in the side of the groove with the side of the 2nd semiconductor regions
On velum；And
Interlayer dielectric in the coordination electrode,
The coordination electrode is made up of polysilicon film,
The interlayer dielectric has：
1st interlayer dielectric, the material of the 1st interlayer dielectric makes the coordination electrode when being contacted with the coordination electrode
Electric conductivity changes；And
2nd interlayer dielectric, its configuration is between the coordination electrode and the 1st interlayer dielectric so that the control electricity
The electric conductivity of pole is constant.
2. semiconductor device according to claim 1, it is characterised in that
The semiconductor device also has bottom-side electrodes, and the bottom-side electrodes are configured described with the coordination electrode insulated separation
On the inner wall insulation film of the bottom surface of groove,
The interlayer dielectric will insulate between the coordination electrode and the bottom-side electrodes.
3. semiconductor device according to claim 2, it is characterised in that
1st interlayer dielectric is made up of bpsg film, and the 2nd interlayer dielectric is made up of NSG films.
4. the semiconductor device according to Claims 2 or 3, it is characterised in that
The semiconductor device also has heat oxide film of the configuration between the 2nd interlayer dielectric and the coordination electrode.
5. a kind of semiconductor device, it is characterised in that the semiconductor device has：
1st semiconductor regions of the 1st conductivity type；
2nd semiconductor regions of the 2nd conductivity type, its configuration is on the 1st semiconductor regions；
3rd semiconductor regions of the 1st conductivity type, its configuration is on the 2nd semiconductor regions；
Inner wall insulation film, it configures the inwall in groove, and the groove extends described in simultaneously insertion from the upper surface of the 3rd semiconductor regions
3rd semiconductor regions and the 2nd semiconductor regions；
Coordination electrode, it is exhausted that it is opposed to the inwall of the configuration in the side of the groove with the side of the 2nd semiconductor regions
On velum, it is made up of polysilicon film；
Bottom-side electrodes, it is configured on the inner wall insulation film of the bottom surface of the groove with the coordination electrode insulated separation；
1st interlayer dielectric, its landfill is made up of, by the coordination electrode and the bottom surface in the inside of the groove bpsg film
Insulated between electrode；And
2nd interlayer dielectric, its configuration suppresses the diffusion of phosphorus between the coordination electrode and the 1st interlayer dielectric,
From at least a portion of the lower surface of the coordination electrode to the distance of the bottom surface of the groove, than from bottom surface electricity
Distance of at least a portion of the lower surface of pole to the bottom surface of the groove.
6. semiconductor device according to claim 5, it is characterised in that
2nd interlayer dielectric is made up of NSG films.
7. the semiconductor device according to claim 5 or 6, it is characterised in that
The semiconductor device also has heat oxide film of the configuration between the 2nd interlayer dielectric and the coordination electrode.
8. the semiconductor device according to claim 5 or 6, it is characterised in that
The position of the upper surface of the position than the bottom-side electrodes of the lower surface of the coordination electrode is on the lower.
9. the semiconductor device according to claim 5 or 6, it is characterised in that
The lower surface of the coordination electrode is formed as wedge surface as follows：The lower surface of the coordination electrode and institute
The distance between described bottom surface of groove is stated to be shortened with the side close to the groove.
10. the semiconductor device according to claim 5 or 6, it is characterised in that
The bottom-side electrodes are following trapezoidal shape：The thickness of the bottom-side electrodes becomes with the side close to the groove
It is thin.
11. semiconductor device according to claim 5 or 6, it is characterised in that
The distance of the bottom surface from the lower surface of the bottom-side electrodes to the groove the bottom-side electrodes it is described under
It is long in neighboring area in middle section ratio in surface.
12. semiconductor device according to claim 5 or 6, it is characterised in that
In top view, the length on the bearing of trend of the groove is more long than the width of the groove, and the groove width ratio
The interval of the adjacent groove is wide.
13. semiconductor device according to claim 5 or 6, it is characterised in that
The thickness of the inner wall insulation film is in the region of the bottom surface of the groove is configured in, than being configured in the groove
The region of the side is thick.
14. semiconductor device according to claim 5 or 6, it is characterised in that
In the entire surface of the lower surface of the coordination electrode, from the lower surface of the coordination electrode to the groove
The distance of the bottom surface, the distance than the bottom surface from the lower surface of the bottom-side electrodes to the groove.
15. semiconductor device according to claim 5 or 6, it is characterised in that
From a part for the bottom-side electrodes side of the lower surface of the coordination electrode to the bottom surface of the groove away from
From, than the distance of the bottom surface from the lower surface of the bottom-side electrodes to the groove, from the institute of the coordination electrode
The distance of the another part to the bottom surface of the groove and the lower surface from the bottom-side electrodes of lower surface are stated to described
The distance of the bottom surface of groove is identical.
16. semiconductor device according to claim 5 or 6, it is characterised in that
The position of the side at least opposed with the bottom-side electrodes of the lower surface of the coordination electrode, than bottom surface electricity
The position of the upper surface of the coordination electrode side of pole is upper.
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