JP4491307B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP4491307B2
JP4491307B2 JP2004273095A JP2004273095A JP4491307B2 JP 4491307 B2 JP4491307 B2 JP 4491307B2 JP 2004273095 A JP2004273095 A JP 2004273095A JP 2004273095 A JP2004273095 A JP 2004273095A JP 4491307 B2 JP4491307 B2 JP 4491307B2
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trench
semiconductor device
located
floating
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JP2006093193A (en
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康嗣 大倉
規仁 戸倉
公守 濱田
秀史 高谷
晃 黒柳
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トヨタ自動車株式会社
株式会社デンソー
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623Buried supplementary region, e.g. buried guard ring
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01BASIC ELECTRIC ELEMENTS
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor device that achieves both high breakdown voltage and low on-resistance by relaxing electric field concentration on a semiconductor layer, and a method for manufacturing the same.

  Conventionally, a trench gate type semiconductor device having a trench gate structure has been proposed as a semiconductor device for power devices. In this semiconductor device, there is generally a trade-off relationship between high breakdown voltage and low on-resistance.

As a semiconductor device focusing on this point, for example, there is one disclosed in Patent Document 1. This semiconductor device is schematically configured as shown in FIG. That is, an N + source region 31 is provided on the upper surface side in FIG. 19, and an N + drain region 11 is provided on the lower side. Between them, a P body region 41 and an N drift region 12 are provided from the upper surface side. Further, a trench 21 formed by digging a part of the upper surface side of the semiconductor device is provided. In addition, a gate electrode 22 is built in the trench 21. A P floating region 59 is provided at a position away from the trench 21. The gate electrode 22 is insulated from the P body region 41 by a gate insulating film 24 formed on the wall surface of the trench 21.

In this semiconductor device 900, by providing the P floating region 59 in the N drift region 12, an increase in the electric field peak can be suppressed. And, it is said that a high breakdown voltage can be achieved by reducing the maximum peak value. Further, since the withstand voltage is high, the on-resistance can be lowered by increasing the impurity concentration of the N drift region 12.

As another semiconductor device, for example, there is one described in Patent Document 2. In this semiconductor device, impurity regions are formed in a sandwich shape in the width direction in the order of pnpn. Such a structure is called a super-junction structure, and makes it possible to completely deplete the drift region when the gate voltage is switched off. Therefore, the impurity concentration can be made higher than that of the conventional structure, and the on-resistance can be reduced.
JP-A-9-191109 JP 2003-273355 A

However, the conventional semiconductor device described above has the following problems. The semiconductor device disclosed in Patent Document 1 is manufactured by the following procedure. First, an N type silicon layer to be an N type drift region 12 is formed on an N + substrate to be an N + drain region 11 by epitaxial growth. At this time, the N type silicon layer is formed up to the position of Z in FIG. Next, a P floating region 59 is formed by ion implantation or the like. Next, epitaxial growth is performed again to form the remaining N type silicon layer. As a result, a semiconductor device in which the P floating region 59 is completely surrounded by the N drift region 12 is formed.

That is, when forming the P floating region 59 completely surrounded by the N drift region 12, at least two N type silicon layer forming steps (epitaxial growth steps) are required, which is extremely difficult to manufacture. It takes time and effort. Furthermore, in a multi-stage the P floating region, N - other processes forming type silicon layer, it is necessary to repeat the ion implantation process, a thermal diffusion process or the like, increase in the number of steps is remarkable.

Therefore, the present applicant has proposed an insulated gate semiconductor device 910 as shown in FIG. 20 (Japanese Patent Application No. 2003-375098). In this insulated gate semiconductor device 910, ions are embedded from the bottom of the trench after the N type silicon layer is formed. Thus, it can be formed by a single N -type silicon layer forming process, and the problem of Patent Document 1 is solved in that the manufacturing procedure is simple. However, when the P floating region is multi-staged, the size of the P floating region 52 located between the bottom of the trench 21 and the P body region 41 is significantly smaller than the size of the P floating region 51 as shown in FIG. . For this reason, the pressure holding function cannot be fully exhibited.

  In addition, a semiconductor device having a super junction structure such as the semiconductor device disclosed in Patent Document 2 is very laborious to manufacture. That is, it is necessary to repeat epitaxial growth, impurity implantation, trench formation, and the like, and the number of processes becomes very large.

  Furthermore, in order to achieve a high breakdown voltage, it is necessary to narrow the pitch of the diffusion layer, but it is difficult to set the pitch to 20 μm or less at present. This is because it is difficult to finely control the size of the diffusion layer because a process with a high thermal load such as an epitaxial growth process is repeatedly performed.

  In addition, a technique for forming a diffusion layer by reducing the number of epitaxial growth steps by performing ion implantation from an oblique direction after forming a trench is disclosed. That is, a technique capable of manufacturing a semiconductor device having a super junction structure while suppressing a thermal load is disclosed (for example, Japanese Patent Application Laid-Open No. 2003-101022). However, when ion implantation is performed from an oblique direction, the ion arrival depth is determined by the opening width and implantation angle of the trench. However, if the tilt angle is small and close to the sidewall of the trench, the oxide film on the sidewall can be passed. It becomes difficult, and high concentration impurity implantation cannot be performed on the sidewall of the trench. In addition, when the trench is deep, the implantation angle is limited, and reflection occurs at a slight angle shift, so that stability when implanting impurities at a desired position is lacking. For this reason, the impurities cannot be embedded accurately in a deep place. On the other hand, it is necessary to deepen the diffusion layer in order to ensure high breakdown voltage. Therefore, it is not possible to sufficiently increase the breakdown voltage.

  The present invention has been made to solve at least one of the problems of the conventional semiconductor device described above. That is, an object of the present invention is to provide a semiconductor device and a manufacturing method thereof that can be easily manufactured while achieving both high breakdown voltage and low on-resistance.

A semiconductor device for solving this problem includes a drift region that is a first conductivity type semiconductor located on a main surface side of a semiconductor substrate, and a body region that is a second conductivity type semiconductor located on an upper surface side of the drift region. The semiconductor device includes: a first floating region that is surrounded by a drift region, at least partially located below the body region, and is a second conductivity type semiconductor; and an upper surface of the semiconductor substrate. , Penetrating through the body region and having a bottom portion surrounded by the drift region and a first trench portion located in the first floating region, located below the first floating region, and not in contact with the first floating region, An opening is provided at the bottom of the second floating region which is the second conductivity type semiconductor and the first trench portion, and the bottom is within the second floating region. A first insulating layer formed on the first insulating layer, and a gate electrode located on the first insulating layer and facing the body region. The deposited insulating layer fills the second trench portion with an insulator, and the upper end of the deposited insulating layer is located below the lower end of the body region and above the upper end of the first floating region. It is characterized by this.

That is, the semiconductor device of the present invention has the first floating region surrounded by the drift region below the body region. A second floating region surrounded by the drift region is provided below the first floating region. That is, the first floating region and the second floating region are arranged side by side in the vertical direction (thickness direction) of the semiconductor substrate. In addition, since the second trench portion has a part of the bottom of the first trench portion as an opening, the first trench portion and the second trench portion are integrated to form a stepped trench portion.

In the semiconductor device of the present invention , the first floating region and the second floating region can be formed at the same time by burying impurities from the vertical direction with respect to the semiconductor substrate in which the stepped trench portion is formed. That is, a multi-layer floating region can be formed in the thickness direction of the semiconductor substrate with a few steps. Further, since the first floating region and the second floating region can be formed at a time by one thermal diffusion treatment, the thermal load on the semiconductor substrate is small, and the controllability of the size of each floating region is good.

In the semiconductor device of the present invention , a step is provided between the first trench portion and the second trench portion, and a floating region also exists below the step portion. Therefore, the size of the first P floating region located in the middle between the second floating portion and the body region is larger than that of the conventional form in which no step is provided (see FIG. 21). Therefore, the withstand voltage holding function can be sufficiently exhibited.

In addition, the semiconductor device manufacturing method of the present invention includes a drift region that is a first conductivity type semiconductor located on a main surface side of a semiconductor substrate, and a body region that is a second conductivity type semiconductor located on an upper surface side of the drift region. A method for manufacturing a semiconductor device, comprising: a mask forming step for forming a mask material on an upper surface of a semiconductor substrate; a first patterning step for patterning the mask material with a first groove width; and a first patterning step. After the first trench portion forming step of forming a trench portion by digging a part of the semiconductor substrate in the thickness direction, and after the first trench portion forming step, the groove width of the mask material is changed to the first groove width. After the second patterning step for widening the width of the second groove and the second patterning step, a part of the semiconductor substrate is dug down in the thickness direction so that the stepped portion is drifted. A second trench portion forming step for forming a trench portion positioned in the region, and an impurity for injecting impurities from the thickness direction of the semiconductor substrate into the stepped trench portion formed in the second trench portion forming step A thermal diffusion process is performed after the implantation step and the impurity implantation step, so that the first floating region that is the second conductivity type semiconductor and the bottom portion of the trench portion are located at the step portion of the trench portion, A floating region forming step for forming a floating region which is non-contact with the floating region and forms a second floating region which is a second conductivity type semiconductor, and a stepped trench formed in the second trench portion forming step The portion is filled with an insulating material to form a deposited insulating layer, the upper end of the deposited insulating layer is located below the lower end of the body region, and the first float Removing a portion of the deposited insulating layer so as to be positioned above the upper end of the region, is characterized by comprising a gate electrode forming step of forming a gate electrode facing the body region to the deposited insulating layer .

  According to the present invention, the impurity region can be formed by one epitaxial growth process. Further, by providing the step-shaped trench, at least two impurity diffusion layers can be simultaneously formed by one thermal diffusion treatment. Therefore, the process is simple and the heat load is small. In addition, since the thermal load is small, the size of the impurity diffusion layer can be finely controlled. Therefore, the pitch in the width direction of impurity regions of the same conductivity type can be reduced. Therefore, a semiconductor device and a manufacturing method thereof that can be easily manufactured while achieving both high breakdown voltage and low on-resistance have been realized.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will be described below in detail with reference to the accompanying drawings. In the present embodiment, the present invention is applied to a power MOS that controls conduction between a drain and a source (hereinafter referred to as “between DS”) by applying a voltage to an insulated gate.

[First embodiment]
The semiconductor device 100 according to the first embodiment has a structure shown in the sectional view of FIG. In FIG. 1, components having the same symbols as those of the conventional semiconductor device shown in FIG. 19 have the same functions as those components. In this specification, the whole of the starting substrate and the single crystal silicon portion formed by epitaxial growth on the starting substrate is referred to as a semiconductor substrate.

In the semiconductor device 100, an N + source region 31 and a contact P + region 32 formed at a high concentration for reducing contact resistance are provided on the upper surface side in FIG. On the other hand, an N + drain region 11 is provided on the lower surface side. Between them, a P body region 41 and an N drift region 12 are provided from the upper surface side. The total thickness of the P body region 41 and the N drift region 12 (hereinafter referred to as “epitaxial layer”) is approximately 6.5 μm (of which the thickness of the P body region 41 is approximately 1.2 μm).

Further, a step-shaped gate trench is formed by digging a part of the upper surface side of the semiconductor substrate. Specifically, the upper trench 21 having a wide opening and the lower trench 25 having a narrow opening constitute an integrated gate trench. That is, the lower trench 25 has an opening at a part of the bottom of the upper trench 21. Upper trench 21 has a depth of approximately 2.5 μm and penetrates P body region 41. The position of the bottom of the lower trench 25 is approximately 4.0 μm from the upper surface of the semiconductor substrate. The width of the opening of the upper trench 21 is approximately 0.8 μm, and the width of the opening of the lower trench 25 is approximately 0.4 μm.

The lower trench 25 is filled with a deposited insulating layer 23 formed by depositing an insulator (for example, silicon oxide). Further, a part of the upper trench 21 is filled with the deposited insulating layer 23. In the upper trench 21, a gate electrode 22 is formed on the deposited insulating layer 23 by depositing a conductor (for example, polysilicon). The lower end of the gate electrode 22 is located below the lower surface of the P body region 41, and specifically, is located at a depth of about 1.3 μm from the upper surface of the semiconductor substrate. The gate electrode 22 faces the N + source region 31 and the P body region 41 of the semiconductor substrate via the gate insulating film 24 formed on the wall surface of the upper trench 21. That is, the gate electrode 22 is insulated from the N + source region 31 and the P body region 41 by the gate insulating film 24.

In the semiconductor device 100 having such a structure, a channel effect is generated in the P body region 41 by applying a voltage to the gate electrode 22, thereby controlling conduction between the N + source region 31 and the N drift region 12. is doing.

Further, in the semiconductor device 100, a P floating region 51 and a P floating region 52 surrounded by the N drift region 12 are formed. The cross sections of the P floating region 51 and the P floating region 52 are substantially circular as shown in the cross sectional view of FIG. The P floating area 51 is located below the P floating area 52. The bottom of the lower trench 25 is located in the P floating region 51, and the bottom of the upper trench 21 (the step portion of the stepped trench) is located in the P floating region 52.

  The dimension of the bottom of the upper trench 21 and the dimension of the bottom of the lower trench 25 are determined so that the peak of the electric field is uniform when the gate voltage is switched off in consideration of the size of the P floating region including each bottom.

  Each upper trench 21 is formed at a pitch of about 3.0 μm. Further, a sufficient space (current path) is secured between the adjacent P floating regions 52 and 52. Therefore, in the ON state, the presence of the P floating region 52 does not hinder the drain current. The upper end of the deposited insulating layer 23 is located above the upper end of the P floating region 52. Therefore, the gate electrode 22 deposited on the deposited insulating layer 23 and the P floating region 52 do not face each other.

The semiconductor device 100 according to the present embodiment is provided with P floating regions 51 and 52 below the upper trench 21 in which the gate electrode 22 is embedded. It has the following characteristics. That is, when the gate voltage is switched off, a depletion layer is formed in the N drift region 12 from the PN junction with the P body region 41 due to the voltage between DS. And the vicinity of the PN junction location becomes a peak of electric field strength. When the tip of the depletion layer reaches the P floating region 52, the P floating region 52 enters a punch-through state, and its potential is fixed.

Further, when the applied voltage between the DSs is high, a depletion layer is also formed from the lower end of the P floating region 52. In addition to the PN junction between the P body region 41 and the vicinity of the lower end portion of the P floating region 52, the electric field strength peaks. That is, electric field peaks can be formed at two locations, and the maximum peak value can be reduced.

When the applied voltage between the DSs is higher, a depletion layer is formed from the lower end of the P floating region 52, and the depletion layer reaches the P floating region 51. For this reason, the electric field strength also peaks at the lower end of the P floating region 51. Therefore, electric field peaks can be formed at three locations, and the maximum peak value can be further reduced. Therefore, high breakdown voltage can be achieved. Further, since the withstand voltage is high, the on-resistance can be lowered by increasing the impurity concentration of the N drift region 12.

The number of electric field peak points can be increased as the number of P floating regions located between the P floating region 51 and the P body region 41 is increased. Therefore, the higher the number of P floating regions, the higher the breakdown voltage and the lower the on-resistance. FIG. 2 shows a semiconductor device 110 in which two layers of P floating regions 52 and 53 are provided between the P floating region 51 and the P body region 41. That is, the semiconductor device 110 has a three-layer P floating region. Specifically, it has a P floating region 52 including the bottom of the upper trench 21, a P floating region 53 including the bottom of the middle trench 26, and a P floating region 51 including the bottom of the lower trench 25. Yes. In the semiconductor device 110, electric field peaks can be formed at four locations, and the maximum peak value can be further reduced.

Next, a manufacturing process of the semiconductor device 100 shown in FIG. 1 will be described with reference to FIGS. First, an N type silicon layer is formed on the N + substrate to be the N + drain region 11 by epitaxial growth. This N -type silicon layer (epitaxial layer) is a portion that becomes each of the N drift region 12, the contact P + region 32, and the N + source region 31. Then, a P body region 41 and an N + source region 31 are formed by subsequent ion implantation or the like. As a result, a semiconductor substrate having an epitaxial layer on the N + drain region 11 is produced as shown in FIG.

  Next, a hard mask 91 such as HTO (High Temperatuer Oxide) is formed on the semiconductor substrate, and a resist 92 is formed on the hard mask 91. Then, patterning is performed with a groove width equivalent to the width of the lower trench 25 as shown in FIG. That is, patterning of a portion corresponding to the lower trench 25 is performed. Next, after performing mask dry etching, trench dry etching is performed as shown in FIG. The intermediate trench 29 is formed by this dry etching. The width of the intermediate trench 29 is equal to the width of the lower trench 25. The depth of the intermediate trench 29 (the length from the upper surface of the semiconductor substrate to the bottom of the intermediate trench 29) is the depth of the lower trench 25 (from the opening of the lower trench 25 (the bottom of the upper trench 21) to the bottom thereof. Is equivalent to the length).

  Next, as shown in FIG. 3D, a pattern corresponding to the upper trench 21 is patterned. That is, the groove width of the hard mask 91 is increased until it becomes equal to the width of the upper trench 21. Next, after performing mask dry etching, trench dry etching is performed again as shown in FIG. By this dry etching, a part of the semiconductor substrate is dug down uniformly in the thickness direction, and the upper trench 21 and the lower trench 25 are formed simultaneously. That is, a stepped gate trench is formed. After performing trench dry etching, unnecessary hard mask 91 and resist 92 are removed.

  Next, a sacrificial oxide film 93 having a thickness of about 30 nm is formed on the wall surfaces of the upper trench 21 and the lower trench 25 by performing a thermal oxidation process. The sacrificial oxide film 93 is used to prevent ion implantation from being performed on the side walls of each trench.

  Next, as shown in FIG. 4F, impurity ions are implanted from the bottom of each trench. Thereafter, by performing thermal diffusion processing, P floating regions 51 and 52 are formed as shown in FIG. That is, two layers of P floating regions can be formed simultaneously by one thermal diffusion process. Thereafter, the sacrificial oxide film 93 is removed by wet etching. Thereby, the damaged layer by dry etching in FIG. 3E is removed.

  Next, the wall surface of each trench is smoothed by using an isotropic etching method such as CDE (Chemical Dry Etching), and then a thermal oxide film 94 having a thickness of about 50 nm is formed. This thermal oxide film 94 improves the embedding property of an insulating film, which will be described later, and can eliminate the influence of the interface state. If the silicon surface is exposed and the insulator is more embedded, the thermal oxide film 94 need not be formed.

  Next, as shown in FIG. 4H, an insulating film 23 is deposited in the upper trench 21 and the lower trench 25 by a CVD (Chemical Vapor Deposition) method. Specifically, as the insulating film (deposited insulating layer) 23, silicon oxide formed by, for example, a low pressure CVD method using TEOS (Tetra-Ethyl-Orso-Silicate) as a raw material or a CVD method using ozone and TEOS as raw materials. Applicable to membranes.

Next, dry etching is performed on the deposited insulating layer 23 as shown in FIG. Thereby, a part of the deposited insulating layer 23 is removed (etched back), and a space for forming the gate electrode 22 is secured. Thereafter, annealing is performed in an oxidizing atmosphere. Specifically, for example, an oxidation annealing process is performed for about 20 minutes at a temperature in the range of 900 ° C. to 1000 ° C. in an atmosphere of a mixed gas of H 2 and O 2 . By this annealing treatment, the deposited insulating layer 23 is densified. Further, since annealing is performed in an oxidizing atmosphere, a thermal oxide film 95 having a thickness of about 50 nm is formed along the silicon surface as shown in FIG. Examples of the oxidation annealing method include a hydrogen combustion oxidation method and a dry oxidation method.

  Next, a cleaning process is performed on the surface of the semiconductor substrate. Specifically, wet etching using a hydrofluoric acid chemical solution (for example, buffered hydrofluoric acid) is performed. By this cleaning process, as shown in FIG. 5 (k), the thermal oxide film 95 formed on the surface of the semiconductor substrate by the oxidation annealing process and the surface layer portion of the deposited insulating layer 23 are removed. As a result, deposits and damage layers generated on the wall surface of the gate trench 21 by etch back are removed together with the thermal oxide film 95.

Next, thermal oxidation treatment is performed to form a thermal oxide film 24 having a thickness of about 100 nm on the silicon surface as shown in FIG. This thermal oxide film 24 becomes the gate oxide film 24 in FIG. Specifically, thermal oxidation treatment is performed at a temperature in the range of 900 ° C. to 1100 ° C. in an atmosphere of a mixed gas of H 2 and O 2 .

Next, a gate material 22 is deposited in the space secured by etch back as shown in FIG. Specifically, the film formation conditions for the gate material 22 include, for example, a reactive gas mixed gas containing SiH 4 , a film formation temperature of 580 ° C. to 640 ° C., and a polysilicon film having a thickness of about 800 nm by atmospheric pressure CVD. Form. This polysilicon film becomes the gate electrode 22. As a method of forming the gate electrode 22, there is a method of depositing a conductor directly in the gate trench 21 or a method of once depositing a high resistance semiconductor and then diffusing impurities into the insulating layer.

  Next, the electrode layer made of the gate material 22 is etched. Thereafter, cap oxidation is performed to form an oxide film on the surface of the electrode layer. Finally, a semiconductor device 100 as shown in FIG. 1 is manufactured by forming a source electrode, a drain electrode, and the like.

  In the case of the semiconductor device 110 having the three-layer P floating region shown in FIG. 2, the patterning shown in FIG. 4D and the trench dry etching shown in FIG. 4E are repeated. That is, patterning and trench dry etching are repeated to form a trench having two step portions in the thickness direction of the semiconductor substrate. Then, ion implantation and thermal diffusion treatment are performed on the stepped trench. As a result, a three-layer P floating region is formed. That is, even if the P floating region is a semiconductor device having a structure of three or more layers, all the P floating regions can be formed by one thermal diffusion process.

[Application example of the first embodiment]
The semiconductor device 100 shown in FIG. 1 can be manufactured by the manufacturing process shown in FIG. 6 in addition to the manufacturing process described above. This manufacturing process is the same as the manufacturing process described above in that the semiconductor substrate shown in FIG. Similarly, a hard mask 91 such as HTO is formed on the semiconductor substrate, and a resist 92 is formed on the hard mask 91.

  In this manufacturing process, patterning is first performed with a groove width equal to the width of the upper trench 21 as shown in FIG. That is, patterning of a portion corresponding to the upper trench 21 is performed. Next, after performing mask dry etching, trench dry etching is performed as shown in FIG. By this dry etching, the upper trench 21 is formed. After performing trench dry etching, unnecessary resist 92 is removed.

  Next, as shown in FIG. 6C, an insulating film 96 is deposited in the upper trench 21 by the CVD method. As the insulating film 96, for example, a silicon oxide film using TEOS as a raw material corresponds. At this time, the insulating film 96 is formed on the surface of the silicon substrate so that a gap having a width equivalent to the width of the lower trench 25 remains in the upper trench 21. Specifically, when the semiconductor device 100 is manufactured, the insulating film 96 having a thickness of about 0.2 μm is formed.

  Next, dry etching is performed to remove the bottom of the insulating film 96 as shown in FIG. During this dry etching, the etching does not proceed on the side wall of the upper trench 21 because the etching rate is slow. Therefore, the insulating film 96 on the bottom of the upper trench 21 and the surface of the silicon substrate is removed, and the semiconductor layer on the bottom of the upper trench 21 is exposed. On the other hand, the insulating film 96 on the side wall of the upper trench 21 is left without being etched.

  Next, trench dry etching is performed as shown in FIG. By this dry etching, the exposed portion of the semiconductor layer in the bottom of the upper trench 21 is dug down, and the lower trench 25 is formed. After performing trench dry etching, unnecessary insulating film 96 and hard mask 91 are removed. As a result, a trench having a desired shape is obtained as shown in FIG.

  Thereafter, a thermal oxidation process is performed to form a sacrificial oxide film 93 having a thickness of about 30 nm on the respective wall surfaces of the upper trench 21 and the lower trench 25. Thereafter, the semiconductor device 100 as shown in FIG. 1 is manufactured by performing the processing after FIG. 4F in the manufacturing process described above. Further, by repeating the processes from the formation of the oxide film mask shown in FIG. 6C to the trench dry etching shown in FIG. 6E, the semiconductor device 110 having the three-layer P floating region is formed. It is possible.

  As described above in detail, in the semiconductor device 100 of the first embodiment, a step-shaped gate trench is provided. That is, the upper trench 21 and the lower trench 25 formed by further digging a part of the bottom of the upper trench 21 are provided. Impurities are simultaneously buried in the step portion of the gate trench (the bottom portion of the upper trench 21) and the bottom portion of the gate trench (the bottom portion of the lower trench 25) by performing ion implantation on the step-shaped gate trench. Then, the P floating region 51 and the P floating region 52 are formed by one thermal diffusion process. That is, in this embodiment, a P-floating region having a multilayer structure can be formed without repeating the epitaxial growth process, the ion implantation process, the thermal diffusion process, and the like as in the conventional embodiment. Therefore, the manufacturing process is simple.

In the semiconductor device 100 of the first embodiment, the gate trench has a step shape, and a P floating region also exists below the step portion. Therefore, the size of the P floating region 52 located in the middle of the bottom of the gate trench and the P body region 41 is larger than that of the conventional form (see FIG. 21). Therefore, the withstand voltage holding function can be sufficiently exhibited.

  Further, the gate trench has a wide upper trench 21 on the surface side and a narrow inner lower trench 25. Therefore, the filling property of the insulating film 23 is good. Even if a void or the like is generated in a portion away from the gate electrode 22, for example, in the lower trench 25, the element characteristics are not affected.

  In this embodiment, a plurality of P floating regions are simultaneously formed by a single thermal diffusion process. Therefore, the thermal load is small and the controllability of the size of the P floating region is good. Therefore, the adjustment between adjacent P floating regions can be performed finely, and the semiconductor substrate can be made compact. Further, since the impurity is implanted by ion implantation from a direction perpendicular to the semiconductor substrate, the impurity can be surely buried up to the bottom of the trench.

  Further, since the deposited insulating layer 23 is formed below the gate electrode 22, the feedback capacitance (Cgd) between the gate and the drain is small. Therefore, oscillation can be prevented and drive loss can be reduced.

[Second form]
The semiconductor device 200 according to the second embodiment has the structure shown in the front sectional view of FIG. A feature of the semiconductor device 200 of this embodiment is that the semiconductor device 200 has a so-called super junction structure. That is, in the semiconductor device 200 of this embodiment, P - P below the body region 41 - P-type diffusion region is provided in communication with the body region 41, the P-type diffusion region and the N - drift region 12 and the semiconductor substrate The structure is repeated alternately in the width direction. This is different from the first embodiment in which the P-type diffusion region located below the P body region 41 is a floating region.

The semiconductor device 200 is provided with an N + source region 31, an N + drain region 11, a P body region 41, and an N drift region 12, similarly to the semiconductor device 100 of the first embodiment. On the upper surface side of the semiconductor device 200, an upper trench 21 that penetrates the P body region 41 and a lower trench 25 having an opening at the bottom of the upper trench 21 are provided. That is, the upper trench 21 having a large width and the lower trench 25 having a small width are integrated to form a stepped gate trench. A deposited insulating layer 23 is provided in the upper trench 21 and the lower trench 25. Furthermore, a gate electrode 22 is built in the upper trench 21.

Further, P diffusion region 54 and P diffusion region 55 sandwiched between N drift regions 12 are formed in semiconductor device 200. Further, the P diffusion region 54 is located below the P diffusion region 55. The bottom of the lower trench 25 is located in the P diffusion region 51, and the bottom of the upper trench 21 (the step portion of the stepped trench) is located in the P diffusion region 55. The cross sections of the P diffusion region 54 and the P diffusion region 55 are substantially circular, and the upper portion of the P diffusion region 54 and the lower portion of the P diffusion region 55 are connected. That is, the P diffusion region 54 and the P diffusion region 55 are an integral P type diffusion region. The lower trench 25 is surrounded by the P diffusion region 54 and the P diffusion region 55.

P diffusion region 54 and P diffusion region 55 are also connected to P body region 41. FIG. 8 is a cross-sectional view showing the AA cross section of FIG. 7, that is, a state when the semiconductor device 200 is viewed from above. FIG. 9 is a cross-sectional view showing a cross section taken along the line B-B of FIG. 7, that is, a state when the semiconductor device 200 is viewed from the side. FIG. 7 is a cross-sectional view showing a state when the semiconductor device 200 is viewed from the front. As shown in FIG. 8, in the semiconductor device 200, a P diffusion layer 50 connected to the P body region 41 is provided around the longitudinal end portion of the upper trench 21. Further, the P diffusion layer 50 is connected to the P diffusion region 55 as shown in FIG. That is, the P body region 41, the P diffusion region 54, and the P diffusion region 55 form an integral P-type diffusion region via the P diffusion layer 50.

The size and concentration of the P diffusion regions 54 and 55 must be designed in consideration of the charge balance. Specifically, it is designed to satisfy the following conditional expression (1).
d1 · n1 = d2 · n2 (1)
In conditional expression (1), d1 is the width of the N drift region 12 sandwiched between the P diffusion regions (dimension d1 in FIG. 7), n1 is the impurity concentration of the N drift region 12, and d2 is the P diffusion region. The width (dimension d2 in FIG. 7) and d2 mean the impurity concentration of the P diffusion region, respectively.

Note that the semiconductor device 200 of this embodiment can be manufactured by a manufacturing process substantially similar to the manufacturing process of the first embodiment. The difference from the first embodiment is that a step of forming a P diffusion layer 50 connected to the P body region 41 and the P diffusion region 54 is added. Specifically, it can be easily manufactured by adding a photolithography process and performing a diffusion treatment deeper than the P body region 41.

As described above in detail, in the semiconductor device 200 of the second embodiment, the P diffusion regions 54 and 55 are connected and provided below the P body region 41 and in the thickness direction of the semiconductor substrate. Further, the P body region 41 and the P diffusion region 54 are connected to have the same potential. Further, the P diffusion regions 54 and 55 and the N drift region 12 are alternately repeated in the width direction of the semiconductor substrate, that is, a super junction structure.

  In this embodiment, similarly to the first embodiment, a multilayer P floating region can be formed without repeating the epitaxial growth process, the ion implantation process, the thermal diffusion process, and the like as in the conventional embodiment. Therefore, the manufacturing process is simple. Further, a plurality of P diffusion regions are simultaneously formed by one thermal diffusion process. Therefore, the heat load is small and the controllability of the size of the P diffusion region is good. Therefore, the pitch of the adjacent P diffusion regions 54 and 54 can be made narrower than that of the conventional form. Therefore, a higher breakdown voltage can be achieved compared to the conventional form. In particular, this structure is suitable for a low on-resistance device in a low breakdown voltage zone (withstand voltage 200 V or less).

[Third embodiment]
The semiconductor device 300 according to the third embodiment has the structure shown in the front sectional view of FIG. A feature of the semiconductor device 300 of this embodiment is that a trench (gate trench) in which a gate electrode is incorporated and a trench (P diffusion region trench) for forming a P diffusion region constituting a super junction structure are separated. The trench for the P diffusion region is provided in a step shape. This is different from the second embodiment in which the gate trench and the P diffusion region trench are integrated.

The semiconductor device 300 is provided with an N + source region 31, an N + drain region 11, a P body region 41 and an N drift region 12 as in the semiconductor device 200 of the second embodiment. Further, a trench 27 formed by digging a part of the upper surface side of the semiconductor device 300 is provided. In addition, the gate electrode 22 is built in the trench 27. Gate electrode 22 is insulated from P body region 41 by gate insulating film 24 formed on the wall surface of trench 21.

  In addition to the gate trench 27 in which the gate electrode 22 is built, the semiconductor substrate is provided with P diffusion region trenches on both sides of the gate trench 27. This P diffusion region trench is formed in a stepped shape by a wide upper trench 21 and a narrow lower trench 25, and the inside thereof is filled with an insulator.

Further, P diffusion region 54 and P diffusion region 55 sandwiched between N drift regions 12 are formed in semiconductor device 300. Further, the P diffusion region 54 is located below the P diffusion region 55. The bottom of the lower trench 25 is located in the P diffusion region 51, and the bottom of the upper trench 21 (the step portion of the stepped trench) is located in the P diffusion region 55. The cross sections of the P diffusion region 54 and the P diffusion region 55 are substantially circular, and the upper portion of the P diffusion region 54 and the lower portion of the P diffusion region 55 are connected. That is, the P diffusion region 54 and the P diffusion region 55 are an integral P type diffusion region.

Further, in the semiconductor device 300, unlike the semiconductor device of the second embodiment, the upper part of the P diffusion region 55 and the lower surface of the P body region 41 are connected. That is, it is not necessary to provide the P diffusion layer 50, and the P diffusion region 55 and the P body region 41 are an integral P type diffusion region. That is, in the semiconductor device 300 of this embodiment, the trench for incorporating the gate electrode 22 and the trench for forming the P diffusion region are separated. Therefore, even if the trench for forming the P diffusion region is surrounded by the P-type impurity region, it does not hinder the drain current. Therefore, the upper portion of the P diffusion region 55 and the lower surface of the P body region 41 are connected to ensure depletion in the N drift region 12.

In the semiconductor device 300 of this embodiment, P - downwardly P body region 41 - P diffusion regions 54 and 55 are connected to the body region 41 is provided, and the P diffusion region 54 and 55 N - and the drift region 12 It is a so-called super junction structure that is alternately repeated in the width direction of the semiconductor substrate. Hereinafter, a manufacturing process of the semiconductor device 300 will be described.

First, an N type silicon layer is formed on the N + substrate to be the N + drain region 11 by an epitaxial growth process. The impurity concentration of this epitaxial layer is 2.5E16 / cm 3 . Then, a P body region 41, an N + source region 31, and a contact P + region 32 are formed by subsequent ion implantation or the like. Further, the gate trench 27 is formed, and the gate electrode 22 is formed in the gate trench 27. As a result, a semiconductor substrate as shown in FIG. That is, a trench gate portion is formed in advance before forming each P diffusion region.

  Next, a hard mask 91 such as HTO is formed on the semiconductor substrate, and a resist 92 is formed on the hard mask 91. Then, patterning of a portion corresponding to the lower trench 25 is performed. Next, after performing mask dry etching, trench dry etching is performed as shown in FIG. The intermediate trench 29 is formed by this dry etching. The width of the intermediate trench 29 is equal to the width of the lower trench 25. The depth of the intermediate trench 29 (the length from the upper surface of the semiconductor substrate to the bottom of the intermediate trench 29) is the depth of the lower trench 25 (from the opening of the lower trench 25 (the bottom of the upper trench 21) to the bottom thereof. Is equivalent to the length).

  Next, patterning of a portion corresponding to the upper trench 21 is performed. Next, after performing mask dry etching, trench dry etching is performed again as shown in FIG. By this dry etching, the patterned trench is evenly dug in the thickness direction of the semiconductor substrate, and the upper trench 21 and the lower trench 25 are formed simultaneously. After performing trench dry etching, unnecessary hard mask 91 and resist 92 are removed.

  Next, a sacrificial oxide film 93 having a thickness of about 30 nm is formed on the wall surfaces of the upper trench 21 and the lower trench 25 by performing a thermal oxidation process. The sacrificial oxide film 93 is used to prevent ion implantation from being performed on the side walls of each trench.

  Next, as shown in FIG. 12D, impurity ions are implanted from the bottom of each trench. Next, as shown in FIG. 12E, an insulating film 23 is deposited in the P diffusion region trench by the CVD method. Specifically, the insulating film (deposited insulating layer) 23 corresponds to, for example, a silicon oxide film formed by a low pressure CVD method using TEOS as a raw material or a CVD method using ozone and TEOS as raw materials. In this embodiment, since there is no etch back process, the sacrificial oxide film 93 can also serve as an oxide film (thermal oxide film 94 in the first embodiment) in order to eliminate the influence of the interface state.

  Next, by performing a thermal diffusion process also as an annealing process for the deposited insulating layer 23, P diffusion regions 54 and 55 are formed as shown in FIG. Thereafter, by forming a source electrode, a drain electrode, and the like, the semiconductor device 300 as shown in FIG. 10 is manufactured.

The characteristics shown in Table 1 below were confirmed in the semiconductor device 300 by simulation.

  As described above in detail, in the semiconductor device 300 of the third embodiment, the gate trench and the P diffusion region trench are separated. Therefore, the gate trench may be formed by a conventional method and is easy to manufacture. In addition, since it is not necessary to form a gate electrode on the deposited insulating layer 23 as in the first embodiment, the embeddability of the insulating film 23 is not a problem. Furthermore, it is not necessary to consider the position and size of the gate electrode when designing the P diffusion region. Therefore, the design freedom is high. Further, the distance between the gate electrode 22 and the P diffusion region 54 is longer than that of the second semiconductor device 200. Therefore, it is easy to secure a current path.

  Note that this embodiment is merely an example, and does not limit the present invention. Therefore, the present invention can naturally be improved and modified in various ways without departing from the gist thereof. For example, the gate insulating film 24 is not limited to an oxide film, and may be another type of insulating film such as a nitride film or a composite film. Also, the semiconductor is not limited to silicon, but may be other types of semiconductors (SiC, GaN, GaAs, etc.).

  Although the semiconductor device of the embodiment is a trench gate type semiconductor device, the scope of application of the present invention is not limited to this. That is, the present invention can be applied to a planar type semiconductor device as shown in FIG. In the semiconductor device 400 shown in FIG. 13, the P junction regions 56 and 57 constitute a super junction structure.

  Further, the semiconductor device of the embodiment can also be applied to a conductivity modulation type power MOS (IGBT) as shown in FIG.

The semiconductor device according to the embodiment has the following characteristics in addition to the characteristics described so far by adopting a conductivity modulation type power MOS. That is, since holes accumulate in each P floating region, each P floating region becomes a hole supply source. As a result, the concentration of holes in the surface region of the N drift region 12, specifically, the region located above the P floating region 51 can be increased. Therefore, the loss can be reduced.

In addition, since a depletion layer is formed also from each P floating region, the breakdown voltage when the load is short-circuited is improved. That is, in the conventional semiconductor device having no P floating region, a depletion layer 15 is formed on the drain side from the PN junction between P body region 41 and N drift region 12 as shown in FIG. Current flows in the region below the trench 21. On the other hand, in the semiconductor device 100 of this embodiment, the deposited insulating layer 23 is formed under the gate electrode 22, and current flows along the trenches 21 and 25 as shown in FIG. A depletion layer 15 is also formed from each P floating region. Therefore, the current path when the load is short-circuited is very narrow. As a result, the short-circuit current is reduced and the withstand voltage when the load is short-circuited is improved.

Further, the present invention can also be applied to a power MOS in which an N hole barrier region 18 acting as a hole barrier is formed between the P body region 41 and the N drift region 12 as shown in FIG. 17 or FIG. is there. In the case of the power MOS in which the N hole barrier region 18 is formed, the depletion layer spreads narrowly in the N hole barrier region 18. As a result, the breakdown voltage may be reduced. However, in the power MOS having the P floating region as in the present embodiment, the depletion layer is formed from the PN junction portion between the P body region 41 and the N drift region 12 and is also depleted from the P floating region. Since the layer is formed, a decrease in breakdown voltage is suppressed.

It is sectional drawing which shows the structure (two-stage structure) of the semiconductor device which concerns on a 1st form. It is sectional drawing which shows the application example (three-stage structure) of the semiconductor device which concerns on a 1st form. FIG. 2 is a diagram (part 1) illustrating a manufacturing process of the semiconductor device illustrated in FIG. 1; FIG. 4 is a diagram (part 2) illustrating a manufacturing process of the semiconductor device illustrated in FIG. 1; FIG. 4 is a diagram (part 3) illustrating a manufacturing process of the semiconductor device illustrated in FIG. 1; FIG. 8 is a diagram (application example) showing a manufacturing process of the semiconductor device shown in FIG. 1; It is front sectional drawing which shows the structure of the semiconductor device which concerns on a 2nd form. It is a top surface sectional view showing the structure of the semiconductor device concerning the 2nd form. It is side surface sectional drawing which shows the structure of the semiconductor device which concerns on a 2nd form. It is front sectional drawing which shows the structure of the semiconductor device which concerns on a 3rd form. FIG. 11 is a diagram (part 1) illustrating a manufacturing process of the semiconductor device depicted in FIG. 10; FIG. 11 is a view (No. 2) showing a manufacturing process of the semiconductor device shown in FIG. 10; It is a figure which shows the example which applied this invention to the planar type semiconductor device. It is a figure which shows the example which applied this invention to the conductivity modulation type semiconductor device. It is a figure which shows the electric current path at the time of the load short circuit in the semiconductor device of the conventional form. It is a figure which shows the electric current path at the time of the load short circuit in the semiconductor device of embodiment. It is sectional drawing which shows the structure (the 1) of the semiconductor device in which the hole barrier layer was formed. It is sectional drawing which shows the structure (the 2) of the semiconductor device in which the hole barrier layer was formed. It is sectional drawing which shows the structure (the 1) of the semiconductor device which concerns on the conventional form. It is sectional drawing which shows the structure (the 2) of the semiconductor device which concerns on the conventional form. It is sectional drawing which shows the structure (the 3) of the semiconductor device which concerns on the conventional form.

Explanation of symbols

11 N + drain region 12 N drift region (drift region)
21 Upper trench (first trench part)
22 Gate electrode (gate electrode)
23 Deposition insulation layer (Deposition insulation layer)
24 Gate insulating film 25 Lower trench (second trench part)
31 N + source region 41 P - body region (body region)
50 P diffusion layer 51 P floating region (second floating region)
52 P floating area (first floating area)
54 P diffusion region (second impurity region)
55 P diffusion region (first impurity region)
100 Semiconductor device

Claims (4)

  1. In a semiconductor device having a drift region that is a first conductivity type semiconductor located on a main surface side of a semiconductor substrate and a body region that is a second conductivity type semiconductor located on an upper surface side of the drift region,
    A first floating region that is surrounded by the drift region and at least partially located below the body region and is a second conductivity type semiconductor;
    An opening is provided in an upper surface of the semiconductor substrate, and a first trench portion penetrating the body region and having a bottom portion located in the first floating region;
    A second floating region that is surrounded by the drift region, is located below the first floating region, is not in contact with the first floating region, and is a second conductivity type semiconductor;
    An opening is provided at the bottom of the first trench, and the bottom has a second trench located in the second floating region;
    In the first trench part,
    A deposited insulating layer formed by depositing an insulator;
    A gate electrode located on the deposited insulating layer and facing the body region is formed;
    The deposited insulating layer has the second trench portion filled with an insulator,
    The semiconductor device according to claim 1, wherein an upper end of the deposited insulating layer is located below the lower end of the body region and above the upper end of the first floating region.
  2. The semiconductor device according to claim 1,
    The width of the opening of the second trench part is narrower than the width of the opening of the first trench part.
  3. In a semiconductor device having a drift region that is a first conductivity type semiconductor located on a main surface side of a semiconductor substrate and a body region that is a second conductivity type semiconductor located on an upper surface side of the drift region,
    A first floating region that is surrounded by the drift region and at least partially located below the body region and is a second conductivity type semiconductor;
    A second floating region that is surrounded by the drift region, is located below the first floating region, is not in contact with the first floating region, and is a second conductivity type semiconductor;
    An opening is formed on the upper surface of the semiconductor substrate, and a step is provided on the wall surface. The step is located in the first floating region and the bottom is located in the second floating region. A trench having a width wider than the width of the bottom,
    In the trench part,
    A deposited insulating layer formed by depositing an insulator;
    A gate electrode located on the deposited insulating layer and facing the body region is formed;
    The semiconductor device according to claim 1, wherein an upper end of the deposited insulating layer is located below the lower end of the body region and above the upper end of the first floating region.
  4. In a method of manufacturing a semiconductor device, wherein a drift region that is a first conductivity type semiconductor located on a main surface side of a semiconductor substrate and a body region that is a second conductivity type semiconductor located on an upper surface side of the drift region are provided. ,
    A mask forming step of forming a mask material on the upper surface of the semiconductor substrate;
    A first patterning step of patterning the mask material with a first groove width;
    After the first patterning step, a first trench portion forming step of forming a trench portion by digging down a part of the semiconductor substrate in the thickness direction;
    A second patterning step of expanding the groove width of the mask material to a second groove width wider than the first groove width after the first trench portion forming step;
    After the second patterning step, a second trench portion forming step of forming a trench portion having a step shape and positioning the step portion in the drift region by digging a part of the semiconductor substrate in the thickness direction; ,
    An impurity implantation step of implanting impurities from the thickness direction of the semiconductor substrate into the step-shaped trench portion formed in the second trench portion formation step;
    A thermal diffusion process is performed after the impurity implantation step, so that the first floating region located at the step portion of the trench portion and the bottom portion of the trench portion is located at the bottom portion of the trench portion. A floating region forming step of forming a second floating region that is non-contact with the region and is a second conductivity type semiconductor ;
    The stepped trench portion formed in the second trench portion forming step is filled with an insulator to form a deposited insulating layer, and the upper end of the deposited insulating layer is located below the lower end of the body region and A gate electrode forming step of removing a part of the deposited insulating layer so as to be located above the upper end of the first floating region, and forming a gate electrode facing the body region on the deposited insulating layer;
    A method for manufacturing a semiconductor device, comprising:
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