JP4735414B2 - Insulated gate semiconductor device - Google Patents

Description

The present invention relates to an insulated gate semiconductor device having a trench gate structure. More specifically, the present invention relates to an insulated gate semiconductor device that relaxes an electric field applied to a drift layer by providing a diffusion layer having a conductivity type different from that of the drift region in the drift region.

  Conventionally, a trench gate type semiconductor device having a trench gate structure has been proposed as an insulated gate type semiconductor device for power devices. In this trench gate type semiconductor device, a high breakdown voltage and a low on-resistance are generally in a trade-off relationship.

As a trench gate type semiconductor device paying attention to this problem, the present applicant has proposed an insulated gate type semiconductor device as shown in FIG. 6 (Patent Document 1). This insulated gate semiconductor device 900 is provided with an N ⁺ source region 31, an N ⁺ drain region 11, a P ⁻ body region 41, and an N ⁻ drift region 12. Further, the gate trench 21 penetrating the P ⁻ body region 41 is formed by digging a part of the upper surface side of the semiconductor substrate. An insulating layer 23 is formed on the bottom of the gate trench 21 by depositing an insulator. Further, a gate electrode 22 is formed on the insulating layer 23. The gate electrode 22 faces the N ⁺ source region 31 and the P ⁻ body region 41 via the gate insulating film 24 formed on the wall surface of the gate trench 21. Further, a floating P diffusion region 51 is formed in the N ⁻ drift region 12. The lower end of the gate trench 21 is located in the P diffusion region 51.

This insulated gate semiconductor device 900 is provided with a floating P diffusion region 51 in the N ⁻ drift region 12 (hereinafter, this structure is referred to as a “floating structure”). Has characteristics.

In this insulated gate semiconductor device 900, when the gate voltage is turned off, a depletion layer spreads from the PN junction portion between the N ⁻ drift region 12 and the P ⁻ body region 41. When the depletion layer reaches the P diffusion region 51, the P diffusion region 51 enters a punch-through state, and the potential is fixed. Further, since the depletion layer also extends from the PN junction portion with the P diffusion region 51, the electric field intensity peak is also present at the PN junction portion with the P diffusion region 51 separately from the PN junction portion with the P ⁻ body region 41. It is formed. That is, electric field intensity peaks can be formed at two locations, and the maximum peak value can be reduced. Therefore, a high breakdown voltage can be achieved. Further, since the withstand voltage is high, the on-resistance can be lowered by increasing the impurity concentration of the N ⁻ drift region 12.

Although different from the structure in which the electric field intensity peaks are formed in two places as in Patent Document 1, the electric field concentration is reduced, for example, in Patent Document 2, an oxide film thicker than the gate oxide film is formed at the bottom of the trench. A technique for relaxing the electric field concentration at the bottom of the trench is disclosed. Although different from the floating structure, for example, Patent Document 3 discloses a technique for suppressing the performance deterioration of the MOSFET by gradually increasing the thickness of the lower portion of the gate insulating film.
JP-A-2005-116822 Japanese Patent Laid-Open No. 10-98188 JP 2004-507092 A

  However, the above-described insulated gate semiconductor device having the trench gate structure has the following problems. In other words, in the insulated gate semiconductor device 900 having a trench gate structure, the gate electrode 22 has a shape that abruptly terminates in the depth direction. Therefore, near the bottom of the gate electrode 22, the equipotential lines are narrow and local electric field concentration occurs. Therefore, the breakdown voltage should be matched to the peak positions (X1 and X2 in FIG. 7) of the electric field intensity at two locations, but the portion near the bottom of the gate electrode 22 (Y in FIG. 7) determines the breakdown voltage. As a result, the design withstand voltage cannot be obtained.

  It is also conceivable to form the gate electrode 22 having a rounded bottom by using isotropic etching such as wet etching. However, wet etching has the following problems. That is, normally, the central portion of the insulating layer 23 under the gate electrode 22 is a portion formed by laminating insulating films deposited from both side walls, and seams and voids are generated. Therefore, when wet etching is performed, a portion where seam or the like is generated has a high etching rate, so that a wedge-shaped groove is formed in the central portion of the insulating layer 23. When the gate material enters the wedge-shaped groove, the depletion layer grows differently from the design when the gate voltage is switched off. As a result, a desired electric field distribution is not formed, resulting in a decrease in breakdown voltage. Further, since the shape of the wedge-shaped groove is not reproducible, it is difficult to form the gate electrode 22 having a stable shape.

  Further, Patent Document 2 discloses a rounded corner at the bottom of the gate trench and the gate electrode, but does not specifically disclose a method of rounding the corner at the bottom of the gate trench. Therefore, in reality, it is considered that the shape ends rapidly like the insulated gate semiconductor device 900 or a complicated manufacturing process is required.

  Further, in Patent Document 3, an oxide film is formed on the wall surface and the bottom surface of the gate trench, a nitride film is formed on the oxide film on the side wall of the gate trench, and thermal oxidation is performed in that state. It is disclosed that the thickness of the oxide film at the bottom of the substrate is thicker than the thickness of the sidewall. However, in this method, the thickness of the oxide film at the bottom of the gate trench is uniformly increased, and the gate electrode does not change into a shape that terminates rapidly in the depth direction. Therefore, the design withstand voltage cannot be obtained.

  In addition, it is conceivable to avoid abrupt termination of the gate electrode by making the entire shape of the gate trench into a tapered shape. However, in the ion implantation for forming the P diffusion region 51, in addition to the bottom portion of the trench, a side wall portion is formed. Impurities are also implanted into the surface. Therefore, it is not preferable to taper the whole when manufacturing a semiconductor device having a floating structure.

The present invention has been made to solve the problems of the above-described conventional insulated gate semiconductor device having a trench gate structure. That is, the problem is to provide an insulated gate semiconductor device that avoids local electric field concentration near the lower end of the gate electrode.

An insulated gate semiconductor device for solving this problem includes a body region which is a first conductivity type semiconductor located on the upper surface side in a semiconductor substrate, and a drift which is a second conductivity type semiconductor in contact with the lower surface of the body region. An insulated gate semiconductor device having a region and a trench portion penetrating the body region from the upper surface of the semiconductor substrate, wherein the insulating layer is located on the bottom of the trench portion and is made of an insulator, A gate electrode layer positioned on the insulating layer and having a lower surface deeper than the lower surface of the body region, a gate insulating film positioned between the body region and the gate electrode layer, a lower end of the gate insulating film, , Having an extended insulating region in contact with the edge of the upper surface of the insulating layer and the corner of the lower surface of the gate electrode layer and having a thickness in the width direction of the trench larger than that of the gate insulating film. Side wall is completely unextended Forms a bulged to the outside of the trench portion along the outer shape of the region, both corner portions of the lower surface of the gate electrode layer, a shape recessed inward along the outer shape of the expanded insulating region with contact with the expanded insulating region, the trench The inside of the portion is characterized by being filled with an insulating layer below the gate electrode layer.

According to the present invention, an insulated gate semiconductor device that avoids local electric field concentration near the lower end of the gate electrode is realized .

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will be described below in detail with reference to the accompanying drawings. In the present embodiment, the present invention is applied to a power MOS that controls conduction between a drain and a source by applying a voltage to an insulated gate.

  An insulated gate semiconductor device 100 (hereinafter referred to as “semiconductor device 100”) according to the embodiment has a structure shown in the cross-sectional view of FIG. Note that in this specification, the whole of the starting substrate and the single crystal silicon portion formed by epitaxial growth on the starting substrate is referred to as a semiconductor substrate.

In the semiconductor device 100, an N ⁺ source region 31 is provided on the upper surface side in FIG. On the other hand, an N ⁺ drain region 11 is provided on the lower surface side. Between them, a P ⁻ body region 41 and an N ⁻ drift region 12 are provided in this order from the upper surface side. In addition, a gate trench 21 is formed by digging a part of the upper surface side of the semiconductor substrate. Gate trench 21 penetrates N ⁺ source region 31 and P ⁻ body region 41.

  An insulating layer 23 is formed on the bottom of the gate trench 21. Specifically, the insulating layer 23 of this embodiment has a two-layer structure, and is formed from the side wall side of the gate trench 21 by a silicon oxide film 231 (hereinafter referred to as “thermal oxide film 231”) formed by thermal oxidation. ) And a silicon oxide film 232 (hereinafter referred to as “CVD oxide film 232”) deposited by the CVD method are sequentially stacked.

Further, a gate electrode 22 is formed on the insulating layer 23. The gate electrode 22 faces the N ⁺ source region 31 and the P ⁻ body region 41 of the semiconductor substrate through a gate insulating film 24 formed on the wall surface of the gate trench 21. That is, the gate electrode 22 is insulated from the N ⁺ source region 31 and the P ⁻ body region 41 by the gate insulating film 24.

In the semiconductor device 100 having such a structure, a channel effect is generated in the P ⁻ body region 41 by applying a voltage to the gate electrode 22, thereby controlling conduction between the N ⁺ source region 31 and the N ⁺ drain region 11. is doing.

  Further, between the gate insulating film 24 and the insulating layer 23 (that is, around the corner on the lower side of the gate electrode 22), an extended insulation in which the film thickness in the width direction of the trench is larger than the film thickness of the gate insulating film 24. Region 241 is formed. Due to the extended insulating region 241, the side portion of the gate trench 21 (that is, the interface between the silicon and the insulator region) has a shape that bulges outward in accordance with the shape of the extended insulating layer 241 near the lower end of the gate electrode 22. ing. That is, a thick insulating region is formed at a site where electric field concentration is likely to occur locally (Y in FIG. 7). Further, the lower corner of the gate electrode 22 has a shape that is recessed inward in accordance with the shape of the extended insulating layer 241. Therefore, the gate electrode 22 has a shape that gradually becomes narrower in the depth direction, that is, has a shape that gradually ends.

Further, in the semiconductor device 100, a floating P diffusion region 51 is formed around the bottom of the gate trench 21 and surrounded by the N ⁻ drift region 12. The P diffusion region 51 is a region formed by implanting impurities from the bottom surface of the gate trench 21. Details of the manufacturing method of the semiconductor device 100 will be described later. The cross section of the P diffusion region 51 has a substantially circular shape centering on the bottom of each trench. In order to increase the breakdown voltage in the floating structure, the peak of the electric field strength when the gate voltage is turned off is the PN junction portion of the P ⁻ body region 41 and the N ⁻ drift region 12, the P diffusion region 51 and the N ⁻ drift. A P diffusion region 51 which is a buried region is arranged at two positions (X1 and X2 in FIG. 7) of the region 12 with the PN junction portion. More preferably, it arrange | positions so that both peak values may become equivalent.

Next, a manufacturing process of the semiconductor device 100 will be described with reference to FIGS. First, an N ⁻ type silicon layer is formed by epitaxial growth on an N ⁺ substrate to be the N ⁺ drain region 11 in advance. This N ⁻ -type silicon layer (epitaxial layer) is a portion that becomes each of the N ⁻ drift region 12, the P ⁻ body region 41, the N ⁺ source region 31, and the contact P ⁺ region 32. The total thickness of the P ⁻ body region 41 and the N ⁻ drift region 12 (hereinafter referred to as “epitaxial layer”) is approximately 7.0 μm at 80V breakdown voltage (including the thickness of the P ⁻ body region 41). Is approximately 1.2 μm). Needless to say, the dimensions differ depending on the pressure resistance.

Next, a P ⁻ body region 41 is formed on the upper surface side of the semiconductor substrate by ion implantation or the like. Thereby, as shown in FIG. 2A, a semiconductor substrate having a P ⁻ body region 41 on the upper surface of the substrate is formed.

Next, a pattern mask 91 is formed on the semiconductor substrate, and trench dry etching is performed. By this trench dry etching, as shown in FIG. 2B, the gate trench 21 penetrating the N ⁺ source region 31 and the P ⁻ body region 41 is formed. The gate trench 21 has a depth of 2.3 μm to 3.0 μm and a width of 0.4 μm to 0.5 μm. The taper angle of the trench side wall is 86.5 degrees to 89.0 degrees. Thereafter, an appropriate cleaning process is performed, and the wall surface of the gate trench 21 is smoothed by using an isotropic etching method such as a chemical dry etching method.

  Next, a thermal oxide film (sacrificial oxide film) having a desired thickness is formed. Thereafter, impurities are implanted from the bottom of each trench by ion implantation. Thereafter, by performing a thermal diffusion process, a P diffusion region 51 is formed as shown in FIG. The thermal diffusion process may be performed when an insulating layer 23 described later is formed. Thereafter, the sacrificial oxide film and the pattern mask 91 are removed to expose a clean silicon surface.

Next, as shown in FIG. 2D, a thin thermal oxide film 231 is formed on a clean silicon surface by thermal oxidation. Specifically, as the film forming conditions of the thermal oxide film 231, for example, the reaction gas is a mixed gas containing O ₂ , H ₂ O, or O ₂ , the oxidation temperature is 800 ° C. to 1100 ° C., and the film thickness is 20 nm to 100 nm. The thermal oxide film is formed. The thermal oxide film 231 is formed as a base of the CVD oxide film in order to stabilize the CVD oxide film embedded in the gate trench 21 in a later step and the silicon interface. The thermal oxidation process may be omitted, and the thermal oxide film may be formed by reoxidation of the buried oxide film interface in a later sacrificial oxidation process.

Next, as shown in FIG. 2E, a CVD oxide film 232 filling the gate trench 21 is deposited on the thermal oxide film 231 by CVD (Chemical Vapor Deposition). As the CVD oxide film 232, for example, a SiO ₂ film having a thickness of 300 nm to 700 nm formed by low pressure CVD using SiH ₄ as a raw material and a film forming temperature of 750 ° C. to 825 ° C. corresponds. In addition, a SiO ₂ film formed by a low pressure CVD method using TEOS (Tetra-Ethyl-Orso-Silicate) as a raw material and a film forming temperature of 600 ° C. to 700 ° C., or CVD using ozone and TEOS as raw materials. The SiO ₂ film formed by the method is applicable.

Next, as shown in FIG. 3F, the thermal oxide film 231 and the CVD oxide film 232, that is, a part of the insulating layer 23 are removed by anisotropic dry etching such as RIE (Reactive Ion Etching) method. Specifically, the insulating layer 23 is etched back by dry etching until the upper surface of the insulating layer 23 is at the same position as the lower surface of the P ⁻ body region 41. Thereby, a space for incorporating the gate electrode 22 is secured. In dry etching, etching is anisotropic regardless of the density of the oxide film and the strength of the Si-O bond. Therefore, voids present on the bonding surface of the CVD oxide film 232 do not affect the etch back. Also, the etching rate difference between the film types is extremely small. Therefore, the insulating layer 23 is uniformly etched back, and its upper surface is flat.

Next, as disclosed in Japanese Patent Application Laid-Open No. 2005-340552, by performing an annealing process in an oxidizing atmosphere, as shown in FIG. An oxide film 94 is formed on the side wall. Specifically, as the film forming conditions for the oxide film 94, for example, the reaction gas is O ₂ , H ₂ O, or a mixed gas containing O ₂ , the oxidation temperature is 800 ° C. to 1100 ° C., and the film thickness is 20 nm to 100 nm. A sacrificial oxide film is formed. This oxidation annealing treatment has roles such as elimination of seams on the bonding surface of the CVD oxide film 232 and enhancement of chemical bonding force due to reaction of unbonded silicon atoms with oxygen.

  Next, the oxide film 94 on the side wall of the gate trench 21 is removed by wet etching, and a clean silicon surface is exposed as shown in FIG. Specifically, the etch-back condition is that the chemical solution is diluted hydrofluoric acid or buffered hydrofluoric acid, and the thermal oxide film is etched back by a thickness of 100 nm to 300 nm. After etch back, an appropriate cleaning process is performed to obtain a clean silicon surface.

Next, as shown in FIG. 3I, a gate insulating film 24 is formed by thermal oxidation, film formation by CVD, or a combination thereof. Specifically, when performing the thermal oxidation treatment, for example, the reaction gas is O ₂ , H ₂ O, or a mixed gas containing O ₂ , and the heat formed by the thermal oxidation treatment at an oxidation temperature of 800 ° C. to 1100 ° C. This corresponds to an oxide film. In the case of forming an oxide film by the CVD method, for example, a SiO ₂ film formed by low pressure CVD using SiH ₄ as a raw material and a film forming temperature of 750 ° C. to 825 ° C. is applicable. In addition, a SiO ₂ film formed by a low pressure CVD method using TEOS as a raw material and a film forming temperature of 600 ° C. to 700 ° C. is applicable. The thickness of the gate insulating film 24 in this embodiment is in the range of 50 nm to 100 nm.

  Next, as shown in FIG. 3J, a CVD nitride film 244 having a thickness of 10 nm to 30 nm is deposited on the gate oxide film 24 and the insulating layer 23 by CVD. The CVD nitride film 244 corresponds to, for example, a SiN film formed by low pressure CVD using SiN as a raw material and a film forming temperature of 700 ° C. to 800 ° C.

  Next, the CVD nitride film 244 on the substrate surface and on the insulating layer 23 is removed by anisotropic dry etching such as RIE as shown in FIG. Specifically, the CVD nitride film 244 is etched back by dry etching until the upper surface of the insulating layer 23 is exposed. By anisotropically etching back, the CVD nitride film 244 on the channel region, that is, on the sidewall of the trench, remains. Note that the oxide film on the substrate surface does not necessarily remain. Appropriate cleaning is performed after etch back.

Next, as shown in FIG. 4L, an extended insulating region 241 having a width larger than that of the gate insulating film 24 is formed between the gate insulating film 24 and the insulating layer 23 by thermal oxidation treatment. That is, since the sidewall of the trench that becomes the channel region is protected by the CVD nitride film 244, the oxide film thickness does not increase. Therefore, there is no problem of increasing the threshold voltage. On the other hand, since the CVD nitride film 244 is removed on the substrate surface and the upper surface of the insulating layer 23, oxygen can be supplied. However, since a thick oxide film exists in the thickness direction of the substrate at the central portion of the upper surface of the insulating layer 23, the silicon at the bottom of the gate trench 21 is not oxidized. On the other hand, at both end portions of the upper surface of the insulating layer 23, the distance from the exposed surface to the silicon portion is short. Therefore, the SiO ₂ region increases. That is, by covering the side wall of the gate trench 21 with the CVD nitride film 244, the vicinity of both ends of the upper surface of the insulating layer 23 (the lower surface of the gate electrode 22) where the electric field tends to concentrate locally is emphasized and oxidized. Since the extended insulating region 244 concentrates and oxidizes silicon near the end of the upper surface of the insulating layer 23, the insulating region near the end extends to the outside of the gate trench 21. In other words, the shape of the sidewall of the gate trench 21 (that is, the interface between the silicon and the insulator region) swells outside the gate trench 21 at the end (the joint portion between the gate insulating film 24 and the insulating layer 23). To. Further, the extended insulating region 241 extends the insulating region in the vicinity of the end portion to the inside of the gate trench 21. Specifically, as the conditions for forming the extended insulating region 241, for example, the reaction gas is O ₂ , H ₂ O, or a mixed gas containing O ₂ , the oxidation temperature is 800 ° C. to 1100 ° C., and the film thickness in the width direction of the trench. The extended insulating region 241 having a thickness of 50 nm to 300 nm is formed.

  Next, the CVD nitride film 244 on the side wall of the gate trench 21 is removed by wet etching, and the gate insulating film 24 is exposed on the side wall of the gate trench 21 as shown in FIG. Specifically, the etch back is performed using a chemical solution as hot phosphoric acid. That is, when the CVD nitride film 244 is etched back by dry etching, deposits are generated on the remaining CVD nitride film 244. Therefore, the interface is cleaned by completely removing the CVD nitride film 244. Further, by removing the CVD nitride film 244, the gate insulating film 24 can be thinned. Therefore, the threshold voltage characteristic is stabilized.

Next, as shown in FIG. 4N, the gate material 22 is deposited in the space secured by the etch back of the insulating layer 23. Specifically, the film formation conditions for the gate material 22 include, for example, a reactive gas mixed gas containing SiH ₄ , a film formation temperature of 580 ° C. to 640 ° C., and a polysilicon film having a thickness of about 800 nm by atmospheric pressure CVD. Form. The bottom surface of the polysilicon film 22 has a shape in which the extended insulating region 241 protrudes to the inside of the space, so that it gently tilts toward the center in the width direction of the gate trench 21. That is, the polysilicon film 22 has a shape that terminates gently in the depth direction.

Next, the polysilicon film 22 is etched. Thereby, the gate electrode 22 is formed. Thereafter, an N ⁺ source region 31 and a contact P ⁺ region 32 are formed in the portion where the P ⁻ body region 41 is formed by ion implantation of boron, phosphorus or the like and subsequent thermal diffusion treatment. Note that the N ⁺ source region 31 and the contact P ⁺ region 32 may be formed in advance before the gate trench 21 is formed. Further, an interlayer insulating film or the like is formed on the semiconductor substrate, and finally a source electrode and a drain electrode are formed, whereby the trench gate type semiconductor device 100 shown in FIG. 1 is manufactured.

  In this embodiment, the CVD nitride film 244 that is a protective film for the gate insulating film 24 is removed by hot phosphoric acid, but it may be left as it is and used as a part of the gate insulating film. That is, the gate insulating film may have a multilayer structure of an oxide film, a nitride film, and an oxide film. By leaving the CVD nitride film 244, the wet etching process of the nitride film (FIG. 4M) can be omitted, and the manufacturing becomes simple.

  In this embodiment, the insulating layer 23 under the gate electrode 22 has a two-layer structure of the thermal oxide film 231 and the CVD oxide film 232, but may have a single-layer structure. That is, the thermal oxidation process (FIG. 2D) for forming the thermal oxide film 231 after the formation of the gate trench 21 may be omitted.

  Further, a dry etching process (FIG. 4K) for removing a part of the CVD nitride film 244 and a thermal oxidation process (FIG. 4L) for forming the extended insulating region 241 are shown in FIG. Thus, an oxide film wet etching step (FIG. 5 (K ′)) may be added. By performing wet etching of the insulating film 23 that is an oxide film, the upper surface of the insulating film 23 is lowered downward, and a large gap is generated between the upper surface of the insulating film 23 and the lower end of the CVD nitride film 244. As a result, silicon around the corners on the lower surface of the gate electrode 22 is easily oxidized, and a wider expanded insulating region 241 can be formed. In addition, since the expanded insulating region 241 expands from the gap between the upper surface of the insulating film 23 and the lower end of the CVD nitride film 244, the influence of an increase in stress due to expansion is less than that in the embodiment having almost no gap.

  As described above in detail, in the semiconductor device 100 of this embodiment, an insulator is deposited in the gate trench 21, and then the insulating film having a large thickness in the substrate thickness direction is formed in the gate trench 21 by etching back the insulator. The layer 23 is to be formed. The insulating layer 23 has a film thickness that does not oxidize the silicon near the bottom of the gate trench 21 in the subsequent thermal oxidation step. Thereafter, a gate insulating film 24 (thermal oxide film) is formed on the side wall of the gate trench 21 reopened by etch back, and a thin CVD nitride film 244 is formed on the gate insulating film 24. Further, the CVD nitride film 244 is removed by anisotropic dry etching. As a result, the CVD nitride film 244 located on the insulating layer 23 is removed from the CVD nitride film 244 while leaving the CVD nitride film 244 located on the gate insulating film 24.

  Thereafter, thermal oxidation is performed with the CVD nitride film 244 protecting the gate insulating film 24 (that is, the channel region). At this time, oxidation of the side walls of the gate trench 21 is suppressed by the CVD nitride film 244. Further, oxidation at the bottom of the gate trench 21 is suppressed by the thick insulating layer 23. On the other hand, in the vicinity of the end portion of the upper surface of the insulating layer 23 (near the lower end of the CVD nitride film 244), the distance between the exposed surface and the silicon portion is short, and silicon is oxidized. That is, the CVD nitride film 244 and the insulating layer 23 can oxidize the two ends of the upper surface of the insulating layer 23 with emphasis, and the extended insulating region 241 having a thickness larger than that of the gate insulating film 24 at the both ends. It is formed.

  The extended insulating region 241 is a region formed by oxidizing silicon in the vicinity of the joint between the upper surface of the insulating layer 23 and the lower end of the gate insulating film 24. The extended insulating region 241 includes an insulating region integrated with the insulating layer 23 and the gate insulating film 24. Become. Since the extended insulating region 241 is formed by concentrating and oxidizing silicon near the joint, the insulating region near the joint is extended outside the gate trench 21. That is, the side wall of the gate trench 21 (that is, the interface between the silicon and the insulator region) is shaped to bulge outside the trench at the joint. That is, a thick oxide film region is formed at a site where electric field concentration is likely to occur locally (Y in FIG. 7). Thereby, the dielectric breakdown in the said site | part is suppressed. Further, the extended insulating region 241 extends the insulating region near the joint to the inside of the gate trench 21. Therefore, both corners of the lower surface of the gate electrode 22 can be formed to be recessed inward along the outer shape of the extended insulating region 241. As a result, the bottom of the gate electrode 22 has a shape that gently terminates in the depth direction. Therefore, local electric field concentration at the corners on the lower surface of the gate electrode 22 is alleviated. Therefore, an insulated gate semiconductor device that avoids local electric field concentration near the lower end of the gate electrode, and a manufacturing method that can easily produce the insulated gate semiconductor device with high accuracy have been realized.

  In particular, in the semiconductor device 100 in which the P floating region 51 is formed by ion implantation from the bottom of the gate trench 21, the gate trench 21 having a deep depth (a large aspect ratio) for forming the P floating region 51, the gate A thick insulating layer 23 that fills the space from the bottom of the trench 21 to the lower end of the gate electrode 22 is provided. Therefore, it is particularly useful to apply the present invention to a semiconductor device having such a floating structure.

  Note that this embodiment is merely an example, and does not limit the present invention. Therefore, the present invention can naturally be improved and modified in various ways without departing from the gist thereof. For example, for each semiconductor region, P-type and N-type may be interchanged. Also, the semiconductor is not limited to silicon, but may be other types of semiconductors (SiC, GaN, GaAs, etc.). The insulated gate semiconductor device of the embodiment can also be applied to an IGBT.

It is sectional drawing which shows the structure of the insulated gate semiconductor device concerning embodiment. FIG. 6 is a diagram (part 1) illustrating a manufacturing process of the insulated gate semiconductor device according to the embodiment; FIG. 6 is a diagram (part 2) for illustrating a manufacturing process of the insulated gate semiconductor device according to the embodiment; FIG. 6 is a diagram (part 3) illustrating a process for manufacturing the insulated gate semiconductor device according to the embodiment; It is a figure which shows the manufacturing process of the insulated gate semiconductor device concerning a modification. It is sectional drawing which shows the structure of the conventional insulated gate semiconductor device. It is a figure which shows the electric field concentration location of the insulated gate semiconductor device which has a floating structure.

Explanation of symbols

11 N ⁺ drain region 12 N ⁻ drift region 21 Gate trench (trench portion)
22 Gate electrode (gate electrode layer)
23 Insulating layer 24 Gate insulating film 241 Extended insulating region 244 CVD nitride film (oxidation protective film)
31 N ⁺ source region 41 P ^- body region 51 P diffusion region 100 insulated gate semiconductor device

Claims (2)

A body region which is located on the upper surface side of the semiconductor substrate and is a first conductivity type semiconductor, a drift region which is in contact with the lower surface of the body region and is a second conductivity type semiconductor, and a trench which penetrates the body region from the upper surface of the semiconductor substrate In an insulated gate semiconductor device having a portion,
An insulating layer located on the bottom of the trench and made of an insulator;
A gate electrode layer located in the trench and on the insulating layer, the lower surface being located deeper than the lower surface of the body region ;
A gate insulating film located between the body region and the gate electrode layer;
The film thickness in the width direction of the trench portion is larger than the film thickness of the gate insulating film, in contact with the lower end of the gate insulating film, the edge of the upper surface of the insulating layer, and the corner of the lower surface of the gate electrode layer An extended insulation region,
The sidewall of the trench portion has a shape that bulges outside the trench portion along the outer shape of the extended insulating region,
Both corners of the lower surface of the gate electrode layer are in contact with the extended insulating region and are recessed inward along the outer shape of the extended insulating region ,
The insulated gate semiconductor device , wherein a portion of the trench portion below the gate electrode layer is filled with the insulating layer . The insulated gate semiconductor device according to claim 1,
A floating region surrounded by the drift region and being a first conductivity type semiconductor;
The trench portion has a bottom located in the floating region,
The floating region is disposed at a position where the electric field strength at the junction between the floating region and the drift region is equal to the electric field strength at the junction between the body region and the drift region. An insulated gate semiconductor device.

Images