JP2012169421A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce gate-drain capacitance of a vertical power MOS transistor having trench gate structure.SOLUTION: A dummy oxide film 12 is formed in a trench 4 extending from a surface of a P type body layer 3 to the inside of an N type drift layer 2. Subsequently, a polysilicon film 11 is deposited on an N+ type semiconductor substrate 1 including the inside of the trench 4 and etched back to form a polysilicon layer 11a on a bottom face of the trench 4. Subsequently, by performing sacrificial oxidation, the polysilicon layer 11a on the bottom face of the trench 4 becomes a silicon oxide film 11b. Subsequently, all of the thickened dummy oxide film 12a on a sidewall of the trench 4 and a part of the silicon oxide film 11b on the bottom face of the trench 4 are removed by etching. Subsequently, gate oxidation is performed and a gate insulation film 5a is formed on the sidewall of the trench 4 and a gate insulation film 5b thicker than the gate insulation film 5a is formed on the bottom face of the trench 4.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device and a method for manufacturing the same in which a gate-drain capacitance of a vertical power MOS transistor having a trench gate structure is reduced.

   Power MOS transistors are widely used in switching power supplies such as DC-DC converters and motor inverter circuits because they have superior switching characteristics and are stable and easy to use compared to bipolar power transistors. Since power MOS transistors have a long history of products and are easy to make, horizontal power MOS transistors in which a source region, a drain region, and a gate region are formed on the surface of a semiconductor substrate were mainly used.

  However, the demand for high withstand voltage, large current, and low saturation voltage is increasing, the semiconductor substrate is etched to form a plurality of trenches, a gate insulating film is formed on the trench sidewall, and the inside of the trench in which the gate insulating film is formed is formed. A vertical power MOS transistor with a trench gate structure embedded with a gate electrode has been developed. As a result, the on-resistance with respect to the current flowing from the source electrode through the channel layer to the drain electrode has been drastically reduced by miniaturization and higher density of the cell.

However, since the bottom surface of the trench and the vicinity thereof are opposed to each other via the drift layer and the gate insulating film, the gate-drain capacitance C _GD in this portion may be a problem. In particular, when high-frequency operation is required in a portable device or the like, the gain-bandwidth product of the power MOS transistor is reduced because the gate-drain capacitance C _GD affects the input capacitance. The gate-drain capacitance C _{GD in this portion} is a capacitance in which an insulating film capacitance C _OX that is inversely proportional to the thickness of the gate insulating film and a depletion layer capacitance C _S extending in the drift layer immediately below the gate insulating film are connected in series. .

In general, the gate insulating film grown on the inner wall of the trench tends to be thinner at and near the bottom surface than the side wall portion. When the gate insulating film in the channel layer forming region on the trench side wall portion is set to the optimum film thickness, As a result, the gate insulating film becomes thin, C _OX increases, and the gate-drain capacitance C _GD increases. The depletion layer capacitance C _S is determined by the impurity concentration of the drift layer determined based on the balance between high breakdown voltage and low on-resistance. Therefore, since the depletion layer capacitance C _S is reduced, it is difficult to easily reduce the impurity concentration of the drift layer.

Patent Document 1 below discloses a technique for reducing the gate-drain capacitance _CGD by increasing the thickness of the gate insulating film at the bottom of the trench to reduce the insulating film capacitance _COX . In the case of a lateral power MOS transistor, a technique for reducing the gate-drain capacitance C _GD by reducing the depletion layer capacitance C _S is disclosed in Patent Document 2 below.

JP 2007-242943 A JP 2010-171433 A

  Patent Document 1 discloses that a gate insulating film is formed thickly on the bottom surface of a trench not covered with a silicon nitride film by exposing the semiconductor substrate to a high-temperature oxidizing atmosphere with the trench sidewalls covered with a silicon nitride film. is doing. There is an advantage that the gate insulating film on the bottom surface of the trench can be surely made to have a necessary film thickness, but cost and man-hour are required for forming a mask of the silicon nitride film.

In Patent Document 2, while reducing the depletion layer capacitance C _S of the lateral power MOS transistor, the impurity concentration of the drift layer extending from the end of the channel region directly below the gate electrode to the drain region is set so as not to increase the on-resistance. It is divided into two stages. As a result, the on-resistance is prevented from increasing while the depletion layer capacitance C _S is reduced.

Possible to reduce the thick and the gate-drain capacitance C _GD the gate insulating film of the trench bottom surface without the use of silicon nitride film, and to reduce the depletion layer capacitance C _S of the trench structure vertical power MOS transistor gate The problem is to reduce the drain-to-drain capacitance _CGD .

  The method of manufacturing a semiconductor device of the present invention includes a step of forming a first conductivity type drift layer on a first conductivity type semiconductor substrate, a step of forming a second conductivity type body layer on the drift layer, Forming a trench extending from the surface of the body layer into the drift layer; forming a dummy oxide film covering the inner wall of the trench; and then forming a polysilicon film on the semiconductor substrate including the dummy oxide film Etching back the polysilicon film to form a polysilicon layer on the bottom of the trench, sacrificing the polysilicon layer and the sidewall of the trench, and oxidizing the polysilicon on the sidewall and bottom of the trench. Etching the entire silicon oxide film formed on the sidewalls of the trench and a portion of the silicon oxide film formed on the bottom surface of the trench; A step of forming a gate insulating film covering the inner wall of the trench, a step of forming a gate electrode filling the trench covered with the gate insulating film, and a first conductive layer in the body layer. Forming a source layer of a type and a contact layer of a second conductivity type, wherein the gate insulating film is formed thicker at a bottom surface of the trench than a side wall portion of the trench.

  The method for manufacturing a semiconductor device of the present invention includes a step of forming a first conductivity type drift layer on a first conductivity type semiconductor substrate, and a step of forming a second conductivity type body layer on the drift layer. Forming a trench extending from the surface of the body layer into the drift layer; forming a first conductivity type capacitance forming layer on the drift layer exposed on a bottom surface of the trench; and A step of forming a gate insulating film covering an inner wall; a step of forming a gate electrode embedded in the trench covered by the gate insulating film; and a first conductivity type source layer and a second conductivity in the body layer Forming a contact layer of the mold.

  A semiconductor device of the present invention includes a first conductivity type drift layer formed on a first conductivity type semiconductor substrate, a second conductivity type body layer formed on the drift layer, and a surface of the body layer. A trench formed extending into the drift layer; a first conductivity type capacitance forming layer formed in the drift layer at the bottom of the trench; and a gate insulation formed covering the inner wall of the trench A gate electrode formed by burying in the trench covered with the gate insulating film, and a first conductivity type source layer and a second conductivity type contact layer formed in the body layer, It is characterized by having.

  The semiconductor device according to the present invention is characterized in that the gate insulating film is formed thicker at a bottom surface of the trench than a side wall portion of the trench.

  According to the semiconductor device and the manufacturing method thereof of the present invention, the gate-drain capacitance of a vertical power MOS transistor having a trench gate structure can be reduced.

It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. It is sectional drawing which shows the conventional semiconductor device. It is sectional drawing which shows the semiconductor device in the 2nd Embodiment of this invention, and its manufacturing method. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 2nd Embodiment of this invention.

[First Embodiment]
1 and 2 are cross-sectional views showing a method for manufacturing a semiconductor device of this embodiment. FIG. 3 is a cross-sectional view of a conventional semiconductor device. The same components as those in FIG. 1 are indicated by the same symbols. In the conventional semiconductor device, after the trench 4 is formed, the gate insulating film 5 is simultaneously formed on the side wall and the bottom surface of the trench 4. In this case, the gate insulating film 5c on the bottom surface of the trench 4 shown in the figure may be thinner than the gate insulating film 5a on the side wall of the trench 4, which causes a problem of increased gate-drain capacitance.

  The semiconductor device manufacturing method of this embodiment is intended to solve the problems of the conventional semiconductor device. The only difference from the conventional semiconductor device manufacturing method is the method of forming the gate insulating film 5 on the bottom surface of the trench 4. The other components are manufactured in the same manner.

  First, as shown in FIG. 1, a semiconductor substrate 1 is prepared. The semiconductor substrate 1 becomes an N + type drain layer 1a. N-type drift layer 2 is deposited on semiconductor substrate 1 by a predetermined epitaxial method. The film thickness and specific resistance of the N-type drift layer 2 are determined from the breakdown voltage and on-resistance of the power NMOS transistor.

  Next, as shown in FIG. 2A, a P-type body layer 3 is formed in the N-type drift layer 2 by ion implantation of predetermined boron (B) or the like. When a positive voltage is applied to the gate electrode 6 shown in FIG. 1, a channel layer composed of an N-type inversion layer is formed in the P-type body layer 3 facing the gate insulating film 5a, and the power NMOS transistor is turned on.

  Next, a trench 4 extending from the surface of the P-type body layer 3 to the inside of the N-type drift layer 2 through the P-type body layer 3 is formed by a predetermined dry etching method. Thereafter, damage removal work that has been caused by dry etching is performed on the inner wall of the trench 4 by light etching or generation / removal of a sacrificial oxide film.

  Next, a dummy oxide film 12 made of a silicon thermal oxide film or the like is formed on the semiconductor substrate 1 including the inside of the trench 4, and then a polysilicon film 11 is formed on the entire surface of the semiconductor substrate 1 including the inside of the trench 4 by a predetermined CVD method. accumulate. As shown in the figure, the polysilicon film 11 completely fills the inside of the trench 4.

  Next, as shown in FIG. 2B, the entire surface of the polysilicon film 11 is etched back by predetermined dry etching. In this case, the etch back is performed under such a condition that the polysilicon layer 11a having a desired film thickness remains at the bottom of the trench 4.

  Next, as shown in FIG. 2C, the semiconductor substrate 1 is put into a high temperature furnace, and the polysilicon layer 11a remaining at the bottom of the trench 4 is made into a silicon oxide film 11b by sacrificial oxidation. At this time, the dummy oxide film 12 such as the sidewall of the trench 4 is also thickened to become a dummy oxide film 12a.

  Next, as shown in FIG. 2D, the dummy oxide film 12a is removed by predetermined wet or dry etching to expose the sidewall of the trench 4. In this case, the polysilicon oxide film 11b on the bottom surface of the trench 4 is also partially etched, but a desired thickness or more remains. Next, a gate insulating film 5a having a predetermined thickness made of a silicon thermal oxide film or the like is formed on the exposed sidewall of the trench 4 by a predetermined method.

The bottom surface of the trench 4 is covered with a gate insulating film 5b thicker than the gate insulating film 5a based on the remaining silicon oxide film 11b. Thus, the present embodiment is characterized in that the gate insulating film 5b on the bottom surface of the trench 4 is formed thicker than the gate insulating film 5a on the side wall of the trench 4. As a result, the gate-drain capacitance C _GD is reduced as compared with the conventional case.

  Thereafter, as shown in FIG. 1, a polysilicon film is deposited on the semiconductor substrate 1 including the inside of the trench 4 by a predetermined CVD method. Next, the polysilicon film is etched back by predetermined dry etching to form a gate electrode 6 that fills the inside of the trench 4. Thereafter, arsenic (As) or the like is ion-implanted into the P-type body layer 3 by a predetermined method to form an N + -type source layer 7 and boron (B) or the like is ion-implanted to form a P + -type contact layer 8.

  Next, an interlayer insulating film 9 covering the trench 4 and its periphery is formed by subjecting the insulating film deposited by a predetermined CVD method or the like to a predetermined photoetching process. Thereafter, the source electrode 10 connected to the N + type source layer 7 and the P + type contact layer 8 is formed by performing a predetermined photoetching process on an aluminum (Al) alloy or the like deposited by a predetermined sputtering method. Next, a multilayer wiring structure is formed as necessary, and finally a passivation film made of a silicon nitride film or the like is formed, whereby the semiconductor device of this embodiment is completed.

In the present embodiment, the gate-drain capacitance _CGD between the N-type drift layer 2 and the gate electrode 6 facing each other through the gate insulating film 5b on the bottom surface of the trench 4 is formed by thickening the gate insulating film 5b. This is reduced by reducing the film capacitance C _OX .

[Second Embodiment]
The semiconductor device of this embodiment will be described below with reference to FIG. The same code | symbol is attached | subjected to the structure similar to 1st Embodiment. The first embodiment is different from the conventional example shown in FIG. 3 in that the gate insulating film 5 is not particularly thickly formed on the bottom surface of the torrent 4, and the gate insulating film 5 c on the bottom surface of the trench 4 is the gate on the side wall of the trench 4. The difference is that it may be thinner than the insulating film 5a.

Note that by performing the same steps as in the first embodiment, it is possible to form a thick gate insulating film 5b on the bottom surface of the trench 4 as in the case shown in FIG. In this case, the effect superimposed on the following embodiment is exhibited, and the gate-drain capacitance C _GD can be further reduced.

The greatest difference from the first embodiment is that, as shown in the figure, the impurity concentration in the N-type drift layer 2 is greater than that in the N-type drift layer 2 from the bottom surface of the trench 4 and the vicinity thereof via the gate insulating film 5c. Is provided with a low N− type capacitance forming layer 2a. With this configuration, the feature of this embodiment is that the depletion layer can be easily expanded from the bottom surface of the trench 4 into the N-type drift layer 2 and the depletion layer capacitance C _S is reduced.

As described above, most of the gate-drain capacitance C _GD of the power MOS transistor is the N-type drain layer adjacent to the gate insulating film 5 c on the bottom surface of the trench 4 and the film thickness of the gate insulating film 5 c on the bottom surface of the trench 4. It is determined by the width of the depletion layer extending to 2.

The gate-drain capacitance C _GD is an N-type drift from the gate electrode 6 sandwiching the gate insulation film 5 c to the N-type drain layer 2, and the gate insulation film C _OX between the N-type drain layer 2 and the gate insulation film 5 c on the bottom surface of the trench 4. It comprised in the state where the depletion layer capacitance C _S is connected in series to extend the inside of the layer 2. Therefore, the smaller the insulating film capacitance C _OX or the depletion layer capacitance C _S , the smaller the gate-drain capacitance C _GD can be made.

It is preferable to reduce both the insulating film capacitance C _OX and the depletion layer capacitance C _{S because} the gate-drain capacitance C _GD is further reduced. The first embodiment is characterized in that the gate insulating film 5b on the bottom surface of the trench 4 is thickened to reduce the insulating film capacitance C _OX .

On the other hand, in this embodiment, an N− type capacitance forming layer 2a having an impurity concentration lower than that of the N type drift layer 2 is provided in the N type drift layer 2 below the bottom surface of the trench 4 so that the depletion layer can be easily expanded. it is characterized in that Te is smaller depletion layer capacitance C _S.

  A method for manufacturing the semiconductor device of this embodiment will be described below with reference to FIGS. The process up to the formation of the trench 4 is the same as in the first embodiment. Characteristic portions of the semiconductor device manufacturing method of the present embodiment will be described with reference to FIG. As shown in FIG. 5A, an opposite conductivity type boron (B) is applied to the N-type drift layer 2 exposed on the bottom surface of the trench 4 using the mask layer 13 made of an insulating film or the like used for forming the trench 4 as a mask. Etc.) is ion-implanted by a predetermined method.

  The dose amount of boron (B) at the time of ion implantation compensates the impurity concentration of the N-type drift layer 2 and forms an N − -type capacitance forming layer 2 a whose impurity concentration is lower than the impurity concentration of the N-type drift layer 2. Set to do. In FIG. 5A, boron (B) and the like are ion-implanted in the direction perpendicular to the bottom surface of the trench 4.

  The direction of ion implantation is not limited to being perpendicular to the bottom surface of the trench 4 and may be implanted at an angle in an oblique direction. Since the impurity concentration of the N-type drift layer 2 is lower than the impurity concentration of the P-type body layer 3, the dose amount of boron (B) or the like when forming the N-type capacitance forming layer 2a is not so large. This is because even if boron (B) or the like is implanted into the body layer 3 from the side walls of the trench 4, it does not cause a significant problem.

  Next, as shown in FIG. 5B, the mask layer 13 is removed, heat treatment such as predetermined sacrificial oxidation is performed, and the sacrificial oxide film is removed, and then the gate insulating film 5 is formed by a predetermined method. . In this case, as shown in FIG. 2D, the gate insulating film 5c at the bottom of the trench 4 may be changed to a thick gate insulating film 5b by performing the same process as in the first embodiment.

  Next, the gate electrode 6 is formed by the same process as in the first embodiment. As shown in FIG. 5B, the N − type capacitance forming layer 2 a activated in the N type drift layer 2 is formed by heat treatment after ion implantation or the like. The N − type capacitance forming layer 2 a is formed only on the bottom surface of the trench 4 and the N type drift layer 2 immediately below the bottom.

  Therefore, the N − type capacitance forming layer 2 a is transferred from the N + type source layer 7 to the N + type drain layer 1 a via the channel layer induced in the P type body layer 3 by the positive voltage applied to the gate electrode 6. There is no major obstacle to the flowing on-current. That is, the N− type capacitance forming layer 2a having a low impurity concentration formed on the bottom surface of the trench 4 does not increase the on-resistance of the power MOS transistor.

  Thereafter, as shown in FIG. 4, the power NMOS transistor according to this embodiment is completed through the same steps as those of the first embodiment. In the above description, the power NMOS transistor has been described as an example, but it goes without saying that the present invention can be similarly applied to a power PMOS transistor.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a N + type drain layer 2 N type drift layer
2a N-type capacitance forming layer 3 P-type body layer 4 Trench
5, 5a, 5b, 5c Gate insulating film 6 Gate electrode 7 N + type source layer 8 P + type contact layer 9 Interlayer insulating film 10 Source electrode
11 Polysilicon film 11a Polysilicon layer 11b Silicon oxide film
12, 12a Dummy oxide film 13 Mask layer

Claims (7)

Forming a first conductivity type drift layer on a first conductivity type semiconductor substrate;
Forming a second conductivity type body layer on the drift layer;
Forming a trench extending from the surface of the body layer into the drift layer;
Forming a dummy oxide film covering the inner wall of the trench, and then forming a polysilicon film on the semiconductor substrate including the dummy oxide film;
Etching back the polysilicon film to form a polysilicon layer on the bottom of the trench;
Sacrificial oxidation of the polysilicon layer and the sidewall of the trench, and forming a silicon oxide film on the sidewall and bottom of the trench;
Etching and removing all of the silicon oxide film formed on the sidewall of the trench and part of the silicon oxide film formed on the bottom surface of the trench;
Forming a gate insulating film covering the inner wall of the trench;
Forming a gate electrode embedded in the trench covered with the gate insulating film;
Forming a first conductivity type source layer and a second conductivity type contact layer on the body layer, and forming the gate insulating film thicker at a bottom surface of the trench than a side wall portion of the trench. A method of manufacturing a semiconductor device.   2. The semiconductor according to claim 1, wherein the polysilicon layer formed on the bottom surface of the trench is completely converted into a silicon oxide film by an oxidation process both during the sacrificial oxidation and when forming the gate insulating film. Device manufacturing method. Forming a first conductivity type drift layer on a first conductivity type semiconductor substrate;
Forming a second conductivity type body layer on the drift layer;
Forming a trench extending from the surface of the body layer into the drift layer;
Forming a first conductivity type capacitance forming layer on the drift layer exposed at the bottom of the trench;
Forming a gate insulating film covering the inner wall of the trench;
Forming a gate electrode embedded in the trench covered with the gate insulating film;
Forming a first conductivity type source layer and a second conductivity type contact layer on the body layer.   4. The method of manufacturing a semiconductor device according to claim 3, wherein the capacitance forming layer is formed by ion-implanting a second conductivity type impurity into the bottom surface of the trench.   5. The method of manufacturing a semiconductor device according to claim 3, wherein the gate insulating film is formed thicker at a bottom surface of the trench than a side wall portion of the trench. A first conductivity type drift layer formed on a first conductivity type semiconductor substrate;
A second conductivity type body layer formed on the drift layer;
A trench formed extending from the surface of the body layer into the drift layer;
A first conductivity type capacitance forming layer formed in the drift layer at the bottom of the trench;
A gate insulating film formed to cover the inner wall of the trench;
A gate electrode formed by embedding the trench covered with the gate insulating film;
A semiconductor device comprising: a first conductivity type source layer and a second conductivity type contact layer formed on the body layer. The semiconductor device according to claim 6, wherein the gate insulating film is formed thicker at a bottom surface of the trench than a side wall portion of the trench.

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