CN116504723A - Withstand voltage terminal structure, passivation method and power semiconductor device - Google Patents

Withstand voltage terminal structure, passivation method and power semiconductor device Download PDF

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CN116504723A
CN116504723A CN202310762805.9A CN202310762805A CN116504723A CN 116504723 A CN116504723 A CN 116504723A CN 202310762805 A CN202310762805 A CN 202310762805A CN 116504723 A CN116504723 A CN 116504723A
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layer
oxygen
silicon dioxide
semiconductor device
power semiconductor
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吴锦鹏
曾嵘
刘佳鹏
沈箫童
余占清
陈政宇
赵彪
黄琦欢
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Tsinghua University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/298—Semiconductor material, e.g. amorphous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture

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Abstract

The application provides a withstand voltage terminal structure, a passivation method and a power semiconductor device, wherein the withstand voltage terminal structure comprises: the thin silicon dioxide layer is arranged on the surface of the power semiconductor device and covers a preset protection area of the power semiconductor device; the oxygen-doped semi-insulating polycrystalline silicon layer is arranged on the thin silicon dioxide layer, and the width of the oxygen-doped semi-insulating polycrystalline silicon layer is smaller than or equal to that of the thin silicon dioxide layer; the silicon nitride layer completely covers the oxygen-doped semi-insulating polycrystalline silicon layer and the thin silicon dioxide layer; and a polyimide layer completely covering the silicon nitride layer. The passivation method is used for forming the voltage-resistant terminal structure. According to the voltage-resistant terminal structure, the passivation method and the power semiconductor device, leakage current can be reduced, foreign water vapor, alkali metal ions and other impurities are prevented from invading, chemical corrosion is prevented, mechanical buffer protection is realized, and voltage-resistant capability of the semiconductor device is improved.

Description

Withstand voltage terminal structure, passivation method and power semiconductor device
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a voltage-resistant terminal structure, a passivation method, and a power semiconductor device.
Background
The PN junction is a structure of the power semiconductor chip which mainly bears pressure resistance, so that the power semiconductor chip has high requirement on pressure resistance. However, for the whole wafer chip, if the PN junction extends to the edge of the chip, surface leakage and voltage-resistant failure are easily caused by defects, dangling bonds and the like; for discrete chips, since the curvature of the edge of the doped window manufactured by the planar process is large, electric field concentration is easy to occur at the edge of the doped window, and the overall withstand voltage level of the chip is reduced, a chip edge structure needs to be specially designed, and the structure is also called a junction terminal. Junction termination techniques mainly include edge bevel (Bevel Edge Terminations), field limiting rings (Field Limiting Ring, FLR), field Plates (FP), junction termination extensions (Junction Terminal Extension, JTE), lateral metamorphic doping (Variable Lateral Doping, VLD), etc.
The existing edge bevel technology uses a mechanical grinding process, so that the surface of a chip is easily damaged; the angle grinding precision needs to be strictly controlled, otherwise, the electric field distribution is different from the expected electric field distribution, the withstand voltage level is reduced, and the process requirement is high; the area of the terminal occupying the chip has a further optimized space.
In the existing VLD structure terminal, the edge passivation layer is mostly a composite layer of silicon oxide and silicon nitride, for example, in patent CN112271210A and patent CN114141858A, the passivation layers are both silicon oxide and silicon nitride, the silicon oxide can store carriers to cause charge accumulation, the existing fixed positive charge easily causes pressure drop, and the silicon nitride film is fragile in physical property, has larger stress and is easy to break when the film is thicker.
Disclosure of Invention
Aiming at the problems in the prior art, the application provides a voltage-resistant terminal structure and a passivation method, which can at least partially solve the problems in the prior art.
In a first aspect, the present application provides a voltage-resistant termination structure applied to a power semiconductor device, including:
the thin silicon dioxide layer is arranged on the surface of the power semiconductor device and covers a preset protection area of the power semiconductor device;
the oxygen-doped semi-insulating polycrystalline silicon layer is arranged on the thin silicon dioxide layer, and the width of the oxygen-doped semi-insulating polycrystalline silicon layer is smaller than or equal to that of the thin silicon dioxide layer;
the silicon nitride layer completely covers the oxygen-doped semi-insulating polycrystalline silicon layer and the thin silicon dioxide layer;
and the polyimide layer completely covers the silicon nitride layer.
Wherein the thin silicon dioxide layer has a thickness of less than 100nm.
Wherein the oxygen content of the oxygen-doped semi-insulating polysilicon layer near the silicon nitride layer is higher than the oxygen content near the thin silicon dioxide layer.
Wherein the thickness of the oxygen doped semi-insulating polysilicon layer is 100-500nm.
Wherein, still include:
and the water vapor isolation structures are arranged at two sides of the oxygen-doped semi-insulating polycrystalline silicon layer at intervals and are completely covered by the silicon nitride layer.
Wherein the thickness of the silicon nitride layer is 100-500nm.
Wherein the thickness of the polyimide layer is not less than 10 μm.
In a second aspect, the present application provides a passivation method for forming a voltage-tolerant termination structure, comprising:
forming a thin silicon dioxide layer on the surface of the power semiconductor device, so that the thin silicon dioxide layer covers a preset protection area of the power semiconductor device;
forming an oxygen-doped semi-insulating polycrystalline silicon layer on the thin silicon dioxide layer, so that the width of the oxygen-doped semi-insulating polycrystalline silicon layer is smaller than or equal to the width of the thin silicon dioxide layer;
forming a silicon nitride layer so that the silicon nitride layer completely covers the thin silicon dioxide layer and the semi-insulating polysilicon layer;
forming a polyimide layer to completely cover the silicon nitride layer.
Wherein, the forming a thin silicon dioxide layer on the surface of the power semiconductor device comprises:
and forming a thin silicon dioxide layer by adopting a dry oxygen oxidation method, so that the thickness of the thin silicon dioxide layer is not more than 100nm.
Wherein the forming of the oxygen doped semi-insulating polysilicon layer on the thin silicon dioxide layer comprises:
forming an oxygen-doped semi-insulating polycrystalline silicon layer on the thin silicon dioxide layer by using silane and laughing gas in a preset proportion, so that the oxygen content of the oxygen-doped semi-insulating polycrystalline silicon layer close to the silicon nitride layer is higher than that of the oxygen content of the oxygen-doped semi-insulating polycrystalline silicon layer close to the thin silicon dioxide layer; the preset proportion is 2:1 to 6: 1;
and annealing the oxygen-doped semi-insulating polycrystalline silicon layer.
Wherein, before forming a silicon nitride layer, the method further comprises:
and carrying out photoetching treatment on the thin silicon dioxide layer and the part of the oxygen-doped semi-insulating polycrystalline silicon layer outside the preset protection area at intervals to obtain a water vapor isolation structure.
Wherein, the time interval between the formation of a silicon nitride layer and the annealing operation is smaller than a preset time interval.
Wherein forming a polyimide layer comprises:
covering polyimide glue on the silicon nitride layer, and carrying out photoetching and high-temperature curing treatment to obtain a polyimide layer; the thickness of the polyimide layer is not less than 10 μm.
In a third aspect, the present application provides a power semiconductor device, including the voltage-withstanding terminal structure according to any one of the above embodiments.
Wherein the power semiconductor device comprises a lateral varying doping structure.
According to the voltage-resistant terminal structure, the passivation method and the power semiconductor device, a thin silicon dioxide layer of a preset protection area of the power semiconductor device is covered; an oxygen doped semi-insulating polysilicon layer disposed on the thin silicon dioxide layer; the polyimide layer completely covers the silicon nitride layer of the oxygen-doped semi-insulating polycrystalline silicon layer and the thin silicon dioxide layer and the polyimide layer completely covers the silicon nitride layer, so that the surface leakage current can be reduced, an external electric field is shielded, the surface potential of a preset protection area is smoothed, the invasion of metal ions and water vapor is prevented, the voltage withstand capability of the power semiconductor device is improved, the high breakdown voltage and the high insulation strength are realized, in addition, the silicon nitride layer can be protected by the arrangement of the polyimide layer, and the mechanical buffering is realized.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a semiconductor chip using an edge bevel structure according to one embodiment of the present application;
fig. 2A to 2H are schematic cross-sectional views of the voltage-tolerant terminal structure shown in fig. 2H at various stages according to an embodiment of the present application using the passivation method provided herein;
FIGS. 3A-3F are schematic cross-sectional views of forming the lateral metamorphic doping structure at various stages according to one embodiment of the present application;
FIG. 4 is a top view of the chip shown in FIGS. 2A-2H;
fig. 5 is a schematic structural diagram of a power semiconductor device according to an embodiment of the present application.
Symbol description
110. Planar structural region
120. Edge corner grinding area
210. Active region
220. Termination region
230. Preset protection area
201. Thin silicon dioxide layer
202. Oxygen doped semi-insulating polysilicon (SIPOS) layer
203. 206, 302 photoresist
204. Water vapor isolation structure
205. Silicon nitride layer
207. Polyimide layer
301. Silicon dioxide mask layer
510. Planar structural region
520. Bevel structure region
530. Withstand voltage terminal structure
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in further detail with reference to the accompanying drawings. The exemplary embodiments of the present invention and their descriptions herein are for the purpose of explaining the present invention, but are not to be construed as limiting the invention. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be arbitrarily combined with each other.
The application provides a voltage-resistant terminal structure, a passivation method and a power semiconductor device. In the prior art, junction termination technologies of power semiconductor devices mainly include edge bevel (Bevel Edge Terminations), field limiting rings (Field Limiting Ring, FLR), field Plates (FP), junction termination extensions (Junction Terminal Extension, JTE), lateral metamorphism (Variable Lateral Doping, VLD), and the like. A schematic diagram of a semiconductor chip using an edge bevel is shown in fig. 1, where the chip includes, from bottom to top, a p+ emitter, an n buffer region, an n-base region, a p base region, a p+ base region, and an n+ emitter, and the chip can be divided into a planar structure region 110 and an edge grinding angle region 120. The VLD structure can be used for replacing an edge bevel angle technology, the chip surface is protected, the terminal structure occupies smaller chip area, but most of the edge passivation layers of the existing VLD structure adopt a composite layer of silicon oxide and silicon nitride, the silicon oxide can store carriers to cause charge accumulation, the existing fixed positive charge easily causes pressure drop, and the silicon nitride film is fragile in physical property, has larger stress and is easy to break when the film is thicker. The application can reduce leakage flow, block foreign water vapor, alkali metal ion and other impurity invasion, prevent chemical corrosion and realize mechanical buffer protection by arranging the composite passivation layer of a thin Silicon dioxide layer, an oxygen-doped Semi-Insulating polycrystalline Silicon layer (Semi-Insulating Poly-Silicon, SIPOS), a Silicon nitride layer (Si 3N 4) and a polyimide layer (PI).
The voltage-resistant terminal structure and the passivation method provided by the application can be used for protecting other preset protection areas needing to be protected of the power semiconductor device besides the VLD structure used for protecting the power semiconductor device, and the range of the preset protection areas can be set according to actual needs.
Fig. 2A to 2H are schematic cross-sectional views illustrating various stages of forming the voltage-tolerant termination structure shown in fig. 2H using the passivation method provided herein, according to some embodiments of the present application.
Referring to fig. 2A, a power semiconductor device is provided, and the power semiconductor device includes a p+ emitter, an n buffer region, an n-base region, a p-base region, a p+ base region, and an n+ doped region, but the application is not limited thereto. The power semiconductor may be divided into an active region 210 and a termination region 220, and a thin silicon oxide layer 201 is formed on the surface of the power semiconductor device by a dry oxygen oxidation method, and the time for forming the thin silicon oxide layer is controlled such that the thickness of the thin silicon oxide layer 201 does not exceed 100nm.
In the embodiment shown in fig. 2A, the power semiconductor device includes a chip having a lateral varying doping (VLD) structure, and cross-sectional views of the chip at various stages in forming the lateral varying doping (VLD) structure are shown in fig. 3A to 3F.
As shown in fig. 3A, a silicon dioxide mask layer 301 is first grown on the chip with the active doped region formed thereon, and then, referring to fig. 3B, a photoresist layer 302 is covered on the silicon dioxide mask layer 301. As shown in fig. 3C, the photolithographic development is performed in accordance with a preset pattern, and the width of the opening of the photoresist 302 after development gradually decreases from the end near the active region to the end far from the active region. The silicon dioxide mask layer 301 is etched using a BOE solution to form an ion diffusion window as shown in FIG. 3D, and photoresist removal is performed to obtain the structure shown in FIG. 3E. And performing boron ion implantation based on the ion diffusion window, and performing furnace tube high-temperature junction pushing to obtain the expected VLD doping structure as shown in fig. 3F. The wafer surface is cleaned with the BOE solution and the silicon dioxide mask layer 301 is removed to obtain the wafer of FIG. 2A for producing a thin silicon dioxide layer, wherein the pre-set protection region of the wafer comprises the VLD region and the n+ doped region of the wafer surface.
Although the power semiconductor device of fig. 2A is a discrete chip including a lateral varying doping (VLD) structure, the present application is not limited thereto.
After forming the thin silicon oxide layer 201, as shown in fig. 2B, an oxygen doped semi-insulating polysilicon (SIPOS) layer 202 is formed on the thin silicon oxide layer 201 using a predetermined ratio of silane and laughing gas at 600-700 c using a Low Pressure Chemical Vapor Deposition (LPCVD).
In one embodiment, the ratio of silane to laughing gas is 2:1 to 6:1, the oxygen content of the oxygen-doped semi-insulating polysilicon layer 202 near the silicon nitride layer 205 (see fig. 2F-2H) can be higher than the oxygen content of the thin silicon dioxide layer 201 by adjusting the mixture ratio of silane and laughing gas. The specific way of implementing the oxygen content change in the oxygen-doped semi-insulating polysilicon layer is not limited in this application, for example, as shown in fig. 2C, the oxygen-doped semi-insulating polysilicon layer 202 may be further divided into two layers, where a layer 202a near the silicon nitride layer 205 has a higher oxygen content than a layer 202b near the thin silicon dioxide layer, and the number of layers of the divided semi-insulating polysilicon layer may be adjusted as required. In addition, the oxygen content of the oxygen-doped semi-insulating polysilicon layer can be changed by gradually changing the mixture ratio of silane and laughing gas when the oxygen-doped semi-insulating polysilicon layer 202 is formed.
In one embodiment, the oxygen-doped semi-insulating polysilicon layer 202 is adjacent to the surface of the thin silicon dioxide layer and has an oxygen content of 10% -25%; the oxygen content of the oxygen-doped semi-insulating polycrystalline silicon layer is 25-35% near the surface of the silicon nitride layer, and the thickness of the oxygen-doped semi-insulating polycrystalline silicon layer is 100-500nm.
The SIPOS material absorbs the movable ions by utilizing the semi-insulating property of the SIPOS material, and can form a space charge area to shield an external electric field; and meanwhile, the surface potential of the terminal area is smoothed by utilizing the resistance characteristic of the terminal area, so that the peak field intensity is reduced, and the breakdown possibility is reduced. The longitudinal change of the oxygen content of the SIPOS is controlled, the low oxygen content is used near the thin silicon dioxide layer to absorb carriers of the bottom oxide layer, and the high oxygen content is used near the silicon nitride layer to provide insulation strength.
Because the SIPOS is a semi-insulating material, a current path exists, leakage current is possibly overlarge, and a thin SiO2 material is additionally arranged below the SIPOS material (namely, is in direct contact with the surface of the power semiconductor device), so that surface leakage current can be reduced under high withstand voltage, and meanwhile, the sectional area of the current path can be further reduced by strictly limiting the thickness of the thin SiO2 layer to be not more than 100nm.
In one embodiment, an annealing operation may be performed on the formed oxygen-doped semi-insulating polysilicon layer. The annealing temperature is 600-700 ℃ and the time is 1-4 hours.
The annealing operation can reduce the risk of stripping the oxygen-doped semi-insulating polycrystalline silicon layer, is favorable for improving the hard turning characteristic of the withstand voltage curve, namely, in a certain voltage range, the leakage current on the surface of the chip is slowly increased, the leakage current is smaller, and when the voltage exceeds the limit, the leakage current is obviously increased.
Thereafter, the excess portions of the thin silicon dioxide layer 201 and the oxygen-doped semi-insulating polysilicon layer 202 are removed, as shown in fig. 2D-2E. A layer of photoresist 203 is grown on the oxygen-doped semi-insulating polysilicon layer 202, and is subjected to photoetching development, so that the position of the residual photoresist 203 is positioned above a preset protection area of the chip, and the width of the photoresist 203 is larger than the width of the preset protection area on the surface of the chip. The oxygen-doped semi-insulating polysilicon layer 202 and the thin silicon dioxide layer 201 are etched using an etchant. In this embodiment, the preset protection region of the chip includes a VLD region and an n+ doped region.
In one embodiment, during the photolithography development, a portion of the photoresist 203 may be reserved at intervals except for the portion above the preset protection area of the chip, and after etching the oxygen-doped semi-insulating polysilicon layer 202 and the thin silicon dioxide layer 201 with an etching solution, the moisture isolation structures 204 located on both sides of the oxygen-doped semi-insulating polysilicon layer and the thin silicon dioxide layer are obtained.
Fig. 4 is a top view of the chip shown in fig. 2A to fig. 2H, as shown in fig. 4, the moisture isolation structure 204 surrounds the active region 210 in the chip and is disposed on two sides of the preset protection region 230, at this time, the moisture intrusion path is shown by an arrow in the drawing, and the number of the moisture isolation structures 204 on two sides of the oxygen doped semi-insulating polysilicon layer 202 and the thin silicon dioxide layer 201 can be adjusted according to the actual situation, which is not limited in the specific number of the moisture isolation structures 204 in the present application.
Because the oxygen-doped semi-insulating polycrystalline silicon layer and the thin silicon dioxide layer are formed through deposition and are subjected to annealing operation, the combination of the water vapor isolation structure and the surface of the chip is compact, the water vapor invasion path entering along the gap between the outer layer and the surface of the chip can be prolonged through the water vapor isolation structure, the oxygen-doped semi-insulating polycrystalline silicon layer is protected, the water absorption failure of the oxygen-doped semi-insulating polycrystalline silicon layer is prevented, and the long-term reliability of a device is enhanced.
Next, after the oxygen-doped semi-insulating polysilicon layer 202 is processed, a silicon nitride layer 205 is grown by Plasma Enhanced Chemical Vapor Deposition (PECVD), as shown in fig. 2F. And a photoresist 206 is formed on the silicon nitride layer 205, and the excess portion is removed by photolithography and development, so that the coverage of the remaining photoresist 206 is larger than the coverage of the oxygen-doped semi-insulating polysilicon layer 202 and the thin silicon dioxide layer 201. The coverage of the remaining photoresist 206 should also be greater when the moisture barrier 204 is present than when the outermost moisture barrier 204 is present. In this embodiment, the coverage of the photoresist 206 should also be within the termination region 220.
In one embodiment, the time interval between the growth of the silicon nitride layer 205 and the completion of the processing of the oxygen-doped semi-insulating polysilicon layer 202 is no more than 6 hours, so as to prevent the oxygen-doped semi-insulating polysilicon layer 202 from being exposed to air and water vapor for a long time, thereby changing physical and chemical properties and even failing in denaturation.
In one embodiment, the temperature at which the silicon nitride layer 205 is grown is 300-400 c and the thickness of the silicon nitride layer 205 is 100-500nm.
As shown in fig. 2G, the silicon nitride layer 205 is dry etched based on the formed photoresist 206, and photoresist removal is performed, so that the resulting silicon nitride layer 205 completely covers the oxygen-doped semi-insulating polysilicon layer 202 and the thin silicon dioxide layer 201. The silicon nitride layer 205 should also completely cover each moisture barrier 204 when the moisture barrier 204 is present.
As shown in fig. 2H, the polyimide gel is covered on the silicon nitride layer 205, and a high-temperature curing treatment is performed to form a polyimide layer 207, and the polyimide layer 207 completely covers the silicon nitride layer 205, thereby obtaining a final voltage-resistant terminal structure.
In one embodiment, the curing temperature is 250-350 ℃ and the polyimide layer thickness is greater than 10mm.
By providing the silicon nitride layer, it is possible to mask the invasion of metal ions such as sodium, potassium, etc. into the chip surface, resulting in unstable breakdown voltage. The polyimide layer is arranged on the silicon nitride layer (namely the outermost layer), so that the invasion of external water vapor can be blocked, the insulation strength is provided, and meanwhile, the polyimide layer can realize mechanical buffering on the surface of the chip due to compact silicon nitride film and relatively fragile physical property, so that the lower structure is protected. The silicon nitride layer and the polyimide layer completely cover the lower layer structure, and can protect the oxygen-doped semi-insulating polycrystalline silicon layer from being invaded by water vapor so as to prevent oxygen content change and even complete denaturation of the oxygen-doped semi-insulating polycrystalline silicon layer and lose the original physical and chemical properties.
Accordingly, the present application also provides a power semiconductor device using the voltage withstand terminal structure formed in each of the above embodiments. For example, the discrete chip with VLD structure shown in fig. 2H, in which the preset protection regions are the VLD structure and n+ doped regions of the chip surface.
In another embodiment, the power semiconductor device may also be a whole wafer chip, as shown in fig. 5, where the chip includes a planar structure region 510 covered by an electrode and an oblique angle structure region 520 covered by an electrodeless, the oblique angle structure region 520 covered by the electrodeless chip may be set as a preset protection region, and a voltage-withstanding terminal structure 530 is formed on the preset protection region.
In addition, the power semiconductor device can be provided with a structure such as a cutoff ring according to actual needs, and the application is not limited to the structure.
In the description of the present specification, reference to the terms "one embodiment," "one particular embodiment," "some embodiments," "for example," "an example," "a particular example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.

Claims (15)

1. A voltage-resistant termination structure applied to a power semiconductor device, comprising:
the thin silicon dioxide layer is arranged on the surface of the power semiconductor device and covers a preset protection area of the power semiconductor device;
the oxygen-doped semi-insulating polycrystalline silicon layer is arranged on the thin silicon dioxide layer, and the width of the oxygen-doped semi-insulating polycrystalline silicon layer is smaller than or equal to that of the thin silicon dioxide layer;
the silicon nitride layer completely covers the oxygen-doped semi-insulating polycrystalline silicon layer and the thin silicon dioxide layer;
and the polyimide layer completely covers the silicon nitride layer.
2. The voltage tolerant termination structure of claim 1 wherein the thin silicon dioxide layer has a thickness of less than 100nm.
3. The voltage termination structure of claim 1, wherein the oxygen-doped semi-insulating polysilicon layer has a higher oxygen content adjacent the silicon nitride layer than adjacent the thin silicon dioxide layer.
4. The voltage tolerant termination structure of claim 1 wherein the oxygen-doped semi-insulating polysilicon layer has a thickness of 100-500nm.
5. The pressure resistant termination structure of claim 1, further comprising:
and the water vapor isolation structures are arranged at two sides of the oxygen-doped semi-insulating polycrystalline silicon layer at intervals and are completely covered by the silicon nitride layer.
6. The voltage-resistant termination structure of claim 1, wherein the silicon nitride layer has a thickness of 100-500nm.
7. The pressure-resistant termination structure according to claim 1, wherein the thickness of the polyimide layer is not less than 10 μm.
8. A passivation method for forming a voltage tolerant termination structure, comprising:
forming a thin silicon dioxide layer on the surface of the power semiconductor device, so that the thin silicon dioxide layer covers a preset protection area of the power semiconductor device;
forming an oxygen-doped semi-insulating polycrystalline silicon layer on the thin silicon dioxide layer, so that the width of the oxygen-doped semi-insulating polycrystalline silicon layer is smaller than or equal to the width of the thin silicon dioxide layer;
forming a silicon nitride layer so that the silicon nitride layer completely covers the thin silicon dioxide layer and the semi-insulating polysilicon layer;
forming a polyimide layer to completely cover the silicon nitride layer.
9. The passivation method of claim 8, wherein forming a thin silicon dioxide layer on the surface of the power semiconductor device comprises:
and forming a thin silicon dioxide layer by adopting a dry oxygen oxidation method, so that the thickness of the thin silicon dioxide layer is not more than 100nm.
10. The passivation method of claim 8, wherein forming an oxygen doped semi-insulating polysilicon layer on the thin silicon dioxide layer comprises:
forming an oxygen-doped semi-insulating polycrystalline silicon layer on the thin silicon dioxide layer by using silane and laughing gas in a preset proportion, so that the oxygen content of the oxygen-doped semi-insulating polycrystalline silicon layer close to the silicon nitride layer is higher than that of the oxygen content of the oxygen-doped semi-insulating polycrystalline silicon layer close to the thin silicon dioxide layer; the preset proportion is 2:1 to 6: 1;
and annealing the oxygen-doped semi-insulating polycrystalline silicon layer.
11. The passivation method of claim 8, further comprising, prior to forming a silicon nitride layer:
and carrying out photoetching treatment on the part of the thin silicon dioxide layer and the oxygen-doped semi-insulating polycrystalline silicon layer outside the preset protection area at intervals to obtain a water vapor isolation structure.
12. The passivation method of claim 10, wherein the time interval between the forming a silicon nitride layer and the annealing operation is less than a predetermined time interval.
13. The passivation method of claim 8, wherein forming a polyimide layer comprises:
covering polyimide glue on the silicon nitride layer, and carrying out photoetching and high-temperature curing treatment to obtain a polyimide layer; the thickness of the polyimide layer is not less than 10 μm.
14. A power semiconductor device comprising the voltage withstand termination structure of any one of claims 1-7.
15. The power semiconductor device of claim 14, wherein said power semiconductor device comprises a lateral varying doping structure.
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JPH04212468A (en) * 1990-11-08 1992-08-04 Fuji Electric Co Ltd High breakdown strength semiconductor device
CN105244326A (en) * 2014-06-23 2016-01-13 北大方正集团有限公司 Passivation layer structure of power device and manufacturing method thereof
CN105390396A (en) * 2015-10-27 2016-03-09 株洲南车时代电气股份有限公司 Method for fractionally depositing semi-insulating polycrystalline silicon based on IGBT and IGBT terminal structure
CN106252244A (en) * 2016-09-22 2016-12-21 全球能源互联网研究院 A kind of terminal passivating method and semiconductor power device
CN106992207A (en) * 2017-05-02 2017-07-28 株洲中车时代电气股份有限公司 A kind of power semiconductor terminal structure and power semiconductor
CN217361590U (en) * 2022-02-28 2022-09-02 华为数字能源技术有限公司 Terminal structure, power semiconductor device and electronic equipment

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04212468A (en) * 1990-11-08 1992-08-04 Fuji Electric Co Ltd High breakdown strength semiconductor device
CN105244326A (en) * 2014-06-23 2016-01-13 北大方正集团有限公司 Passivation layer structure of power device and manufacturing method thereof
CN105390396A (en) * 2015-10-27 2016-03-09 株洲南车时代电气股份有限公司 Method for fractionally depositing semi-insulating polycrystalline silicon based on IGBT and IGBT terminal structure
CN106252244A (en) * 2016-09-22 2016-12-21 全球能源互联网研究院 A kind of terminal passivating method and semiconductor power device
CN106992207A (en) * 2017-05-02 2017-07-28 株洲中车时代电气股份有限公司 A kind of power semiconductor terminal structure and power semiconductor
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