CN117080245A - Power semiconductor device and preparation method thereof - Google Patents
Power semiconductor device and preparation method thereof Download PDFInfo
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- CN117080245A CN117080245A CN202311175979.1A CN202311175979A CN117080245A CN 117080245 A CN117080245 A CN 117080245A CN 202311175979 A CN202311175979 A CN 202311175979A CN 117080245 A CN117080245 A CN 117080245A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Abstract
The invention relates to a power semiconductor device and a preparation method thereof, in order to provide a chip structure with high reliability, the invention reduces the surface stress of the peripheral area of the chip and improves the breakdown voltage and the reliability of a terminal area by being provided with more than one source area, more than one terminal area, more than one floating groove area and a cut-off area positioned at the outermost periphery of the chip.
Description
Technical Field
The invention relates to a structure of a power semiconductor device, in particular to a trench type field effect transistor device and a manufacturing method thereof.
Background
The related art background of the conventional shielded gate trench type field effect transistor will be described below. It is noted that corresponding positional words such as "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "vertical" as described in this document are relative positions corresponding to the reference drawings. The fixing direction is not limited in the specific implementation. It should be noted that the devices in the drawings are not necessarily drawn to scale. The straight lines shown in the boundaries of the doped regions and trenches in the drawings, and the sharp corners formed by the boundaries, are generally not straight lines and precise angles in practical applications.
The shielded gate trench type field effect transistor has the characteristics of low on-resistance and high switching speed. Fig. 1 is a schematic cross-sectional view of an N-type shielded gate trench fet of conventional structure in which a deeper trench depth and a thicker trench oxide layer are required as the withstand voltage of the shielded gate trench fet is increased, and a trench depth of 7-12um and a trench oxide layer of 1-2um are typically required in a medium voltage shielded gate trench fet design of greater than 150V. The deep trenches arranged in high density are easy to generate larger stress in the processes of thermal process, filling and the like of device chip manufacture, and cause wafer warpage, thereby influencing the stability of the manufacturing process. One approach has been to form multiple regions of different trench orientation within a chip to mitigate wafer warpage. However, the surface stresses in different directions are generated in the different regions, and mechanical deformation is likely to occur at the junctions of the different regions, so that cracks are generated.
In a shielded gate trench type field effect transistor device, it is necessary to ensure that the withstand voltage of a termination region located at the outermost periphery is higher than that of an active region, the termination region is typically formed of a plurality of deep trenches surrounding the active region, which are typically deeper than the trenches in the active region. The deep trench structure easily causes severe stress at the chip surface of the termination region, easily causes delamination of the surface oxide layer and the passivation layer of the chip edge region, causes intrusion of moisture or foreign contaminant ions into the inside of the semiconductor, and forms a leakage path at the upper surface of the semiconductor of the chip edge region, thus requiring a highly reliable chip peripheral structure.
Disclosure of Invention
In order to solve the above-mentioned problems, the present invention provides the following technical solutions:
the invention aims at providing a power semiconductor device, which comprises a drain electrode metal layer positioned at the bottom, a first conductive type heavily doped substrate layer positioned on the drain electrode metal layer, a first conductive type first epitaxial layer positioned on the first conductive type heavily doped substrate layer, a second epitaxial layer, a groove region and a source electrode metal layer and a grid electrode metal layer positioned on the upper surface of the device, wherein the drain electrode metal layer is positioned on the bottom; the semiconductor device is characterized by being provided with more than one active area, more than one terminal area surrounding the active area, more than one floating groove area surrounding all the active areas and the terminal areas and positioned at the periphery of the chip, and a cut-off area surrounding the outermost periphery of the chip;
the active region comprises a series of cell grooves which are parallel to each other, the cell grooves comprise a gate electrode positioned above the grooves and a shielding gate electrode positioned below the grooves, a first conductive type lightly doped drift region and a second conductive type doped body region positioned above the first conductive type lightly doped drift region are arranged between the cell grooves, and the active region comprises at least two active regions formed by the cell grooves in different directions in one device;
the terminal area comprises more than one section of terminal grooves which are parallel to each other, a shielding gate electrode is filled in the terminal grooves, and the shielding gate electrode is connected to source metal on the upper surface of the device or other electric potentials between the source electrode and the drain electrode;
the floating groove area comprises more than one section of floating grooves which are parallel to each other;
the cut-off region comprises at least one cut-off groove and a cut-off metal layer positioned on the upper surface of the device in the region, wherein the cut-off groove is at least provided with a shielding gate electrode, and the shielding gate electrode is connected to the cut-off metal layer on the upper surface of the semiconductor.
Preferably, the floating grooves are filled with low-stress insulating materials, at least one floating groove is internally provided with a floating electrode, and the floating electrode is connected to a floating potential.
Preferably, the floating grooves comprise a first type of parallel floating grooves parallel to the terminal grooves and a second type of vertical floating grooves perpendicular to the adjacent terminal grooves.
Further, the floating electrode is arranged in the second type parallel floating groove, and/or extends towards the direction inside the chip.
Preferably, the floating electrode has a width and depth equal to the width and depth of the termination trench.
Preferably, a second conductive type floating injection region is arranged below the floating groove.
Further, the periphery of the floating groove region is surrounded by a second conductive type floating injection region.
Preferably, the distance between the floating grooves in the floating groove region gradually increases in a direction away from the central region of the chip.
Preferably, the floating electrode is connected to the cut-off metal layer at a corner of the quadrangular chip.
Preferably, the floating grooves and the cell grooves are oriented differently.
Preferably, the angle between the floating groove and one of the cell grooves is 45 ℃.
Preferably, an extension groove with the same direction as the cell groove is arranged at the end of at least one cell groove in the active area, the depth and width of the extension groove are not larger than those of the cell groove, and the extension groove is connected to the terminal groove.
Preferably, the active area is provided with more than one inner ring terminal groove connected with any two cell grooves with more than one cell groove in the middle, and more than one outer ring terminal groove connected with the cell grooves on two sides of each inner ring terminal groove and surrounding the inner ring terminal groove, and the structures of the inner ring terminal groove and the outer ring terminal groove are the same as those of the terminal grooves.
Preferably, the cell trenches in adjacent active regions are oriented perpendicular to each other.
Another object of the present invention is to provide a method for manufacturing a power semiconductor device, the method comprising the steps of:
a first step of forming a first conductivity type epitaxial layer on a first conductivity type semiconductor substrate;
forming a nitride hard mask layer and an oxide hard mask layer above the nitride hard mask layer on the upper surface of the semiconductor through deposition and photoetching, and then etching a semiconductor groove;
thirdly, forming a shielding gate isolation layer in the cell groove and the terminal groove;
fourthly, firstly depositing a shielding gate electrode material, and then performing chemical mechanical polishing to remove the shielding gate electrode material and the shielding gate isolation layer material on the upper surface of the semiconductor, wherein the polishing is stopped on the nitride hard mask layer on the upper surface of the semiconductor;
fifth, photoetching is carried out, and then the shielding gate isolation layer in the cell groove is etched under the protection of photoresist;
after etching, the thickness of the shielding gate isolation layer remained on the side wall of the etching hole in the cell groove is not lower than 2000A;
forming a gate oxide layer and a gate electrode;
seventh, forming a channel doping region, forming a surface oxide layer, and then forming a contact hole in the surface oxide layer, a source metal layer, a gate metal layer and a cut-off metal layer; the channel doped region includes at least a second conductivity type doped body region located between the cell trenches.
Preferably, in the first step, a polysilicon layer is formed under the first conductive type semiconductor substrate, an oxide layer is formed under the polysilicon layer, the polysilicon layer is first formed under the oxide layer and is thermally oxidized to form a thick oxide layer, and the polysilicon layer, the oxide layer, and the thick oxide layer are removed in a subsequent process.
Preferably, in the fifth step, the photoresist only protects the material of the shielding gate isolation layer on the termination trench and the floating trench, the shielding gate isolation layer on the upper portion of the cell trench is removed, and the inter-electrode isolation layer is formed by thermal oxidation in a subsequent process.
The invention provides a field effect tube structure, which can reduce the surface stress of a peripheral area of a chip and ensure the breakdown voltage and reliability of a terminal area.
Drawings
Fig. 1 is a schematic cross-sectional view of a prior art shielded gate trench field effect transistor device.
Fig. 2 is a schematic cross-sectional view of one embodiment of the device of the present invention.
Fig. 3 is a schematic cross-sectional view of another embodiment of the device of the present invention.
Fig. 4 is a schematic cross-sectional view of another embodiment of the device of the present invention.
Fig. 5 is a schematic cross-sectional view of another embodiment of the device of the present invention.
Figure 6 is a top view of a trench structure of one embodiment of the device of the present invention.
Fig. 7 is a top view of a trench structure of another embodiment of the device of the present invention.
Fig. 8 is a top view of a trench structure of another embodiment of the device of the present invention.
Fig. 9 is a top view of the structure of a cell trench and termination trench of one embodiment of the device of the present invention.
Fig. 10A is a top view of the structure of a cell trench and termination trench of another embodiment of the device of the present invention.
Fig. 10B is a top view of the structure of a cell trench and termination trench and gate metal layer of one embodiment of the device of the present invention.
Fig. 11-16 are key steps in the manufacturing flow of one embodiment of the device of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the drawings and examples. Note that, in the following description of the shielded gate trench type field effect transistor device and the method of manufacturing the same of the present invention, a semiconductor substrate of the shielded gate trench type field effect transistor device is considered to be composed of a silicon (Si) material. However, the substrate may be formed of any other material suitable for manufacturing a shielded gate trench field effect transistor, such as gallium nitride (GaN), silicon carbide (SiC), and the like. In the following description, the conductivity type of the semiconductor region is classified into P-type (second conductivity type) and N-type (first conductivity type), and one P-type conductivity type semiconductor region may be formed by doping one or several impurities into the original semiconductor region, which may be, but are not limited to: boron (B), aluminum (Al), gallium (Ga), and the like. An N-type conductive semiconductor region can be formed by forming a semiconductor layer on the original semiconductor layerThe region is doped with one or more impurities, which may be, but are not limited to: phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), protons (H) + ) Etc. In the following description, a heavily doped P-type conductive semiconductor region is labeled P + A region, a heavily doped N-type conductivity semiconductor region labeled N + A zone. For example, in a silicon material substrate, the impurity concentration of a heavily doped region is typically 1X 10 19 cm -3 Up to 1X 10 21 cm -3 Between them. Those skilled in the art will appreciate that the P-type (second conductivity type) and N-type (first conductivity type) of the present invention may be interchanged.
Example 1
Fig. 2 is a cross-sectional view corresponding to a broken line a in fig. 6, showing a structure of a semiconductor field effect transistor device according to a first embodiment. The method comprises the following steps: a drain metal layer (212) at the bottom; n on the drain metal layer + A substrate layer (201); located at N + An N-type first epitaxial layer (200) over the substrate layer, and a second epitaxial layer (204) over the first epitaxial layer.
The following regions can be divided by trench structure and distribution: an active region (230), a termination region (231), a floating trench region (232), and a cut-off region (233).
The device includes two or more active regions (230) each containing a series of cell trenches (220) in the same direction and parallel to each other. The cell trench (220) within the overall device has a minimum of two different trench orientations. The cell trench (220) includes a gate electrode (206) located above the trench and a shield gate electrode (207) located below the trench. The gate electrode (206) is isolated from the trench sidewalls by a gate oxide layer. An inter-electrode isolation layer is provided between the gate electrode (206) and the shield gate electrode (207). Wherein the shield gate electrode (207) is connected to a source metal (211) on the upper surface of the device. In addition, a shield gate isolation layer (215) is provided between the shield gate electrode (207) and the trench sidewall. A P-doped body region (208) is located on the upper surface of the device between the cell trenches. In one embodiment, under the P-doped body regionSquare has N - A type drift region (205).
The termination trench region (231) is composed of one or several sections of termination trenches (221) parallel to each other. And the termination trench (221) encloses the centrally located active region (230). The termination trench has the same depth and width as the cell trench and is filled with a shield gate electrode (207) with a shield gate isolation layer (215) between the shield gate electrode (207) and the trench sidewalls. Wherein the shield gate electrode (207) within the termination trench is connected to source metal (211) or other source-drain potential on the upper surface of the device.
A floating trench region (232) is located at the periphery of the chip and surrounds the plurality of active regions (230) and termination regions (231). The floating trench region (232) has a plurality of independent and parallel floating trenches (222) therein. The width and depth of the floating trench are no greater than the termination trench (221). The length of the floating trench (222) is generally less than the cell trench (220). The plurality of floating trenches (232) are typically spaced apart from one another by a distance greater than the spacing of the cell trenches (220) from one another, and the spacing is different at different locations of the chip. In one embodiment, the floating trench (222) is filled with a low stress insulating material (216). In one embodiment, a floating electrode (217) is contained within the floating trench (222), the floating electrode (217) typically being connected to a floating potential. The floating electrode may be located at an upper portion of the trench, and the depth of the floating electrode may be the same as the gate electrode in the cell trench (220). At the upper semiconductor surface of the floating region there may be a gate metal layer (214), which gate metal layer (214) is connected to a gate electrode (206) on a cell trench (220) in the active region. In one embodiment, a portion of the floating electrode (217) may be connected to the gate metal layer (214).
The floating trench (222) can mitigate contaminant ions from entering the active region and the termination region from the periphery of the chip. The floating electrode (217) advantageously limits the electric field distribution near the upper surface of the semiconductor at the floating trench region (232) to prevent leakage paths formed by contaminant ion intrusion.
The cut-off region (233) is located at the outermost periphery of the chip and at least comprises a cut-off groove (224) surrounding the inside of the chip, and the cut-off groove (224) has the same structure as the cell groove (220) or the terminal groove (221). Wherein all electrodes in the cut-off trench (224) are connected to the cut-off metal layer (213) on the upper surface of the semiconductor and connected to the upper surface of the semiconductor at the periphery of the cut-off trench (224) through the contact hole.
In one embodiment, the cell trench (220) and the termination trench (221) have a width of between 1um and 4um and a depth of between 5um and 14um. In one embodiment, the distance between adjacent cell trenches (220) is between 0.4um and 2 um.
Figure 6 illustrates a top view of a possible trench structure of the device of the present invention. Wherein the dashed line a corresponds to a partial cross-section in fig. 2.
As shown, the center of the device chip has a plurality of active areas (230). Within the active region (230) are a series of mutually parallel cell trenches (220). Typically, the series of cell trenches (220) within adjacent active areas (230) are oriented perpendicular to each other. At the periphery of each individual active region (230), there is a termination trench (221) which surrounds the active region (230) in one or more sections parallel to each other and forms a termination trench region (231).
Typically, each active region (230) forms a termination trench region (231) with a termination trench (221) at its periphery, the termination trench region (231) having an aspect ratio of 4:1 to 1: 4.
At the outermost periphery of the device chip, a cut-off trench (224) surrounding the quadrangular device is provided and a cut-off region (233) is formed. The shut-off trench (224) may form a rounded arc at the corners.
In the irregular region between the cut-off region (233) and the terminal trench (221), there are a plurality of separate and mutually parallel floating trenches (222) and a floating trench region (232) is formed. Typically, the floating trench (222) has multiple directions. As shown in fig. 6, the floating grooves (222) have vertical and horizontal directions and are parallel to the adjacent termination grooves (221).
In one embodiment, the distance between a cell trench (220) and an adjacent terminal trench (221) is equal to the distance between a cell trench (220) and an adjacent cell trench (220) within the active region (230).
In one embodiment, the distance between the outermost cell trench (220) within the active region (230) and the adjacent termination trench (221) is equal to the distance between the cell trench (220) within the active region (230) and the adjacent cell trench (220).
In one embodiment, the distance between adjacent floating trenches (222) within a floating trench region (232) is equal to the distance between adjacent cell trenches (220) within an active region (230).
In one embodiment, the distance between adjacent floating trenches (222) in the floating trench region (232) increases with distance from the central region of the chip.
In one embodiment, a floating electrode (217) is provided within a portion of the floating trench (222) and is connected to the cut-off metal layer (213) at a corner of the quadrilateral chip, as shown in fig. 6.
Example 2
Fig. 3 is a schematic diagram of a field effect transistor device structure according to another embodiment of the present invention. The structure differs from the structure of fig. 2 in that the floating trench region (232) includes a plurality of separate and differently oriented floating trenches (222) therein, including a first type of parallel floating trenches (252) parallel to the termination trenches (221) and a second type of vertical floating trenches (262) perpendicular to the adjacent termination trenches (221). The first type vertical floating trenches (252) and the second type parallel floating trenches (262) may have multiple segments and the segments may be parallel to each other. The plurality of segments of parallel floating trenches (252) of the first type and vertical floating trenches (262) of the second type within the floating trench region (232) may exhibit an alternating arrangement.
In one embodiment, the second type of parallel floating trenches (262) contains floating electrodes (217), the floating electrodes (217) being connected to a stop metal layer (213) on the upper surface of the semiconductor. A portion of the floating trench (222) extends in a direction from the outside of the chip to the inside of the chip, or a direction from the off-region (233) to the active region (230), as shown in fig. 3. The floating electrode (217) may extend inward a length shorter than the length of the floating trench (222). In one embodiment, a length of the floating trench (222) is 3-15 a um a floating electrode (217) of which is connected to the peripheral cut-off metal layer (213) and extends inward of the chip a distance of 2-12 a um a.
Example 3
Fig. 4 is a schematic diagram of a field effect transistor device structure according to another embodiment of the present invention. The structure differs from the device structure of fig. 2 and 3 in that the floating trench (222) in the floating trench region (232) has the same width and depth as the termination trench (221) in the termination trench region (231), and in that the floating trench (222) has a floating electrode (217) therein, the floating electrode (217) extending to the trench bottom.
Example 4
Fig. 5 illustrates a field effect transistor device structure according to another embodiment of the present invention. The structure differs from the device structure described above in that there is a P-type floating implant region (255) between the floating trench (222) and below the floating trench within the floating trench region (232).
In one embodiment, the P-type floating implant region (255) has a lower doping concentration than the P-doped body region (208).
In one embodiment, the P-type floating implant region (255) surrounds a termination trench (221) located at the outermost periphery of the termination region (231).
Example 5
Fig. 7 shows a top view of another possible trench structure of the device of the present invention. Wherein the dashed line B corresponds to a partial cross-section of the floating trench region 232 in fig. 3. Unlike the structure shown in fig. 6, the floating trenches (222) within the same-side floating trench region (232) have independent vertical and horizontal segments.
In one embodiment, a floating electrode (217) is provided in a portion of the floating trench (222), and the floating electrode (217) is connected to the cut-off metal layer (213) of the quadrangular chip, as shown in fig. 7.
Example 6
Fig. 8 shows a top view of another possible trench structure of the device of the present invention. The difference from the foregoing structure is that the floating trench (222) in the floating trench region (232) has a different direction from the cell trench (220) in the active region (230).
In one embodiment, the direction of the floating trenches (222) within the partially floating trench region (232) has a 45 degree angle with respect to the direction of the cell trenches (220) within the active region (230).
In the embodiments of fig. 6-8 described above, the structure of the chip edge is advantageous in limiting contaminant ions from entering the chip interior, and in balancing the surface stresses on the four sides of the chip, reducing the risk of passivation layer breakage.
Example 7
Fig. 9 shows a top view of another possible cell trench (220) and termination trench (221) structure of the device of the present invention. Wherein, in the active region (230), an extension trench (253) having the same direction as the cell trench (220) is provided at the end of part of the cell trench (220), and the extension trench (253) is connected to the terminal trench (221). Typically, the depth and width of the extension trench (253) are no greater than the depth and width of the cell trench (220). In some embodiments, the extension trench may be a floating trench (222). The extension trench 253 ensures the breakdown voltage of the semiconductor region near the end of the cell trench 220.
Example 8
Fig. 10A shows a top view of another possible cell trench (220) and termination trench (221) structure of the device of the present invention. Wherein, in the active region (230), the end of the cell groove (220) is provided with an inner ring terminal groove (257) connected with the cell groove (220), and an outer ring terminal groove (259). The inner ring termination groove (257) and the outer ring termination groove (259) are both termination grooves (221). Wherein, two cell grooves (220) separated by more than one cell groove (220) are connected through an inner ring terminal groove (257) at the end of the cell groove, that is, at least one cell groove (220) is enclosed between the two cell grooves (220) connected through the inner ring terminal groove (257), and only one cell groove (220) is enclosed in fig. 10A; the ends of the two cell grooves (220) at two sides of the periphery of each inner ring terminal groove (257) are connected through the peripheral terminal grooves (259), that is to say, the inner ring terminal grooves (257) and the corresponding cell grooves (220) are enclosed between the two cell grooves (220) connected through the peripheral terminal grooves (259).
Figure 10B illustrates a top view of one possible trench and gate metal layer structure of the device of the present invention.
The structure includes a minimum of four active regions (230), and the series of cell trenches (220) within adjacent active regions (230) are oriented perpendicular to each other. A termination trench region (231) comprising termination trenches (221) is provided at the junction of adjacent active regions (230). Above the edges of the termination trench region (231) and the active region (230), there is a cross-shaped or cross-windmill shaped gate metal layer (214) structure. The gate metal layer (214) may be connected to the gate electrode (206) inside a portion of the cell trench (220) through a contact hole.
Example 9
Fig. 11-16 illustrate key steps of the manufacturing flow of one embodiment of the device of the present invention.
In a first step, an N-type epitaxial layer (200) is formed on an N-type semiconductor substrate (201).
Under the N-type semiconductor substrate 201, there may be a polysilicon layer 280, and an oxide layer 281 under the polysilicon layer 280. The thickness of the polysilicon layer (280) is between 0.4um and 1um, and the thickness of the oxide layer (281) is between 0.2um and 0.8 um. To mitigate wafer warpage caused by subsequent processes, a thick oxide layer 282 may be formed under the oxide layer 281. In one embodiment, a polysilicon layer is first formed under the wafer bottom oxide layer (281) and thermally oxidized to form a thick oxide layer (282) having a thickness between 0.2-1 um. The polysilicon layer 280, the oxide layer 281 and the thick oxide layer 282 are removed in the subsequent process.
In a second step, a nitride hard mask layer (254) and an oxide hard mask layer (256) thereon are formed on the upper surface of the semiconductor by deposition and photolithography. Next, semiconductor trenches (220, 221, 222) are etched, as shown in fig. 11.
A thin oxide layer may first be formed to a thickness between 50A and 2000A prior to depositing the nitride hard mask layer 254.
In one embodiment, it is possible to first etch the cell trench (220) and termination trench (221) and then etch the floating trench (222).
Typically, the cell trench (220) is between 0.5um and 4um wide and 5um to 14um deep. The width and depth of the termination trench (221) are not smaller than those of the cell trench. The width and depth of the floating trench (222) are no greater than the cell trench.
In one embodiment, the cell trenches (220) are the same as the trench width and depth of the termination trench (221).
In one embodiment, the cell trenches (220) and termination trenches (221) have the same trench width and depth, and the floating trenches (222) have the same depth as the termination trenches (221).
Third, a shield gate isolation layer (215) is formed in the cell trench (220) and the terminal trench (221), as shown in fig. 12.
The shield gate spacer may be comprised of an oxide, typically between 3000A and 2um thick. In one embodiment, a 1500A-6000A oxide layer is formed by thermal oxidation first, followed by deposition to form a 1000A-1.5um oxide layer.
In one embodiment, the shield gate isolation layer (215) material may completely fill the floating trench (222). In another embodiment, the shield gate spacer (215) material within the floating trench (222) may be removed, either completely or partially, by photolithography and etching steps, and further low stress insulating material, such as silicon-rich silicon oxide or the like, may be deposited therein.
Fourth, a shield gate electrode material (258) is deposited and then chemical mechanical polishing is performed to remove the shield gate electrode material (258) and the shield gate spacer material (215) from the upper surface of the semiconductor, the polishing stopping on the nitride hard mask layer (254) on the upper surface of the semiconductor.
The shield gate electrode material (258) is typically polysilicon. The upper surface of the polysilicon after deposition is higher than the upper surface of the semiconductor. The shield gate electrode material 258 may be etched back after chemical mechanical polishing.
In one embodiment, the nitride hard mask (254) layer in the second step may be omitted and the shield gate electrode material (258) etched back in a subsequent fourth step and using a dry or wet etch process.
Fifth, photolithography is performed, and then the barrier gate spacer (215) in the cell trench (220) is etched under the protection of the photoresist (260), as shown in fig. 14.
The etching method may be dry etching, and in some embodiments, dry etching may be performed first followed by wet etching. After etching is completed, the width of the upper surface opening is 0.1um to 1um, and the etching depth is 0.2um to 1.5um. After etching, the thickness of the shielding gate isolation layer (215) remained on the side wall of the etching hole in the cell groove (220) is not lower than 2000A.
After the etching is completed and the photoresist is removed, the nitride hard mask layer 254 on the upper surface of the semiconductor may be further removed.
In one embodiment, the photoresist only protects the shield gate isolation layer (215) material over the termination trench (221) and the floating trench, the shield gate isolation layer (215) over the cell trench (220) is removed and an inter-electrode isolation layer is formed by thermal oxidation in a subsequent process.
Sixth, a gate oxide layer and a gate electrode (206) are formed as shown in fig. 15.
The gate electrode (206) material is typically polysilicon and the formation process may be polysilicon deposition followed by etching back. In one embodiment, the polysilicon deposition may be followed by chemical mechanical polishing and then polysilicon etchback.
In one embodiment, the gate electrode (206) material within the floating trench (222) after the etch back is a floating electrode (217).
Seventh, a channel doped region is formed, then a surface oxide layer 261 is formed, then a contact hole 272 in the surface oxide layer, and an upper surface metal layer 211, 212, 213 are formed, and finally the device is formed, as shown in fig. 16. Wherein the channel doped regions include at least P-doped body regions (208) located between the cell trenches.
It will be appreciated by those skilled in the art that the above manufacturing steps list only key steps and do not demonstrate complete steps for forming the device.
The specific details of the manufacturing process may be suitably varied and increased according to the common general knowledge and process steps of the manufacturing process known in the art.
Furthermore, those skilled in the art will appreciate that the structural features and process steps recited in the various embodiments of the invention described above may be combined with one another to form further embodiment device structures and manufacturing flows.
Claims (17)
1. The power semiconductor device comprises a drain metal layer positioned at the bottom, a first conductive type heavily doped substrate layer positioned on the drain metal layer, a first conductive type first epitaxial layer positioned on the first conductive type heavily doped substrate layer, a second epitaxial layer, a groove region, and a source metal layer and a gate metal layer positioned on the upper surface of the device; the semiconductor device is characterized by being provided with more than one active area, more than one terminal area surrounding the active area, more than one floating groove area surrounding all the active areas and the terminal areas and positioned at the periphery of the chip, and a cut-off area surrounding the outermost periphery of the chip;
the active region comprises a series of cell grooves which are parallel to each other, the cell grooves comprise a gate electrode positioned above the grooves and a shielding gate electrode positioned below the grooves, a first conductive type lightly doped drift region and a second conductive type doped body region positioned above the first conductive type lightly doped drift region are arranged between the cell grooves, and the active region comprises at least two active regions formed by the cell grooves in different directions in one device;
the terminal area comprises more than one section of terminal grooves which are parallel to each other, a shielding gate electrode is filled in the terminal grooves, and the shielding gate electrode is connected to source metal on the upper surface of the device or other electric potentials between the source electrode and the drain electrode;
the floating groove area comprises more than one section of floating grooves which are parallel to each other;
the cut-off region comprises at least one cut-off groove and a cut-off metal layer positioned on the upper surface of the device in the region, wherein the cut-off groove is at least provided with a shielding gate electrode, and the shielding gate electrode is connected to the cut-off metal layer on the upper surface of the semiconductor.
2. The power semiconductor device of claim 1, wherein the floating trenches are filled with a low stress insulating material, and at least one of the floating trenches is provided with a floating electrode, the floating electrode being connected to a floating potential.
3. The power semiconductor device of claim 1 wherein said floating trenches comprise a first type of parallel floating trenches parallel to the termination trenches and a second type of vertical floating trenches perpendicular to the adjacent termination trenches.
4. The power semiconductor device of claim 2, wherein said floating electrodes are disposed in said second type of parallel floating trenches and/or said floating electrodes extend in a direction toward the inside of the chip.
5. The power semiconductor device of claim 1 wherein said floating electrode has a width and depth equal to the termination trench width and depth.
6. The power semiconductor device of claim 1, wherein a second conductivity type floating implant region is provided under said floating trench.
7. The power semiconductor device of claim 6 wherein said floating trench region is peripherally surrounded by a floating implant region of a second conductivity type.
8. The power semiconductor device of claim 1, wherein the distance between the floating trenches in the floating trench region increases gradually in a direction away from the central region of the chip.
9. The power semiconductor device of claim 1, wherein the floating electrode is connected to the cut-off metal layer at a corner of the quadrangular chip.
10. The power semiconductor device of claim 1, wherein the floating trench and the cell trench are oriented differently.
11. The power semiconductor device of claim 10 wherein the angle between the floating trench and one of the cell trenches is 45 ℃.
12. The power semiconductor device of claim 1, wherein an extension trench in the same direction as the cell trench is provided at a terminal end of at least one cell trench in the active region, the extension trench having a depth and a width not greater than the depth and the width of the cell trench, the extension trench being connected to the termination trench.
13. The power semiconductor device of claim 1, wherein more than one inner ring termination trench connecting any two cell trenches separated by more than one cell trench and more than one peripheral termination trench connecting cell trenches on both sides of each inner ring termination trench and surrounding the inner ring termination trench are provided in the active region, and the inner ring termination trench and the outer ring termination trench have the same structure as the termination trenches.
14. The power semiconductor device of claim 1 wherein the cell trenches in adjacent active areas are oriented perpendicular to each other.
15. A method of manufacturing a power semiconductor device, comprising the steps of:
a first step of forming a first conductivity type epitaxial layer on a first conductivity type semiconductor substrate;
forming a nitride hard mask layer and an oxide hard mask layer above the nitride hard mask layer on the upper surface of the semiconductor through deposition and photoetching, and then etching a semiconductor groove;
thirdly, forming a shielding gate isolation layer in the cell groove and the terminal groove;
fourthly, firstly depositing a shielding gate electrode material, and then performing chemical mechanical polishing to remove the shielding gate electrode material and the shielding gate isolation layer material on the upper surface of the semiconductor, wherein the polishing is stopped on the nitride hard mask layer on the upper surface of the semiconductor;
fifth, photoetching is carried out, and then the shielding gate isolation layer in the cell groove is etched under the protection of photoresist;
after etching, the thickness of the shielding gate isolation layer remained on the side wall of the etching hole in the cell groove is not lower than 2000A;
forming a gate oxide layer and a gate electrode;
seventh, forming a channel doping region, forming a surface oxide layer, and then forming a contact hole in the surface oxide layer, a source metal layer, a gate metal layer and a cut-off metal layer; the channel doped region includes at least a second conductivity type doped body region located between the cell trenches.
16. The method of manufacturing a power semiconductor device according to claim 15, wherein in the first step, a polysilicon layer is formed under the first conductivity type semiconductor substrate, an oxide layer is formed under the polysilicon layer, the polysilicon layer is first formed under the oxide layer and is thermally oxidized to form a thick oxide layer, and the polysilicon layer, the oxide layer, and the thick oxide layer are removed in a subsequent process.
17. A method of manufacturing a power semiconductor device according to claim 15, wherein in the fifth step, the photoresist only protects the material of the barrier layer on the termination trench and the floating trench, the barrier layer on the upper portion of the cell trench is removed, and the inter-electrode barrier layer is formed by thermal oxidation in a subsequent process.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311175979.1A CN117080245A (en) | 2023-09-13 | 2023-09-13 | Power semiconductor device and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311175979.1A CN117080245A (en) | 2023-09-13 | 2023-09-13 | Power semiconductor device and preparation method thereof |
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