CN220672589U - Semiconductor field effect transistor device - Google Patents
Semiconductor field effect transistor device Download PDFInfo
- Publication number
- CN220672589U CN220672589U CN202322204070.6U CN202322204070U CN220672589U CN 220672589 U CN220672589 U CN 220672589U CN 202322204070 U CN202322204070 U CN 202322204070U CN 220672589 U CN220672589 U CN 220672589U
- Authority
- CN
- China
- Prior art keywords
- region
- trench
- type
- gate
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 230000005669 field effect Effects 0.000 title claims abstract description 36
- 230000005684 electric field Effects 0.000 claims abstract description 21
- 230000002093 peripheral effect Effects 0.000 claims abstract description 9
- 230000015556 catabolic process Effects 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 77
- 229920005591 polysilicon Polymers 0.000 claims description 77
- 229910052751 metal Inorganic materials 0.000 claims description 47
- 239000002184 metal Substances 0.000 claims description 47
- 238000002955 isolation Methods 0.000 claims description 40
- 238000005468 ion implantation Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 238000002161 passivation Methods 0.000 claims description 7
- 210000000746 body region Anatomy 0.000 claims description 5
- 239000003990 capacitor Substances 0.000 claims description 4
- 239000002131 composite material Substances 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 22
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- 230000003647 oxidation Effects 0.000 description 11
- 238000007254 oxidation reaction Methods 0.000 description 11
- 238000005530 etching Methods 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 10
- 238000000206 photolithography Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 238000000151 deposition Methods 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000003344 environmental pollutant Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 231100000719 pollutant Toxicity 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000011669 selenium Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 208000033999 Device damage Diseases 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- -1 na + Chemical class 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
Abstract
The utility model relates to a semiconductor field effect transistor device and a manufacturing method thereof, and relates to a power semiconductor device, wherein the semiconductor device further comprises an active area for providing a current conducting area when the device is turned on, a terminal groove area for enabling an electric field between a source electrode and a drain electrode to be positioned in the active area to prevent breakdown of a peripheral area of the device, a gate-source capacitance area for providing additional Cgs for the device and improving switching performance, a stress release area and an electric field cut-off area for reducing stress generated by grooves arranged periodically, the ratio of gate-source capacitance to gate-drain capacitance can be improved compared with the traditional structure and process, and the device terminal structure with high reliability is provided.
Description
Technical Field
The utility model relates to a structure of a power semiconductor device, in particular to a shielded gate trench type field effect transistor device and a manufacturing method thereof.
Background
The related art background of the conventional shielded gate trench type field effect transistor will be described below. It is noted that corresponding positional words such as "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "vertical" as described in this document are relative positions corresponding to the reference drawings. The fixing direction is not limited in the specific implementation. It should be noted that the devices in the drawings are not necessarily drawn to scale. The straight lines shown in the boundaries of the doped regions and trenches in the drawings, and the sharp corners formed by the boundaries, are generally not straight lines and precise angles in practical applications.
The shielded gate trench type field effect transistor is used as a novel power device and has the characteristics of low on-resistance and high switching speed. The structure of the shielded gate trench field effect transistor is characterized in that a gate electrode and a shielded gate electrode which are isolated from each other are arranged in a trench, wherein the shielded gate electrode is positioned below the gate electrode and needs to be connected to upper surface metal.
In the switching process of the field effect transistor device, especially in the occasion that a plurality of field effect transistors are used in parallel, the ratio of the gate-source capacitance (Cgs) to the gate-drain capacitance (Cgd) is improved, and the device damage caused by the incorrect switching-on of the device is prevented. In conventional designs, the ratio of the gate-source capacitance (Cgs) to the gate-drain capacitance (Cgd) is typically determined by the structure of the device.
High reliability applications such as automobiles, rail transit, etc. need to ensure that the parameters of the fet devices remain stable for long periods of use, ensuring circuit safety. However, in the practical application process, water vapor or foreign pollutant ions may invade into the field effect transistor device chip, affecting parameters such as threshold voltage, leakage, breakdown voltage, etc. Therefore, it is desirable to provide a highly reliable device termination area that prevents foreign contamination or mobile ions from entering the chip active area.
In the shielded gate trench field effect transistor, the deep trench structure may cause severe stress on the surface of the chip, and the surface oxide layer and the passivation layer of the terminal area under thermal expansion and cold contraction are easy to crack or delaminate, so that water vapor or foreign pollutant ions are more easy to invade the semiconductor, and the device is invalid.
In addition, some high reliability has certain requirements on electrostatic protection performance of the gate electrode of the device, and a clamp protection circuit, such as a parallel zener diode structure, needs to be arranged between the gate and the source of the field effect transistor. In the field effect transistor integrated with the electrostatic protection circuit, the total process flow generally needs eight to ten photolithography steps, the process cost is high, and the manufacturing process for reducing the photolithography steps is necessary to save the cost.
Disclosure of Invention
In view of the above-mentioned problems of the prior art shielded gate trench fet devices, there is a need to provide a highly reliable shielded gate trench fet structure and process flow with a simple process.
The semiconductor field effect transistor device comprises a drain electrode metal layer positioned at the bottom of the device, a first conductive type heavily doped substrate layer positioned above the drain electrode metal layer and a first conductive type epitaxial layer positioned above the first conductive type heavily doped substrate layer; a second conductive type doped body region and a first conductive type heavily doped source region positioned on the upper surface of the device; an oxide layer, a source metal layer and a gate metal layer on top of the device; a passivation layer located at the edge of the device and above the source metal layer and the gate metal layer; the upper surface of the device is downwards extended with a first type groove and a second type groove, the first type groove comprises a first shielding gate electrode and a gate electrode, and the second type groove comprises a second shielding gate electrode and a surface polysilicon layer formed by upwards extending the second shielding gate electrode; the device at least comprises an active area for providing a current conducting area when the device is turned on, a terminal groove area for enabling an electric field between a source electrode and a drain electrode to be located in the active area when the device is reversely biased so as to prevent breakdown of a peripheral area of the device, a gate-source capacitance area for providing additional Cgs for the device and improving switchability, a stress releasing area for reducing stress generated by grooves arranged periodically of the device and an electric field cut-off area.
Wherein the active region is formed by a series of first type trenches; the terminal groove region is formed by more than one section of second type grooves which are parallel to each other, and a second shielding gate electrode in the second type grooves in the region is connected with the source electrode metal layer; the gate-source capacitance region comprises more than one section of second type grooves which are parallel to each other, a second shielding gate electrode in the region is connected with the source metal layer, and gate metal in the region and a surface polysilicon layer in the region form a gate-source capacitance in the vertical direction; the stress relief region comprises at least one first type of trench surrounding the gate-source capacitance region; the electric field cut-off region at least comprises a first type groove surrounding the stress release region, a second type groove surrounding the first type groove of the region, and a contact hole surrounding the second type groove of the region and used for connecting a semiconductor region at the periphery of the device and a second shielding gate electrode in the second type groove of the region.
Preferably, a first isolation layer, a second isolation layer and a third isolation layer are sequentially arranged between the shielding gate electrode and the side wall of the groove, wherein the composition material of the second isolation layer is different from that of the first isolation layer and the third isolation layer.
Further, the thickness of the third trench-like dielectric layer below the trench is wider than the thickness above the trench.
Preferably, the electric field cut-off region further includes an electric field cut-off metal layer located above, connected to the gate electrode in the first type trench in the electric field cut-off region through the contact hole, and connected to the peripheral contact hole.
Preferably, the second conductivity type ion implantation region is arranged right below the second type trench in the terminal trench region.
Preferably, a gate polysilicon layer is disposed in the oxide layer in the gate-source capacitance region, and the gate polysilicon layer and the surface polysilicon layer in the region form a gate-source capacitance in a vertical direction.
Preferably, a plurality of sections of ineffective grooves are arranged on the periphery of the first type groove in the stress relief area.
Furthermore, the ineffective groove is a first groove, the gate electrode and the first shielding gate electrode in the groove are not connected to the external electrode and are at floating potential, or the ineffective groove is an insulator filling groove.
Preferably, the device further comprises an electrostatic protection region adjacent to the termination trench region and a gate trench region adjacent to the electrostatic protection region; the electrostatic protection area comprises a surface polysilicon layer positioned above the semiconductor, and the polysilicon layer is respectively connected to the second shielding gate electrode in the terminal trench area and the gate trench area; the polysilicon layer is internally provided with a zener diode structure arranged in the horizontal direction.
Preferably, the electrostatic protection area is further provided with a second type of groove, which is used for limiting the position of the electrostatic protection area.
Preferably, the gate metal and polysilicon layer located over the device form a vertically oriented capacitor structure.
Preferably, the device comprises more than two active regions, the trench direction in each active region is parallel or vertical, and the active regions are connected to the gate trench region through the electrostatic protection region.
The utility model has the beneficial effects that: compared with the traditional structure and process, the novel shielding gate trench type field effect transistor device structure and the manufacturing process flow can improve the gate-source capacitance-gate-drain capacitance ratio and provide a device terminal structure with high reliability.
Furthermore, a device structure integrated with electrostatic protection is proposed on the basis of the above structure.
In addition, the manufacturing method of the structure is provided, at least two photoetching steps can be saved, and the manufacturing cost is effectively reduced.
Drawings
FIG. 1 is a schematic cross-sectional view of a shielded gate trench FET of the present utility model;
FIG. 2 is a schematic view of the location of a P-type implanted ion region;
FIG. 3 is a schematic diagram of a gate polysilicon layer position;
FIG. 4 is a schematic cross-sectional view of the electrostatic protection region of a shielded gate trench FET of the present utility model;
FIG. 5 is a top view of one possible device layout for a shielded gate trench field effect transistor of the present utility model;
FIGS. 6-13 are schematic cross-sectional views of one possible key fabrication step of a shielded gate trench field effect transistor of the present utility model;
fig. 14 is a schematic cross-sectional view of a key manufacturing step of the electrostatic protection region of the shielded gate trench fet of the present utility model.
Detailed Description
The present utility model will be described in detail below with reference to the drawings and examples. In the following description of the shielded gate trench type field effect transistor device and the method of manufacturing the same of the present utility model, the semiconductor substrate of the shielded gate trench type field effect transistor device is considered to be composed of a silicon (Si) material。However, the substrate may be formed of any other material suitable for manufacturing a shielded gate trench field effect transistor, such as gallium nitride (GaN), silicon carbide (SiC), and the like. In the following description, the conductivity type of the semiconductor region is classified into P-type (second conductivity type) and N-type (first conductivity type), and one P-type conductivity type semiconductor region may be formed by doping one or several impurities into the original semiconductor region, which may be, but are not limited to: boron (B), aluminum (Al), gallium (Ga), and the like. An N-type conductive semiconductor region may also be formed by doping the original semiconductor region with one or more impurities, such as, but not limited to: phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), protons (h+), and the like. In the following description, a heavily doped P-type conductive semiconductor region is denoted as a p+ region, and a heavily doped N-type conductive semiconductor region is denoted as an n+ region. For example, in a silicon material substrate, the impurity concentration of a heavily doped region is typically 1X 10 19 cm -3 Up to 1X 10 21 cm -3 Between them. Those skilled in the art will appreciate that the P-type (second conductivity type) and N-type (first conductivity type) of the present utility model may be interchanged.
Fig. 1 is a semiconductor field effect transistor device of a first embodiment, which includes: a drain metal layer (213) located at the bottom; an n+ substrate layer (200) over the drain metal layer; an N-type epitaxial layer (201) over the n+ substrate layer; a P doped body region (220) and an N+ doped source region (221) located on the upper surface of the device; a source metal layer (240) and a gate metal layer (241) on top of the device; a passivation layer (242) on top of the source (240) and gate (241) metal layers at the edge of the device.
Furthermore, two types of grooves are included: a first type trench (202) and a second type trench (211).
The first type of trench (202) comprises at least: a gate electrode (209) located above the trench and a shield gate electrode (205) located below. The gate electrode (209) is isolated from the trench sidewall by a gate oxide layer. An inter-electrode isolation layer (206) is provided between the gate electrode (209) and the shield gate electrode (205). Wherein the shield gate electrode (205) is connected to a source metal (240) located on the upper surface of the device. In addition, a first isolation layer (225), a second isolation layer (226) and a third isolation layer (227) are arranged between the shielding gate electrode (205) and the side wall of the groove, wherein the composition materials of the second isolation layer (225) are different from those of the first isolation layer and the third isolation layer, and the second isolation layer is beneficial to reducing stress generated by the third isolation layer and the first isolation layer on adjacent semiconductors in a thermal process. The first spacer layer (225) is typically an oxide, typically between 100A-1000A thick; the second isolation layer (226) may be a nitride or other oxidation resistant insulating material having a thickness between 100A and 2000A; the third spacer (227) may be an oxide, typically having a thickness between 500A-5000A.
The second type trench (211) includes at least a shield gate electrode (205). Wherein the shield gate electrode (205) extends to the upper surface of the semiconductor and forms a surface polysilicon layer (247). And a first isolation layer (225), a second isolation layer (226) and a third isolation layer (227) are arranged between the shielding gate electrode (205) and the side wall of the groove.
This embodiment includes at least the following regions: an active region (251), a termination trench region (252), a gate-source capacitance region (253), a stress relief region (254), and an electric field cutoff region (255).
The active region (251) is constituted by a series of trenches (202) of a first type arranged horizontally.
The active region (251) functions to provide a current conduction region when the device is on.
The termination trench region (252) comprises one or more sections of trenches (211) of a second type parallel to each other. The second type trench encloses the active region (251) and wherein the shield gate electrode (205) is connected to the source metal layer (240).
The termination trench region (252) functions to locate the electric field between the source and drain electrodes in the active region inside the device during reverse bias to prevent breakdown of the peripheral region of the device.
The gate-source capacitance region (253) includes one or more segments of a second type of trench (211) that are parallel to each other, and a gate metal (241) located thereabove. Wherein the shield gate electrode (205) is connected to the source metal layer (240), and a portion of the shield gate electrode (205) extending to the upper surface of the semiconductor and the gate metal (241) form a gate-source capacitance in a vertical direction. The second type of trenches (211) in the gate-source capacitance region (253) may have multiple segments and may be arranged parallel to each other, and the pitch between the trenches may be larger than the pitch of the trenches in the active region (251).
The gate-source capacitance region (253) functions to provide additional Cgs to the device and improve switching; in addition, the interior of the upper surface of the device is at the source potential and the edge of the device is near the drain potential upon reverse bias, positively charged foreign contaminant ions (e.g., na + ，K + ，H + ，Zn + Etc.) tend to move from the edge to the inside of the device under the influence of the electric field, accumulate in the termination area (or other process defect), create breakdown weak points and affect the device breakdown voltage. The gate-source capacitance in the vertical direction in the structure can relieve the movement and accumulation of external pollutant positive charges in the device in the charge-discharge process of the device switch, and prevent the influence of movable ions on the terminal trench region (252).
The stress relief region (254) has a length greater than 5um and comprises at least a first type trench (202) surrounding the gate-source capacitance region (253). The depth of the trench may be shallower than the trench of the termination trench region. In some embodiments, the fill material in the trench may be different from the fill material in the trenches in other regions. For example, the gate electrode (209) material in the first type of trench (202) in the (254) region is metal, while the other trenches are polysilicon. As another example, the gate electrode (209) material in the first type of trench (202) in the (254) region is undoped polysilicon, while the other trenches are doped polysilicon. The aim is to reduce the stress of the grooves in the relief area (254).
The stress relief region (254) acts to reduce stress created by the periodically arranged trenches of the device, to reduce micro-cracking and warping of the peripheral region of the device due to stress, and the trenches in that region also act to block contaminant ions from migrating into the interior of the device.
Further, there may be a plurality of sections of the first type groove (202) having different lengths and directions from each other around the first type groove (202).
The field stop region (255) includes at least a first type of trench (202) surrounding the stress relief region (254), a second type of trench (211) surrounding the first type of trench (202), and a peripheral contact hole trench (219) surrounding the second type of trench (211). The contact hole trench (219) is filled with a metal or metal compound to connect the semiconductor region at the periphery of the device and the shield gate electrode (205) in the second type trench (211).
Furthermore, the electric field cut-off region (255) may further comprise an upper electric field cut-off metal layer (243). The electric field cut-off metal layer (243) may be connected to the gate electrode (209) of the first type trench (202) within the electric field cut-off region (255) through a contact hole and connected to the peripheral contact hole trench (219).
The electric field cut-off region (255) is used for preventing the electric field between the source electrode and the drain electrode from expanding to the edge region of the device during reverse bias, and in addition, an equipotential region can be formed at the outermost periphery of the device, so that movable ions at the edge of the device are prevented from gathering at the edge of the device, and the movable ions on the defect of a cutting line at the edge of the device are prevented from invading into the device.
The above structure provides a high reliability shielded gate trench field effect transistor device structure that may vary from one embodiment to another.
In one embodiment, a P-type implanted ion region 261 is located directly below the second type trench 211 in the termination trench region 252, as shown in fig. 2. The P-type ion implantation region can improve the breakdown voltage of the terminal trench region and increase the UIS capability of the device.
In one embodiment, the gate-source capacitance region (253) is not provided with an overlying gate metal layer 241, but with an additional gate polysilicon layer (262) provided in the oxide layer (230) over the shielded gate electrode in the second type trench (211), as shown in fig. 3. And a gate-source capacitor in the vertical direction is formed between the gate polysilicon layer and the shielding gate electrode below the gate polysilicon layer. The structure can avoid the limit of minimum width between metals to save the area of the device, and the grid-source capacitance can be larger because the grid polysilicon can be arranged closer to the shielding grid electrode.
In one embodiment, the stress relief region (254) comprises one or more segments of a first type of trench (202) surrounding the gate-source capacitance region (253), and a plurality of segments of inactive trenches are provided around the periphery of the first type of trench (202). The inactive trenches have a lower density than the trenches in the active region. In one embodiment, the lower the ineffective trench density within the stress relief region (254) closer to the device periphery. The inactive trench is typically a first type of trench whose internal gate electrode and shield gate electrode are not connected to external electrodes and are floating. Furthermore, ineffective trenches may also fill the trenches with insulation. The inactive grooves may be multiple segments of short grooves, with the segments of short grooves having different directions. The ineffective grooves can also be a plurality of needle-shaped grooves which are distributed in a punctiform manner on the layout.
Fig. 4 shows another embodiment of the present utility model, and an electrostatic protection area (256) is additionally provided on the basis of the above embodiment. The electrostatic protection region (256) is adjacent to the termination trench region (252) and the gate trench region (257), respectively.
Wherein the gate trench region (257) comprises at least one section of a second type trench (211), and a shielding gate electrode (205) of the second type trench is connected to the gate metal layer (241) on the upper surface.
The electrostatic protection region (256) includes a surface polysilicon layer (247) over the semiconductor. The polysilicon layer (247) is connected to the shield gate electrode (205) in the second type of trench (211) within the termination trench region (252) and the gate trench region (256), respectively. The polysilicon layer has a zener diode structure (266) disposed in a horizontal direction. The zener diode structure may be comprised of an alternating set of P-type polysilicon and N-type polysilicon.
In addition, more second-type trenches may be included within the electrostatic protection region (256) to define the location of the electrostatic protection region (256). The gate metal (241) and polysilicon layer (247) located over the device may form a vertically oriented capacitance structure and increase the gate-source capacitance.
Fig. 5 is a schematic diagram of a trench top view of one possible chip layout embodiment of the present utility model, wherein a dashed line a corresponds to the cross-sectional structure of fig. 1 and a dashed line B corresponds to the cross-sectional structure of fig. 4.
As shown, the layout structure may include a plurality of active regions (251), and the trench orientation may be different in each active region. The active region (251) is connected to the gate trench region (257) through the electrostatic protection region (256). Between the active region (251) and the periphery of the chip are respectively: a termination trench region (252), a gate-source capacitance region (253), a stress relief region (254), and an electric field cut-off region (255). In the above structure, a surface polysilicon layer (247) is arranged above the second type groove (211), and the polysilicon layer is cut off on the adjacent first type groove (202). The first type of trench (202) surrounding the second type of trench (211) serves to define the location of the surface polysilicon layer and thereby define the gate-source capacitance region (253) and the electrostatic protection region (256).
The following describes the steps of the manufacturing process of the shielded gate trench type field effect transistor device described above, as shown in fig. 6 to 13.
In a first step, an N-type epitaxial layer (201) is formed on an n+ substrate layer (200), and a series of first-type trenches (202) and second-type trenches (211) are formed on the N-type epitaxial layer (201), as shown in fig. 5. Wherein the N+ substrate may be doped with red phosphorus or arsenic, and has a thickness of 50-800 um. The N-type epitaxial layer may be phosphorus doped and have a thickness of between 0.5 and 15 μm. In one embodiment, the doping concentration is in a dilute-down concentration distribution within the N-type epitaxial layer. Wherein the most doping concentration is 5e17 cm -3 To 1e16 cm -3 Between them, the maximum concentration is 5e17 cm -3 To 1e18 cm -3 Between them.
A hard mask, which may be a semiconductor oxide or nitride, or a combination of both, may be formed on the upper surface of the epitaxial layer by photolithography prior to trench formation. The hard mask may be removed after the trench etch or may remain partially or completely on the upper surface of the epitaxial layer after the trench etch.
The first type trench (202) and the second type trench (211) may be simultaneously formed by dry etching, and the etching depth is determined by the size of an etching window on the upper surface of the semiconductor during etching. In one embodiment, the trench may be formed by reactive ion etching. In a specific embodiment, the first type of trench has a top surface width of 0.2-0.5um and a depth of 1.2-3 um. In another specific embodiment, the first type of trench has an upper surface with a width of 0.5-1.5um and a depth of 3-6 um.
And secondly, forming a groove insulating layer, namely an isolation layer, in the groove. The trench insulating layer is composed of a first isolation layer (225), a second isolation layer (226), and a third isolation layer (227), as shown in fig. 7.
The first spacer layer (225) is typically an oxide and may be formed by thermal oxidation or deposition, or a combination of both, with the first type trench dielectric layer typically having a thickness of between 100A and 1000A.
The second isolation layer (226) may be a nitride or other oxidation resistant insulating material, such as silicon-rich silicon nitride, formed by deposition to a thickness of between 100A-2000A. In a specific embodiment, the method for forming the second type trench dielectric layer includes: 1000A nitride is deposited by chemical vapor deposition over the first trench-type dielectric layer.
The third spacer (227) may be an oxide and may be formed by deposition, typically having a thickness between 500A and 5000A.
In one embodiment, the thickness of the third isolation layer (227) is wider below the trench than above the trench. In one embodiment, the third spacer (227) is an oxide having boron or phosphorus doping.
Fourth, the trench is filled with polysilicon 245 and is above the upper surface of the semiconductor, as shown in fig. 8.
The thickness of the polysilicon (245) on the upper surface of the semiconductor after filling is between 2000A and 8000A. After filling the polysilicon 245, chemical mechanical polishing is typically performed to planarize the top surface of the polysilicon.
In one embodiment, the filled polysilicon (245) may be low doped polysilicon or undoped polysilicon. The electrostatic protection structure is formed by adjusting the doping concentration in the subsequent process.
Fifth, photoetching is carried out, polysilicon above the first type groove (202) is etched under the protection of the photoresist (246), and a shielding gate electrode (205) in the first type groove is formed. As shown in fig. 9.
The photoresist protects the polysilicon (245) over the second type trenches (211) during photolithography so that the polysilicon in that region remains on the upper surface of the semiconductor after etching.
The polysilicon is etched back by dry etching to a depth of between 0.3 um and 1um down the top surface of the semiconductor.
In one embodiment, after the formation of the photoresist protection region, or after the formation of the shield gate electrode (205), an additional vertical ion implantation is performed under the photoresist protection to increase the oxidation rate of the polysilicon in the exposed region in a subsequent thermal oxidation process.
In one embodiment, the polysilicon (245) is undoped polysilicon or low doped polysilicon, and after the shielding gate electrode (205) is formed, ion implantation is additionally performed in a vertical direction under the protection of photoresist, so that the doping concentration and the oxidation rate of the polysilicon of the shielding gate electrode (205) are improved, and the realization of oxide layers with different thicknesses in different areas in the subsequent thermal oxidation process is facilitated.
Sixth, a thick oxide layer (249) is formed on the upper surface of the shield gate electrode (205) by thermal oxidation. The upper surface and sides of the polysilicon layer (245) overlying the second type trenches are simultaneously partially oxidized to oxide (248) while forming a thick oxide layer. After the thermal oxidation, the polysilicon remaining on the upper surface of the semiconductor forms a surface polysilicon layer (247), as shown in fig. 10.
The thick oxide layer (206) formed by thermal oxidation has a thickness of 0.2 to 1um, and the polysilicon layer (247) remaining on the upper surface of the semiconductor after thermal oxidation has a thickness of 0.05 to 3 um. The polysilicon layer (247) serves as a capacitor structure and an electrostatic protection structure in the vertical direction of the final device. The width and length of which are defined by the distance between adjacent trenches (211) of the second type. In one embodiment, the length and width are between 1-1000 um.
Seventh, the thick oxide layer 249 is etched back to form an inter-electrode isolation layer 206, and the first, second and third isolation layers 225, 226 and 227 on the first type trench 202 are removed to expose the upper half of the trench, as shown in fig. 11.
The method of etching back the oxide layer (249) may be wet etching, and when etching back the thick oxide layer (249), the oxide layer (248) above the polysilicon layer (247) on the upper surface is partially etched, which plays a role of protecting the polysilicon layer (247). The first isolation layer (225) may be oxide and may be completely removed at the same time as the thick oxide layer (249) is etched back. The thickness of the inter-electrode isolation layer (206) formed after the back etching is between 0.1 and 0.5 um.
Wet etching may be used to remove the second isolation layer (226). It is possible to form a groove structure between the first isolation layer (225) and the third isolation layer (227) after etching. In one embodiment, the second isolation layer (226) may be removed followed by depositing an oxide to fill the recess and etching back the oxide while the third isolation layer (227) is removed.
Eighth step, a gate oxide layer (208), a gate electrode (209) are respectively formed, and then ion implantation is performed to form a P-type doped body region (220) and N + A type dopant source region 221 as shown in fig. 12.
The gate electrode (209) is typically polysilicon and may be formed by a process that includes two steps, polysilicon deposition and polysilicon etchback. The method of polysilicon etchback may be dry etching. The distance from the upper surface of the gate electrode 209 after the back etching to the upper surface of the semiconductor is 0-0.2 mu m.
During the ion implantation, the surface polysilicon (247) and the surface oxide layer (248) above the second type trenches (211) can be used as a hard mask to limit the ion implantation area to the position between the first type trenches (202). Thus, by arranging the first and second type trenches in fig. 5, for example, a photolithography step omitting one or two ion implantations can be realized.
Ninth, an oxide layer (230), a contact hole (219), an upper surface metal layer (240, 241, 243), a passivation layer (242), a back surface metal layer (213) are formed, respectively, and finally a device is formed, as shown in fig. 13.
The oxide layer (230) is typically composed of an oxide and has a thickness of 0.3-1.5 μm. In one embodiment, the oxide layer (230) comprises a layer of undoped silicon oxide having a thickness of 0.05-1.0 μm below and a layer of borophosphosilicate glass having a thickness of 0.1-1.5 μm above. The oxide layer (230) formation method may include oxide deposition and oxide planarization.
A part of the contact hole (219) is positioned right above the groove and goes deep into the shielding gate electrode (205) or the gate electrode (209); a portion of the contact hole (219) is located between the trenches and deeper into the semiconductor, and is in contact with the P-type doped region (220) and N + Doping source region221 A) contact.
The upper surface metal is typically Al or an Al compound composition, e.g., al/Cu, al/Si/Cu, with a thickness of 3-5 μm. The diffusion barrier metal material may be filled in the contact holes (219) first before the upper surface metal is formed.
The upper surface metal may also be a combination layer, such as an Al/Cu layer on top and a Ti/W layer on bottom, and the combination layers may be formed by different photolithography steps.
A passivation layer (242) is over the metal layer, and the constituent material may be an oxide layer, a nitride layer, a silicon-rich nitride layer, a polyimide, or a combination thereof. In one embodiment, the passivation layer is: a 3000A-10000A oxide layer, a 3000A-8000A nitride layer, and a polyimide layer of 3um-8 um.
Based on the above process flow, a process flow of a device structure introducing an electrostatic protection structure is as follows: in the eighth step, a zener diode structure (266) is formed on the polysilicon (247) on the upper surface of the semiconductor in the electrostatic protection region (256), as shown in fig. 14.
An electrostatic protection region (256) is located between the two segments of the second type of trench (211).
In one embodiment, the surface polysilicon (247) is P-type polysilicon. After the P-type doped body region (220) is formed in the seventh step, the oxide layer (248) over the polysilicon (247) is etched by photolithography to form a discontinuous opening. Then, N-type doped polysilicon 244 is formed on the polysilicon 247 at the same time as the n+ -type doped source region 221 is formed by ion implantation in the subsequent step. The P-type polysilicon and the N-type doped polysilicon 244 form a zener diode structure 266.
In another embodiment, the surface polysilicon (247) is P-type polysilicon. After the n+ type doped source region 221 is formed in the seventh step, the oxide layer 248 above the polysilicon 247 is etched under the protection of photoresist by photolithography to form a discontinuous opening, and then additional ion implantation is performed to form the N type doped polysilicon 244 above the polysilicon 247.
The relevant process steps in the above embodiments may be appropriately increased or decreased to achieve the same effect, and those skilled in the relevant art will recognize that the above-described embodiments of the present utility model are not limited to the examples, and the present utility model may be implemented within a wider range than the above-described embodiments.
Claims (13)
1. The semiconductor field effect transistor device comprises a drain electrode metal layer positioned at the bottom of the device, a first conductive type heavily doped substrate layer positioned above the drain electrode metal layer and a first conductive type epitaxial layer positioned above the first conductive type heavily doped substrate layer; a second conductive type doped body region and a first conductive type heavily doped source region positioned on the upper surface of the device; an oxide layer, a source metal layer and a gate metal layer on top of the device; a passivation layer located at the edge of the device and above the source metal layer and the gate metal layer; the upper surface of the device is downwards extended with a first type groove and a second type groove, the first type groove comprises a first shielding gate electrode and a gate electrode, and the second type groove comprises a second shielding gate electrode and a surface polysilicon layer formed by upwards extending the second shielding gate electrode;
the device is characterized by further comprising an active area for providing a current conducting area when the device is turned on, a terminal groove area for enabling an electric field between a source electrode and a drain electrode to be located in the active area when the device is reversely biased so as to prevent breakdown of a peripheral area of the device, a gate-source capacitance area for providing additional Cgs for the device and improving switchability, a stress releasing area for reducing stress generated by grooves arranged periodically and an electric field cut-off area.
2. The semiconductor field effect transistor device as recited in claim 1, wherein,
the active area is formed by a series of first type trenches; and/or
The terminal groove region is formed by more than one section of second type grooves which are parallel to each other, and a second shielding gate electrode in the second type grooves in the region is connected with the source electrode metal layer; and/or
The gate-source capacitance region comprises more than one section of second type grooves which are parallel to each other, a second shielding gate electrode in the region is connected with the source metal layer, and gate metal in the region and a surface polysilicon layer in the region form a gate-source capacitance in the vertical direction; and/or
The stress relief region comprises at least one first type of trench surrounding the gate-source capacitance region; and/or
The electric field cut-off region at least comprises a first type groove surrounding the stress release region, a second type groove surrounding the first type groove of the region, and a contact hole surrounding the second type groove of the region and used for connecting a semiconductor region at the periphery of the device and a second shielding gate electrode in the second type groove of the region.
3. The semiconductor field effect transistor device as claimed in claim 1, wherein a first isolation layer, a second isolation layer and a third isolation layer are provided in this order between the shield gate electrode and the trench sidewall, wherein a composition material of the second isolation layer is different from that of the first and third isolation layers.
4. The semiconductor field effect transistor device as recited in claim 3, wherein a thickness of the third trench-like dielectric layer is wider below the trench than above the trench.
5. The semiconductor field effect transistor device as recited in claim 1, wherein said field stop region further comprises an upper field stop metal layer connected to the gate electrode in the first type of trench in the field stop region by a contact hole and connected to the peripheral contact hole.
6. The semiconductor field effect transistor device of claim 1, wherein an ion implantation region of the second conductivity type is located directly below the second type trench in the termination trench region.
7. The semiconductor field effect transistor device as recited in claim 1, wherein a gate polysilicon layer is disposed in the oxide layer in the gate-source capacitance region, the gate polysilicon layer and the surface polysilicon layer of the region forming a vertically oriented gate-source capacitance.
8. The semiconductor field effect transistor device as recited in claim 1, wherein a plurality of segments of inactive trenches are provided around the periphery of the first type of trench in the stress relief region.
9. The semiconductor field effect transistor device of claim 8, wherein the inactive trench is a first type trench and the gate electrode and the first shield gate electrode in the trench are not connected to an external electrode and are floating potential, or wherein the inactive trench is an insulator filled trench.
10. The semiconductor field effect transistor device of claim 1, wherein said device further comprises an electrostatic protection region adjacent to said termination trench region and a gate trench region adjacent to said electrostatic protection region; the electrostatic protection area comprises a surface polysilicon layer positioned above the semiconductor, and the polysilicon layer is respectively connected to the second shielding gate electrode in the terminal trench area and the gate trench area; the polysilicon layer is internally provided with a zener diode structure arranged in the horizontal direction.
11. The semiconductor field effect transistor device as recited in claim 10, wherein a second type of trench is further provided in said electrostatic protection region for defining a location of the electrostatic protection region.
12. The semiconductor field effect transistor device of claim 10, wherein the gate metal and polysilicon layer above the device form a vertically oriented capacitor structure.
13. The semiconductor field effect transistor device of claim 10, wherein the device comprises more than two active regions, the trench direction in each active region being parallel or perpendicular, the active region being connected to the gate trench region by an electrostatic protection region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322204070.6U CN220672589U (en) | 2023-08-16 | 2023-08-16 | Semiconductor field effect transistor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322204070.6U CN220672589U (en) | 2023-08-16 | 2023-08-16 | Semiconductor field effect transistor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220672589U true CN220672589U (en) | 2024-03-26 |
Family
ID=90338080
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322204070.6U Active CN220672589U (en) | 2023-08-16 | 2023-08-16 | Semiconductor field effect transistor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220672589U (en) |
-
2023
- 2023-08-16 CN CN202322204070.6U patent/CN220672589U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9502554B2 (en) | High frequency switching MOSFETs with low output capacitance using a depletable P-shield | |
| CN203325907U (en) | Insulated gate semiconductor device structure | |
| TWI509809B (en) | High density trench-based power mosfets with self-aligned active contacts and method for making such devices | |
| CN108400161B (en) | Semiconductor power device prepared by self-aligned process and more reliable electrical contact | |
| US9214526B2 (en) | Semiconductor device | |
| US6765264B1 (en) | Method of fabricating power rectifier device to vary operating parameters and resulting device | |
| TWI518803B (en) | Device structure and methods of making high density mosfets for load switch and dc-dc applications | |
| US20140077290A1 (en) | Trench metal oxide semiconductor field effect transistor with embedded schottky rectifier using reduced masks process | |
| US20140159144A1 (en) | Trench gate mosfet and method of forming the same | |
| JP6532549B2 (en) | Semiconductor device | |
| US20200020798A1 (en) | Power mosfet with an integrated pseudo-schottky diode in source contact trench | |
| US8159021B2 (en) | Trench MOSFET with double epitaxial structure | |
| KR20160150349A (en) | Power semiconductor device | |
| CN110071169A (en) | With body contact and the semiconductor devices of dielectric spacer portion and corresponding manufacturing method | |
| CN116093162A (en) | Shielded gate trench field effect transistor and manufacturing method thereof | |
| CN219419037U (en) | Groove type silicon carbide MOSFET device | |
| KR20210009005A (en) | Semiconductor device and method manufacturing the same | |
| CN220672589U (en) | Semiconductor field effect transistor device | |
| CN116314302A (en) | Manufacturing method of groove type silicon carbide MOSFET device | |
| CN111312824B (en) | Groove type power semiconductor device and preparation method thereof | |
| CN106601811B (en) | Trench type power transistor | |
| CN114823343A (en) | Shielding gate MOSFET device and manufacturing method thereof | |
| CN116825849A (en) | Semiconductor field effect transistor device and manufacturing method thereof | |
| US20120299109A1 (en) | Trench power mosfet structure with high switching speed and fabrication method thereof | |
| KR20200008170A (en) | Power semiconductor device and a method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |