CN101621081B - Structure of overlapping capacitors in semiconductor manufacture process - Google Patents
Structure of overlapping capacitors in semiconductor manufacture process Download PDFInfo
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- CN101621081B CN101621081B CN2009101844177A CN200910184417A CN101621081B CN 101621081 B CN101621081 B CN 101621081B CN 2009101844177 A CN2009101844177 A CN 2009101844177A CN 200910184417 A CN200910184417 A CN 200910184417A CN 101621081 B CN101621081 B CN 101621081B
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Abstract
The invention relates to a structure of an overlapping capacitor in a semiconductor manufacture process, which is an overlapping capacitor manufacture technology compatible with a bipolar complementary metal oxide semiconductor (BiCMOS) process and a complementary metal oxide semiconductor (CMOS) process. A capacitor the unit-area capacitance Cox of which reaches a high capacitance value of 4.1ff/um<2> is provided in the CMOS process, and BV is higher than 12V, and additional processes are not needed. Under the circumstance of not adding any processing step, the unit-area capacitance value Cox of an overlapped capacitor is increased to 4.1 ff/um<2> from 2.5 ff/um<2> of typical polyl1/Nw or poly1/diff in the manner of overlapping a layer of ONO capacitor on a poly1/Nw or poly1/diff capacitor, i.e. the unit-area capacitance value is increased by 64 percent, thereby greatly increasing the integration level of the capacitor; moreover, the overlapping capacitor manufacture technology is compatible with the prior arts; therefore, adding additional processes is not needed. On the premise of not increasing manufacture cost, using the capacitor with the structure can reduce the capacitor area in a circuit by about 38 percent.
Description
Technical field
The present invention is a kind of and the manufacturing technology of the overlap capacitance of BiCMOS (bipolar complementary metal oxide semiconductor), CMOS (complementary metal oxide semiconductors (CMOS)) process compatible, belongs to technical field of manufacturing semiconductors.
Background technology
In the BiCMOS and CMOS technology of main flow, ONO (oxide-nitride thing-oxide) electric capacity and Poly/well (polysilicon/trap), Poly/diff (polysilicon/diffusion region) electric capacity have been normal component at present.For the 0.6um that extensively adopts in the present domestic Analog Circuit Design (long measure: micron) BiCMOS technology and 0.5um CMOS technology, in order to guarantee the requirement of dielectric withstanding voltage, medium tunnelling current, anti-SILC (stress induces leakage current) characteristic and medium life-span aspect, ono dielectric thickness must have certain thickness, unit-area capacitance Cox (capacitance of the unit are)=1.6ff/um2 of typical ONO electric capacity, BV (puncture voltage)＞15V; Typical Poly/well, Poly/diff capacitor C ox=2.5ff/um2, BV＞12V.
Summary of the invention
Technical problem: the structure that the purpose of this invention is to provide overlap capacitance in a kind of BiCMOS and the CMOS technology, the electric capacity of the high appearance value that a kind of unit-area capacitance reaches Cox=4.1ff/um2 is provided in 0.6um BiCMOS technology and 0.5um CMOS technology, BV＞12V, and do not need extra technology.
Technical scheme: the structure of overlap capacitance is in the semiconductor fabrication process of the present invention: the capacitor regions at P substrate slice upper surface is a N trap, and diffusion 2 ~ 4um is dark downwards from silicon chip surface for the N trap, constitutes the bottom crown of electric capacity; The silicon face of capacitor regions just bottom crown N trap surface be a big active area, a little active area: little active area has N+ to inject the diffusion region---to form ohmic contact down by contact hole and metal line, as the exit of bottom crown; Big active area is as the effective coverage of poly1/well electric capacity in the overlap capacitance; Be exactly the place outside the active area, above the place be
Thick oxide is as the isolation between the active area; The silicon face of active area is one deck
Thick oxide, the oxide of big surfaces of active regions has just constituted the dielectric layer of poly1/well electric capacity in capacitor regions; On the thin oxide in the surface, effective coverage of poly1/well electric capacity is one deck
Polysilicon, the area of polysilicon is more slightly bigger than the effective coverage area of poly1/well electric capacity, has extended on the other place of big active area, this layer polysilicon just constituted the middle plate of electric capacity; Do not have polysilicon above the little active area, there is the polysilicon that extends up at the edge except the effective coverage active area that is close to poly1/well electric capacity on the place, and all the other zones do not have polysilicon yet; Upper surface at polysilicon is one deck
Ono dielectric, this layer medium constituted the dielectric layer of poly2/poly1 ONO electric capacity in the overlap capacitance; Be second layer polysilicon on ono dielectric, constituted the top crown of electric capacity, the area of this layer polysilicon is smaller than the area of the effective coverage active area of poly1/well electric capacity, and other zones do not have second layer polysilicon; On second layer polysilicon be cover whole wafer surface 6000～
Oxide, be referred to as multilevel oxide, the oxide directly over the polysilicon is the thinnest, the oxide directly over the bottom crown exit N+ diffusion region is the thickest; Multilevel oxide can be constituted the contact hole of through N+ or polysilicon surface by the place to go in the place of drawing of bottom crown exit N+ diffusion region, poly1, the relevant position of drawing the place of poly2; Be exactly ground floor metal line (13) directly over multilevel oxide, in the position of contact hole, metal line contacts with N+ or polysilicon surface, and the two ends of electric capacity are drawn respectively, forms a complete overlap capacitance structure.
Described bottom crown N trap according to the requirement different to capacitance characteristic, adds a highly doped N sinker diffusion region in the bottom crown N trap, to change the C-V characteristic of electric capacity.
Described bottom crown N trap, according to different manufacturing process, it is that P trap or P trap are deepened the boron injection that the bottom crown N trap in this capacitance structure changes into, corresponding trap contact becomes the P+ diffusion region by N+.
Beneficial effect: under the situation that does not increase any processing step, by using the mode of one deck ONO electric capacity that on poly1/Nw or poly1/diff electric capacity, superposes again, the unit of capacity area capacitance value Cox that makes stack is increased to 4.1ff/um2 from the Cox=2.5ff/um2 of typical poly1/Nw or poly1/diff, be that the unit-area capacitance value has increased by 64%, improved the integrated level of electric capacity greatly, and and the existing processes compatibility, do not need to increase extra operation.
Under the prerequisite that does not increase manufacturing cost, use this structure capacitive, can make that the area of electric capacity reduces about 38% in the circuit. for a large amount of various analog circuits that use electric capacity in the circuit structure, adopt this structure overlap capacitance, can dwindle chip area greatly, reduce the production cost of single circuit, enhance competitiveness.
Description of drawings
Fig. 1 Poly/well and ONO overlap capacitance basic structure schematic diagram.The trap target is Nwell among the figure, and reality also can be Pwell, and corresponding trap contact becomes P+ by N+.
Fig. 2 Poly/diff and ONO overlap capacitance basic structure schematic diagram.The trap target is Nwell and Nsinker among the figure, also can be that Pwell and boron inject, and corresponding trap contact becomes P+ by N+.
Fig. 3 Poly/well and ONO overlap capacitance utility structure schematic diagram.The trap target is Nwell among the figure, and reality also can be Pwell, and corresponding trap contact becomes P+ by N+.
Fig. 4 Poly/diff and ONO overlap capacitance utility structure schematic diagram.The trap target is Nwell and Nsinker among the figure, also can be that Pwell and boron inject, and corresponding trap contact becomes P+ by N+.
Wherein have:
The 1-P substrate slice, 2-N trap, 3-N sinker diffusion region, the 4-N+ diffusion region, the little active area of 5-, the big active area of 6-, 7-place, the dielectric layer of 8-poly1/well electric capacity, 9-middle plate polycrystalline, the dielectric layer of 10-poly2/poly1ONO electric capacity, 11-top crown polycrystalline, the 12-multilevel oxide, 13-ground floor metal line.
Embodiment
The present invention passes through at the top crown Poly1 of Poly/well, Poly/diff electric capacity (ground floor polysilicon) superficial growth one deck ono dielectric, and then deposit one deck Poly2 (second layer polysilicon) makees the 3rd pole plate, by metallization wiring the well of the Poly2 and the bottom or diff short circuit are picked out the utmost point as electric capacity at last, Poly1 picks out as another utmost point, so just formed the electric capacity of ONO electric capacity and Poly1/well, the stack of Poly1/diff electric capacity, can improve unit-area capacitance value, Cox=1.6ff/um2+2.5ff/um2=4.1ff/um2 greatly.
Poly1/well, Poly1/diff capacitor dielectric are that the gate oxide of the epontic gate oxide of well and mos pipe (metal oxide semiconductor field effect tube) is grown simultaneously below the poly1, do not need other operation.The ono dielectric between Poly2/poly1 and the ono dielectric of standard are grown simultaneously, also do not need other operation.
Poly/well and ONO (polysilicon/trap electric capacity oxygenates-nitride-capacitive oxide) is consistent with these two kinds of overlap capacitance basic structures of Poly/diff and ONO (polysilicon/diffusion region electric capacity oxygenates-nitride-capacitive oxide), shown in accompanying drawing 1, accompanying drawing 2.
Because the doping content of bottom crown is variant, the C-V characteristic of electric capacity has certain difference.
In the manufacture process of reality, for the requirement of the dielectric withstanding voltage, medium tunnelling current, anti-SILC characteristic and the medium life-span aspect that make electric capacity can reach actual instructions for use, the practical structures of capacitance structure must be optimized, through the structure of optimizing, could in manufacture process, stand the corrosion of various etching procedure ionic mediums, guarantee the integrality and the uniformity of dielectric layer.The capacitance structure of the practicality of satisfied manufacturing of energy and instructions for use as shown in Figure 3, Figure 4.
The structure of overlap capacitance in the semiconductor fabrication process: the capacitor regions 2 at P substrate slice 1 upper surface is N traps, and diffusion 2 ~ 4um is dark downwards from silicon chip surface for the N trap, constitutes the bottom crown of electric capacity; The silicon face of capacitor regions just bottom crown N trap surface be a big active area 6, a little active area 5: little active area 5 has N+ to inject the diffusion region---to form ohmic contact down by contact hole and metal line, as the exit of bottom crown; Big active area 6 is as the effective coverage of poly1/well electric capacity in the overlap capacitance; Be exactly place 7 outside the active area, above the place be
Thick oxide is as the isolation between the active area; The silicon face of active area is one deck
Thick oxide, the oxide on big active area 6 surfaces has just constituted the dielectric layer 8 of poly1/well electric capacity in capacitor regions; On the thin oxide in the surface, effective coverage of poly1/well electric capacity is one deck
Polysilicon, the area of polysilicon is more slightly bigger than the effective coverage area of poly1/well electric capacity, has extended on the other place of big active area, this layer polysilicon just constituted the middle plate 9 of electric capacity; Do not have polysilicon above the little active area, there is the polysilicon that extends up at the edge except the effective coverage active area that is close to poly1/well electric capacity on the place, and all the other zones do not have polysilicon yet; Upper surface at polysilicon is one deck
Ono dielectric 10, this layer medium constituted the dielectric layer 10 of poly2/poly1 ONO electric capacity in the overlap capacitance; Be second layer polysilicon on ono dielectric, constituted the top crown 11 of electric capacity, the area of this layer polysilicon is smaller than the area of the effective coverage active area of poly1/well electric capacity, and other zones do not have second layer polysilicon; On second layer polysilicon be cover whole wafer surface 6000～
Oxide, be referred to as multilevel oxide 12, the oxide directly over the polysilicon is the thinnest, the oxide directly over the bottom crown exit N+ diffusion region is the thickest; Multilevel oxide can be constituted the contact hole of through N+ or polysilicon surface by the place to go in the place of drawing of bottom crown exit N+ diffusion region, poly1, the relevant position of drawing the place of poly2; Be exactly ground floor metal line 13 directly over multilevel oxide, in the position of contact hole, metal line contacts with N+ or polysilicon surface, and the two ends of electric capacity are drawn respectively, forms a complete overlap capacitance structure.
Regular size crucial in this structure is:
1, poly1 must extend on the oxygen of showing up, and the cont of poy1 (contact hole) also must open on the poly1 on the oxygen on the scene.
2, the edge of poly2 is to the necessary certain spacing that guarantees at active area edge.
The manufacture process process of this electric capacity is as follows:
The P substrate slice is prepared
Once oxidation
BN (N buried regions) exposure, development
Antimony injects, advances
BP (P buried regions) exposure, development
The boron ion injects, advances (for CMOS technology, injecting, push away trap, is unwanted) from the once oxidation to B+
The N epitaxial growth
Oxidation
The exposure of N trap, development
Phosphorus injects
The exposure of P trap, development
The boron ion injects
Advance and form 1. Nwell of bottom crown
Buffer oxide
The low pressure silicon nitride deposition
Active area exposure, development
Silicon nitride etch
Annotate the P field: the general notes of phosphonium ion
The N field is annotated exposure, is developed
N field boron difluoride ion injects
The field oxidation
Silicon nitride is shelled entirely
Wet etching, cleaning
Gate oxidation forms Poly1/well, Poly1/diff capacitor dielectric
N sinker exposure, development form 2. diff of bottom crown
Phosphonium ion injects, advances
A polysilicon deposit
The general notes of phosphorus
LP TEOS (deposit of low pressure tetraethoxysilane), densification
A polysilicon exposure, development
A polysilicon polysilicon corrosion forms electric capacity middle plate poly1
The oxidation of a polysilicon polycrystalline
The low pressure silicon nitride deposition
The silicon nitride oxidation
ONO exposure, development
The ONO corrosion
The secondary gate oxidation
Threshold voltage is adjusted the boron ion and is injected
Base exposure, development
The boron difluoride ion injects
Emitter region photoetching, development
The emitter region corrosion
The deposit of secondary polysilicon
Polysilicon emissioning area arsenic injects
Rapid thermal annealing (for CMOS technology, it is unwanted exposing, develop to RTA from Base)
The exposure of secondary polysilicon, development
The secondary etching polysilicon forms top crown poly2
The exposure of N type lightly doped drain, development
Phosphorus injects
Side wall forms
N type source is leaked exposure, is developed
Arsenic injects
P type source is leaked exposure, is developed
The boron difluoride ion injects
Boracic, the deposit of phosphorus tetraethoxysilane
Reflux
Contact hole exposure, development
Contact hole etching
Metal one deposit
Metal one exposure, development
Metal one alloy
... the metallization operation in road, back is omitted.
Claims (3)
1. the structure of overlap capacitance in the semiconductor fabrication process, it is characterized in that: the capacitor regions (2) at P substrate slice (1) upper surface is a N trap, diffusion 2～4um is dark downwards from silicon chip surface for the N trap, constitutes the bottom crown of electric capacity; The silicon face of capacitor regions just bottom crown N trap surface be a big active area (6), a little active area (5): little active area (5) has N+ to inject the diffusion region---to form ohmic contact down by contact hole and metal line, as the exit of bottom crown; Big active area (6) is as the effective coverage of the 1/ trap electric capacity of polysilicon in the overlap capacitance; Be exactly place (7) outside the active area, above the place be
Thick oxide is as the isolation between the active area; The silicon face of active area is one deck
Thick oxide, the oxide on big active area (6) surface has just constituted the dielectric layer (8) of polysilicon 1/ trap electric capacity in capacitor regions; On the thin oxide in the surface, effective coverage of polysilicon 1/ trap electric capacity is one deck
Polysilicon, the area of polysilicon is more slightly bigger than the effective coverage area of polysilicon 1/ trap electric capacity, has extended on the other place of big active area, this layer polysilicon just constituted the middle plate (9) of electric capacity; Do not have polysilicon above the little active area, there is the polysilicon that extends up at the edge except the effective coverage active area that is close to polysilicon 1/ trap electric capacity on the place, and all the other zones do not have polysilicon yet; Upper surface at polysilicon is one deck
Ono dielectric (10), this layer medium constituted the dielectric layer (10) of polysilicon 2/ polysilicon 1 ONO electric capacity in the overlap capacitance; Be second layer polysilicon on ono dielectric, constituted the top crown (11) of electric capacity, the area of this layer polysilicon is smaller than the area of the effective coverage active area of polysilicon 1/ trap electric capacity, and other zones do not have second layer polysilicon; Be to cover the whole wafer surface on second layer polysilicon
Oxide, be referred to as oxide skin(coating) (12), the oxide directly over the polysilicon is the thinnest, the oxide directly over the bottom crown exit N+ diffusion region is the thickest; Multilevel oxide can be constituted the contact hole of through N+ or polysilicon surface by the place to go in the place of drawing of bottom crown exit N+ diffusion region, polysilicon 1, the relevant position of drawing the place of polysilicon 2; Be exactly ground floor metal line (13) directly over multilevel oxide, in the position of contact hole, metal line contacts with N+ or polysilicon surface, and the two ends of electric capacity are drawn respectively, forms a complete overlap capacitance structure.
2. the structure of overlap capacitance in the semiconductor fabrication process as claimed in claim 1, it is characterized in that described bottom crown N trap, according to the requirement different, add a highly doped Nsinker diffusion region (3) in the bottom crown N trap, to change the C-V characteristic of electric capacity to capacitance characteristic.
3. the structure of overlap capacitance in the semiconductor fabrication process as claimed in claim 1, it is characterized in that described bottom crown N trap, according to different manufacturing process, it is that P trap or P trap are deepened the boron injection that the bottom crown N trap in this capacitance structure changes into, and corresponding trap contact becomes the P+ diffusion region by N+.
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| CN103985707A (en) * | 2014-04-24 | 2014-08-13 | 无锡市晶源微电子有限公司 | Capacitor of sandwich structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1670875A (en) * | 2004-03-19 | 2005-09-21 | Tdk株式会社 | Multilayer capacitor |
| CN1318869C (en) * | 2003-06-24 | 2007-05-30 | 三星电子株式会社 | Coupling structure for optical waveguide and optical device and optical alignment method by using the same |
| CN101414606A (en) * | 2007-10-16 | 2009-04-22 | 东部高科股份有限公司 | Stack capacitor in semiconductor device and method for fabricating the same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1318869C (en) * | 2003-06-24 | 2007-05-30 | 三星电子株式会社 | Coupling structure for optical waveguide and optical device and optical alignment method by using the same |
| CN1670875A (en) * | 2004-03-19 | 2005-09-21 | Tdk株式会社 | Multilayer capacitor |
| CN101414606A (en) * | 2007-10-16 | 2009-04-22 | 东部高科股份有限公司 | Stack capacitor in semiconductor device and method for fabricating the same |
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Address after: No. 5, Xijin Road, Xinwu District, Wuxi City, Jiangsu Province, 214000 Patentee after: Wuxi Jingyuan Microelectronics Co.,Ltd. Address before: Room 209, Building A, Plot 106-C, Wuxi National High tech Industrial Development Zone, Wuxi City, Jiangsu Province, 214028 Patentee before: Wuxi Jingyuan Microelectronics Co.,Ltd. |
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