CN101853850B - Super barrier semiconductor rectifying device and manufacture method thereof - Google Patents
Super barrier semiconductor rectifying device and manufacture method thereof Download PDFInfo
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Abstract
The invention relates to a super barrier semiconductor rectifying device and a manufacture method thereof. The super barrier semiconductor rectifying device comprises a first conductive type substrate and a first conductive type drifting region, wherein a groove type MOS tube structure is adopted in the first conductive type drifting region, the outer side of the groove is provided with a contact hole, the positions above the outer wall sides of the groove and the contact hole are respectively provided with a first conductive type implanted layer, an insulation oxidizing layer is covered on the inner wall of the groove, a first electrode is deposited in the groove, the bottom of the contact hole is provided with a second conductive type covering layer, a first metal is deposited above a first main surface, the contact hole is filled with the first metal, the first metal is in ohmic contact with the first electrode, a second metal layer is covered on the second main surface of the semiconductor base plate, and the second metal layer and the first conductive type substrate are in ohmic contact. The invention reduces the positive direction pressure drop of the rectifying device, improves the structure cell integration density of the rectifying device in the unit area, reduces the manufacture cost of the rectifying device, and enlarges the process window of the device manufacture.
Description
Technical field
The present invention relates to a kind of power semiconductor rectifying device and manufacture method thereof, especially a kind of superpotential barrier semiconductor rectifying device and manufacture method thereof.
Background technology
The power semiconductor rectifying device includes Schottky barrier rectifier, and Schottky barrier rectifier is to contact with semiconductor with noble metal (as gold, silver, platinum, titanium, nickel, molybdenum etc.), the semiconductor device of making to form potential barrier of heterogenous junction.In view of the architectural feature of Schottky barrier rectifier, it has following weak point:
1), metal and semi-conductive contact berrier directly influenced the forward conduction voltage drop of Schottky barrier rectifier, in order to satisfy the demand of different components forward conduction voltage drop, can select different kinds of metals usually, complexity that can corresponding increase manufacturing process;
2), the reverse leakage current of Schottky barrier rectifier can increase with the rising of temperature usually, the increase of leakage current can make the rectifier temperature raise again; Therefore, reduced stability and the reliability of Schottky barrier rectifier in application;
3), use precious metal material to contact the manufacturing cost height with semiconductor; And pollute because heavy metal exists, its manufacturing process and CMOS standard technology are difficult to compatibility.
At present Chinese patent ZL01143693.X and Chinese patent ZL01800833.X disclose a kind of " making power rectifier device to change improving one's methods and obtained device of running parameter " and " preparing power rectifier device with the method for change operating parameter and the device that makes thereof " respectively.Described two kinds of semiconductor rectifier devices do not use Schottky barrier, the structure of described two kinds of semiconductor rectifiers is shown in accompanying drawing 2J among accompanying drawing 4 among the patent ZL01143693.X and the patent ZL01800833.X, its fundamental idea of the invention is: vertical semiconductor rectifying device, its effective rectification unit comprise PN junction structure and MOS structure in parallel; Be example when being the N type with first conduction type, the MOS structural equivalents of device is the barrier MOS pipe of N type raceway groove; Device is when forward bias condition, the drain electrode of this N type raceway groove barrier MOS pipe becomes equipotential with the grid short circuit, the grid of metal-oxide-semiconductor and the voltage between the source electrode equal the drain electrode of metal-oxide-semiconductor and the voltage between the source electrode, this moment is because the inclined to one side effect of lining of metal-oxide-semiconductor, the barrier MOS pipe is opened when hanging down forward bias, and device is operated under the conducting state.Device is when reverse bias condition, and the source electrode of this N type raceway groove barrier MOS pipe becomes zero potential with the grid short circuit, and at this moment, the barrier MOS pipe is in cut-off state, and the PN junction in PN junction district exhausts fast, bears reversed bias voltage, and the reverse leakage current size of device is determined by PN junction.
Yet because plane MOS structure has been adopted in described two kinds of rectifying device important component part barrier MOS areas under control, it certainly exists following problem:
1, between two raceway grooves of plane metal-oxide-semiconductor district grid oxygen below, have a parasitic JFET (junction field effect transistor) resistance, this has limited device forward voltage drop V
fThe space that further reduces.
2, described barrier MOS pipe occupies the chip area over half of rectifying device; The integrated level of chip is the important component part of rectifying device chip cost.And plane MOS structure has restricted the cellular integrated level of device in unit are greatly, and adopting plane MOS structure is the bottleneck that rectifying device chip manufacturing cost further reduces.
3, among the described patent ZL01800833.X, the formation of device lateral channel is to form the ion implantation mask of inclination with isotropic etch, inject the horizontal gradual PN junction that ion forms channel region by it, shown in Figure 14 A among the patent ZL01143693.X and Figure 14 B; Among the Chinese patent ZL01800833.X, the device lateral channel be with the mask behind the isotropic etching as the barrier layer, inject thereafter that ion forms, as Fig. 2 I among the patent ZL01800833.X; The length of described two kinds of device channel (0.25um is to 0.1um) depends on the size and the pattern of corrosion back mask layer.And in actual process, the precision of lithography registration and the condition of corrosion to etching after size, the pattern of mask layer significant effects is arranged; The size of mask layer is different with pattern, can cause the process window of channel length less, thereby makes forward voltage drop V
fProcess window less.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, a kind of superpotential barrier semiconductor rectifying device and manufacture method thereof are provided, it has reduced the forward voltage drop of rectifying device, improved the cellular integrated level of rectifying device in unit are, reduced the manufacturing cost of rectifying device and increased the process window that device is made.
According to technical scheme provided by the invention, described superpotential barrier semiconductor rectifying device, on the cross section of described rectifier, comprise semiconductor substrate with two relative interareas, the rectification unit that the PN junction district by metal-oxide-semiconductor district and adjacent described metal-oxide-semiconductor district constitutes is set in the described semiconductor substrate; Its innovation is:
On the cross section of described rectifier, the metal-oxide-semiconductor of described rectification unit adopts groove structure; One or more grooves extend into second conductive type layer from first interarea, and the degree of depth stretches into the first conduction type drift region of second conductive type layer below; The outside of described groove is provided with contact hole; The outer wall side top of described groove and contact hole is equipped with the first conduction type implanted layer; The bottom of described contact hole is positioned at the below of the first conduction type implanted layer;
On the cross section of described rectifier, described semiconductor substrate comprises first conductivity type substrate that is positioned at the semiconductor substrate bottom and is positioned at the first conduction type drift region on semiconductor substrate top that described first conductivity type substrate is in abutting connection with the first conduction type drift region; Top, the described first conduction type drift region is provided with second conductive type layer and the first conduction type implanted layer, the described first conduction type implanted layer be positioned at second conductive type layer directly over; The surface of described first conductivity type substrate is second interarea of semiconductor substrate, and the surface of the described first conduction type drift region is first interarea of semiconductor substrate; The doping content of the described first conduction type drift region is lower than the doping content of first conductivity type substrate;
Be coated with insulating oxide on the described trench wall, deposit first electrode in the described groove that is coated with insulating oxide; The bottom of described contact hole is provided with the second conduction type embracing layer, and the described second conduction type embracing layer coats the bottom of contact hole, and the second conduction type embracing layer contacts with second conductive type layer; The top of described first interarea is deposited with first metal; The described first metal filled contact hole, and with the first electrode ohmic contact; Described the first metal layer, insulating oxide, first electrode, the first conduction type implanted layer and the second conduction type interlayer form the groove MOS tubular construction; The described first conduction type implanted layer and the second conduction type interlayer form the PN junction district of contiguous described groove MOS pipe; Described trench MOS structure constitutes rectification unit with the PN junction district of contiguous described groove MOS pipe; Described first metal and the first conduction type implanted layer, second conductive type layer and the second conduction type embracing layer electrically connect; Be coated with second metal level on second interarea of described semiconductor substrate, described second metal level and first conductivity type substrate be ohmic contact mutually.
Described first electrode comprises conductive polycrystalline silicon.Described trench wall forms insulating oxide by heat growth or deposit.Described the first metal layer is provided with anode tap.Described second metal level is provided with cathode terminal.
The manufacture method of described superpotential barrier semiconductor rectifying device comprises the steps:
A, provide the first conductive type semiconductor substrate with two relative interareas, described two relative interareas comprise first interarea and second interarea; B, on above-mentioned first interarea, the deposit hard mask layer; C, optionally shelter and the etching hard mask layer, form the hard mask of etching groove, and etching forms groove on first interarea, described groove is coated with hard mask layer corresponding to the outer remainder of notch; Hard mask layer on d, described semiconductor substrate first interarea of removal; E, insulating oxide is arranged in above-mentioned trench wall superficial growth; F, in having the groove of insulating oxide, described growth forms first electrode; G, on first interarea of above-mentioned semiconductor substrate, inject the ion of first conduction type, above the outer wall side of described groove, form the first conduction type implanted layer; H, selectivity is laid mask layer, the notch of described mask layer covering groove on first interarea of described semiconductor substrate; Form contact hole by exposing, being developed on first interarea, the bottom of described contact hole is positioned at first conduction type implanted layer below; I, inject the ion of second conduction type on first interarea of above-mentioned semiconductor substrate, form the second conduction type embracing layer in the bottom of contact hole, the described second conduction type embracing layer coats the bottom of contact hole; Mask layer on j, described semiconductor substrate first interarea of removal; K, on first interarea of above-mentioned semiconductor substrate, inject the ion of second conduction type, and the high temperature knot forms second conductive type layer in semiconductor substrate, described second conductive type layer be positioned at the first conduction type implanted layer under; Described second conductive type layer contacts with the second conduction type embracing layer; Described second conductive type layer is positioned at the top of above-mentioned groove bottom land; L, on first interarea of described semiconductor substrate deposit first metal, the described first metal filled contact hole; By selectivity and etching first metal, on first interarea of described semiconductor substrate, form the first metal layer; The first electrode ohmic contact in described the first metal layer and the groove, and electrically connect with the first conduction type implanted layer, second conductive type layer and the second conduction type embracing layer; M, on second interarea of described semiconductor substrate, cover second metal level, the first conductivity type substrate ohmic contact of described second metal level and semiconductor substrate.
Described hard mask layer is that LPTEOS, thermal oxidation silicon dioxide add chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.Described mask layer comprises photoresist.The material of described semiconductor substrate comprises silicon.The described first conduction type implanted layer, second conductive type layer, the second conduction type embracing layer and the first electrode equipotential.
Described " first conduction type " and " second conduction type " are among both, and for the N type semiconductor rectifier, first conduction type refers to the N type, and second conduction type is the P type; For the P type semiconductor rectifier, first conduction type is just in time opposite with the type and the N type semiconductor rectifier of the second conduction type indication.
Advantage of the present invention:
1, the metal-oxide-semiconductor structure of rectification unit adopts the metal-oxide-semiconductor structure of plough groove type, the PN junction that forms between the PN junction that the described metal-oxide-semiconductor and the first conduction type implanted layer, the second conduction type interlayer form and second conductive type layer, the second conduction type embracing layer and the first conduction type drift region is in parallel, avoid the JEFT effect of rectifier midplane type metal-oxide-semiconductor district generation, improved the forward voltage drop V of rectifier greatly
fCharacteristic.
2, by the corresponding second conductive type layer injection condition, gash depth and the contact hole degree of depth of regulating, can obtain different forward voltage drop V easily
fCharacteristic, i.e. forward voltage drop V
fCharacteristics Control is more simple.
3, the raceway groove of the described first conduction type implanted layer and second conduction type interlayer formation is that the general notes after annealing of ion forms, and described channel length depends primarily on the condition of ion injection and the condition of subsequent anneal, can accurately control channel length.
4, by the groove MOS pipe structure in parallel, increased current density, for raising device cell density, reducing cost provides the space with PN junction.
Description of drawings
Fig. 1 a is a structural representation of the present invention.
Fig. 1 b is the equivalent circuit diagram of superpotential barrier semiconductor rectifying device of the present invention.
Fig. 2～Fig. 9 is the concrete process implementing profile of the present invention, wherein:
Fig. 2 is the cutaway view of semiconductor substrate.
Fig. 3 is the cutaway view behind the formation groove in the first conduction type drift region.
Fig. 4 is the cutaway view after trench wall forms insulating oxide.
Fig. 5 is the cutaway view behind formation first electrode in groove.
Fig. 6 is the cutaway view after the first conduction type implanted layer is formed at top, the first conduction type drift region.
Fig. 7 is the cutaway view behind the formation contact hole in the first conduction type drift region.
Fig. 8 is the cutaway view after the second conduction type embracing layer is formed on the bottom of contact hole.
Fig. 9 is the cutaway view after forming second metal level on second interarea.
Embodiment
As Fig. 1 a, Fig. 1 b, Fig. 2～shown in Figure 9: with the N type semiconductor rectifier is example, the present invention includes N+ substrate 1, N type drift region 2, groove 3, insulating oxide 4, first electrode 5, N+ implanted layer 6, mask layer 7, contact hole 8, P+ embracing layer 9, P trap layer 10, the first metal layer 11, second metal level 12, PN junction 13, MOS structure 14, rectification unit 15, hard mask layer 16, anode tap 17 and cathode terminal 18.
Fig. 9 and Fig. 1 a are the cutaway view of described superpotential barrier semiconductor rectifying device.Shown in Fig. 9 and Fig. 1 a: as described on the cross section of superpotential barrier semiconductor rectifying device, described semiconductor rectifier comprises semiconductor substrate, described semiconductor substrate comprises N+ substrate 1 and N type drift region 2, described N type drift region 2 is in abutting connection with N+ substrate 1, and the doping content of N type drift region 2 is greater than the doping content of N+ substrate 1.Described semiconductor substrate has two relative interareas, and semiconductor substrate is first interarea corresponding to the surface of N type drift region 2; Semiconductor substrate is second interarea corresponding to the surface of N+ substrate 1, and described second interarea is corresponding with the position of first interarea.The top of described N type drift region 2 is provided with P trap layer 10; The MOS structure adopts groove structure in the described N type drift region 2, comprises a groove 13 at least in the described N type drift region 2.Described groove 3 is positioned at P trap layer 10, and the degree of depth stretches in the N type drift region 2 of P trap layer 10 below.Growth has an insulating oxide 4 on described groove 3 inwalls, deposit first electrode 5 in described growth has the groove 3 of insulating oxide 4, and described first electrode 5 comprises conductive polycrystalline silicon.The side top of described groove 3 outer walls is provided with N+ implanted layer 6, and described N+ implanted layer 6 is positioned at the top of P trap layer 10, and contacts with P trap layer 10.When groove 3 is one, the arranged outside contact hole 8 of described groove 3.On the cross section of described superpotential barrier semiconductor rectifier, when groove 3 when being a plurality of, 3 of described adjacent trenches are provided with contact hole 8, and the bottom of described contact hole 8 is positioned at N+ implanted layer 6 belows; The bottom of contact hole 8 is provided with P+ embracing layer 9, and described P+ embracing layer 9 contacts with P trap layer 10; The P trap layer 10 of described contact hole 8 both sides is connected by P+ embracing layer 9.
Deposit the first metal layer 11 on first interarea of described semiconductor substrate, described the first metal layer 11 filling contact holes 8, and with groove 3 in first electrode, 5 ohmic contact.Described the first metal layer 11 covers on first interarea of semiconductor substrate, and the first metal layer 11 electrically connects with N+ implanted layer 6, P trap layer 10 and P+ embracing layer 9, thereby makes first electrode 5, N+ implanted layer 6, P trap layer 10 and P+ embracing layer 9 have same potential.Described the first metal layer 11 is provided with anode tap 17, is used for being connected with the power supply that needs rectification.Be coated with second metal level 12 on the described N+ substrate 1, described second metal level 12 and N+ substrate 1 ohmic contact is provided with cathode terminal 18 on described second metal level 12.Be connected with the power supply that needs rectification by described cathode terminal 18, anode tap 17, constitute two links of rectifier.
As Fig. 1 a and shown in Figure 9: as described in the P trap layer 10 of N+ implanted layer 6 and N+ implanted layer 6 belows form a PN junction 13; P trap layer 10 links into an integrated entity with P+ embracing layer 9, and P trap layer 10, P+ embracing layer 9 also form PN junction 13 structures with N type drift region 2.On the cross section of described superpotential barrier semiconductor rectifier, the first metal layer 11 and first electrode 5, N+ implanted layer 6 and P trap layer 10 are in contact, thereby form groove-shaped metal-oxide-semiconductor structure; 10 on the N+ implanted layer 6 of described groove 3 both sides and P trap layer form the PN junction structure; Therefore can access the equivalent structure that MOS structure 14 and PN junction structure 13 are in parallel among Fig. 1 b, described groove type MOS tubular construction forms rectification unit with contiguous described groove MOS pipe PN junction district.
The structure of above-mentioned superpotential barrier semiconductor rectifying device adopts following processing step to realize:
A, provide the first conductive type semiconductor substrate with two relative interareas, described two relative interareas comprise first interarea and second interarea; Described semiconductor substrate is second interarea corresponding to the bottom surface of N+ substrate 1, and semiconductor substrate is first interarea corresponding to the upper surface of N type drift region 2, as shown in Figure 2;
B, on above-mentioned first interarea, deposit hard mask layer 16; 16 layers of described hard masks can adopt LPTEOS (plasma-enhanced tetraethyl orthosilicate), thermal oxidation silicon dioxide adds chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride, forms hard mask by photoetching and anisotropic etching thereafter;
C, optionally shelter and etching hard mask layer 16, form the hard mask of etching groove, and etching forms groove 3 on first interarea, described groove 3 is coated with hard mask layer 16 corresponding to the outer remainder of notch, described etching groove adopts plasma anisotropic etching, form the trenched side-wall (angle of trenched side-wall and semiconductor substrate is not less than 88 degree) of near vertical, groove 3 degree of depth need be considered the needs of component characteristic parameter, described groove 3 degree of depth are generally 0.4 μ m～2 μ m, and through behind the etching groove, hard mask layer between groove above the table top portion also keeps certain thickness, and concrete thickness need be considered follow-up injection technology condition, as shown in Figure 3;
E, insulating oxide 4 is arranged in the growth of above-mentioned groove 3 inner wall surface; The method that described insulating oxide 4 can adopt high temperature furnace pipe growth, chemical vapour deposition (CVD) or high temperature furnace pipe growth to combine with chemical vapour deposition (CVD) is grown on the inwall of groove 3, as shown in Figure 4;
F, in described growth has the groove 4 of insulating oxide 4 the deposit conductive polycrystalline silicon, described conductive polycrystalline silicon is boiler tube growth or chemical vapour deposition (CVD) heavily doped polysilicon, remove the conductive polycrystalline silicon of semiconductor substrate by etching corresponding to first interarea, obtain being positioned at the conductive polycrystalline silicon of groove 4, thereby form first electrode 5, as shown in Figure 5;
In certain embodiments, can remove the partially conductive polysilicon of semiconductor substrate, obtain being positioned at first electrode 5 of groove 3 and first electrode 5 on first interarea by etching corresponding to first interarea;
In certain embodiments, also can remove the conductive polycrystalline silicon of semiconductor substrate, obtain being positioned at first electrode 5 of groove 3 by etching corresponding to first interarea; Thereafter deposit one deck conductive polycrystalline silicon on first interarea of semiconductor substrate again obtains first electrode 5 on first interarea;
In certain embodiments, also can remove the conductive polycrystalline silicon of semiconductor substrate, obtain being positioned at first electrode 5 of groove 3 by etching corresponding to first interarea;
In certain embodiments, also can be when the operation of etching conductive polysilicon, conductive polycrystalline silicon except removing groove 3 is also removed the conductive polycrystalline silicon of groove 3 internal upper parts, thereafter and remove the insulating oxide 4 that groove 3 internal upper parts do not have the trenched side-wall of first electrode, 5 parts;
G, inject N type foreign ion (as arsenic element) on first interarea of above-mentioned semiconductor substrate, form N type implanted layer 6 on the top of described N type drift region 2, described N+ implanted layer 6 is positioned at the side top of groove 3 outer walls, as shown in Figure 6;
In certain embodiments, after injecting N type foreign ion on first interarea of semiconductor substrate, also can form N type implanted layer 6 by increasing high temperature knot process;
H, selectivity is laid mask layer 7, the notch of described mask layer 7 covering grooves 3 on first interarea of described semiconductor substrate; Form contact hole 8 on first interarea by exposing, being developed in, the bottom of described contact hole 8 is positioned at N+ implanted layer 6 belows, as shown in Figure 7;
Described mask layer 7 comprises photoresist, and by optionally being coated with photoresist on first interarea, by form contact hole 8 after exposure, the development step on first interarea, promptly photoresist is as contact hole 8 etch mask layers 7;
I, inject the p type impurity ion on first interarea of above-mentioned semiconductor substrate, form P+ embracing layer 9 in the bottom of contact hole 8, described P+ embracing layer 9 coats the bottom of contact holes 8;
In certain embodiments, after first interarea of semiconductor substrate injects the p type impurity ion, also can form P+ embracing layer 9 in the bottom of contact hole 8 by high temperature knot process;
Mask layer 7 on j, described semiconductor substrate first interarea of removal;
K, on first interarea of above-mentioned semiconductor substrate, inject the p type impurity ion, and the high temperature knot forms P trap layer 10 in semiconductor substrate, described P trap layer 10 be positioned at N+ implanted layer 6 under, and contact with P+ embracing layer 6, described P trap layer 10 is positioned at the top of groove 3 bottom lands, be the degree of depth that the degree of depth of P trap layer 10 is shallower than groove 3, as shown in Figure 8;
The p type impurity ion that injects among the described step k is different at aspects such as energy with step I p type impurity ion, but is the p type impurity ion; In the process that forms P trap layer 10, also can in P+ embracing layer 9, inject the p type impurity ion; P trap layer 10 under the described N+ implanted layer 6 is connected with the P+ embracing layer 9 of contact hole 8 bottoms;
L, on first interarea of described semiconductor substrate deposit first metal, the described first metal filled contact hole 8; By selectivity and etching first metal, on first interarea of described semiconductor substrate, form the first metal layer 11; First electrode, 5 ohmic contact in described the first metal layer 11 and the groove 3, and electrically connect with N+ implanted layer 6, P trap layer 10 and P+ embracing layer; The described first conduction type implanted layer, second conductive type layer, the second conduction type embracing layer and the first electrode equipotential; Described the first metal layer 8 contacts with first electrode 10, forms the anode electrode of rectifier, by anode tap 17 is set on the first metal layer 11, is convenient to the first metal layer 11 and is connected with the power end that needs rectification
M, on second interarea of described semiconductor substrate, cover second metal level 12, N+ substrate 1 ohmic contact of described second metal level 12 and semiconductor substrate, form the cathode electrode of rectifier, by on second metal level 12, cathode terminal 18 being set, be convenient to second metal level 12 and be connected, as described in Figure 9 with the power end that needs rectification.
As Fig. 1 b and shown in Figure 9: the working mechanism of superpotential barrier semiconductor rectifying device of the present invention is: a kind of groove-shaped superpotential barrier semiconductor rectifying device, described semiconductor rectifier can equivalence be the rectification unit of several PN junction that is in parallel 13 structures and N type MOS structure 14 formations.Described first electrode 5 is the gate terminal of MOS structure 14, and N+ implanted layer 6 is the source terminal of MOS structure 14; Described N+ implanted layer 6 is connected by the first metal layer 11 with first electrode 5, i.e. N+ implanted layer 6 and 5 equipotentials of first electrode.The channel length of described equivalent PN junction 13 structures is the length difference of 10 on N+ implanted layer 6 and P trap layer.When adding forward bias voltage on the described semiconductor rectifier, be that 18 of anode tap 17 and cathode terminals are when having positive electrical potential difference, the source electrode of the groove-shaped barrier MOS pipe of this N type raceway groove utilizes the first metal layer 11 short circuits to become equipotential with grid, and the drain electrode of metal-oxide-semiconductor and the voltage between the grid equal the drain electrode of metal-oxide-semiconductor and the voltage between the source electrode; At this moment, because the inclined to one side effect of lining of metal-oxide-semiconductor, the cut-in voltage of described N type metal-oxide-semiconductor is lower than the cut-in voltage of independent metal-oxide-semiconductor.The cut-in voltage of described metal-oxide-semiconductor is subjected to the effect length of the thickness and PN junction structure 13 raceway grooves of insulating oxide 4 on groove 3 inwalls, when the relevant parameter of described insulating oxide layer thickness and raceway groove is complementary, the cut-in voltage of this barrier MOS pipe is lower than the junction barrier voltage in PN junction district, then when semiconductor rectifier upper offset voltage was lower than the junction barrier voltage in PN junction district, the barrier MOS pipe also can be opened; This moment, rectifying device was in the forward conduction state, had accelerated the opening speed of described semiconductor rectifier device.The potential barrier of rectifying device is that its forward voltage drop is lower by few son generation of barrier MOS pipe channel region.
When described semiconductor rectifier device adds reverse bias voltage, be 18 of anode tap 17 and cathode terminals have negative electrical potential difference the time, the P+ embracing layer 9 of N type drift region 2 below contact hole 8 bottoms constitutes back-biased PN junction, because P+ embracing layer 9 concentration are greater than the concentration of N type drift region 2, therefore 2 extensions in the N type drift region around the PN junction that anti-depletion layer can be most partially, described bearing of trend comprises horizontal direction.When the depletion layer that PN junction produced below adjacent two contact hole 8 bottoms contacts in the horizontal direction, the depletion layer that is connected has promptly been blocked the top of N type drift region 2 and the bottom of N type drift region 2, has also blocked simultaneously the reverse leakage circulation flow path of 18 of the anode tap 17 of rectifier and cathode terminals.And the source electrode of the N type raceway groove barrier MOS pipe of described semiconductor rectifier equivalence becomes equipotential with the grid short circuit, at this moment, the groove-shaped barrier MOS pipe of N type raceway groove is in cut-off state, and the PN junction of PN junction exhausts fast, bear reversed bias voltage, the reverse leakage current size of described semiconductor rectifier is determined by PN junction, can significantly reduce the size of reverse leakage current.
The metal-oxide-semiconductor structure of rectification unit of the present invention adopts the metal-oxide-semiconductor structure of plough groove type, the PN junction of described metal-oxide-semiconductor and N+ implanted layer 6,10 formation of P trap layer is in parallel, avoid the JEFT effect of rectifier midplane type metal-oxide-semiconductor district generation, improved the forward voltage drop V of rectifier greatly
fCharacteristic.By the bottom at contact hole 8 P+ embracing layer 9 is set, when the rectifier two ends added reverse bias voltage, the P+ embracing layer 9 of contact hole 8 bottoms formed the path that PN junction can stop reverse leakage current with N type drift region 2, significantly reduces reverse leakage current.The degree of depth by correspondence is regulated injection condition, groove 3 and the contact hole 8 of P trap layer 10 can obtain different forward voltage drop V easily
fCharacteristic, i.e. forward voltage drop V
fCharacteristics Control is more simple.Described N+ implanted layer 6 is that the general notes after annealing of ion forms with the raceway groove that P trap layer 10 forms, and described channel length depends primarily on the condition of ion injection and the condition of subsequent anneal, can accurately control channel length.By adopting groove MOS tubular construction 14 and PN junction structure 13 structure in parallel, increased current density, for raising device cell density, reducing cost provides the space.
Claims (10)
1. a superpotential barrier semiconductor rectifying device on the cross section of described rectifier, comprises the semiconductor substrate with two relative interareas, and the rectification unit that the PN junction district by metal-oxide-semiconductor district and adjacent described metal-oxide-semiconductor district constitutes is set in the described semiconductor substrate; It is characterized in that:
On the cross section of described rectifier, the metal-oxide-semiconductor of described rectification unit adopts groove structure; One or more grooves extend into second conductive type layer from first interarea, and the degree of depth stretches into the first conduction type drift region of second conductive type layer below; The outside of described groove is provided with contact hole; The outer wall side top of described groove and contact hole is equipped with the first conduction type implanted layer; The bottom of described contact hole is positioned at the below of the first conduction type implanted layer;
On the cross section of described rectifier, described semiconductor substrate comprises first conductivity type substrate that is positioned at the semiconductor substrate bottom and is positioned at the first conduction type drift region on semiconductor substrate top that described first conductivity type substrate is in abutting connection with the first conduction type drift region; Top, the described first conduction type drift region is provided with second conductive type layer and the first conduction type implanted layer, the described first conduction type implanted layer be positioned at second conductive type layer directly over; The surface of described first conductivity type substrate is second interarea of semiconductor substrate, and the surface of the described first conduction type drift region is first interarea of semiconductor substrate; The doping content of the described first conduction type drift region is lower than the doping content of first conductivity type substrate;
Be coated with insulating oxide on the described trench wall, deposit first electrode in the described groove that is coated with insulating oxide; The bottom of described contact hole is provided with the second conduction type embracing layer, and the described second conduction type embracing layer coats the bottom of contact hole, and the second conduction type embracing layer contacts with second conductive type layer; The top of described first interarea is deposited with first metal; The described first metal filled contact hole, and with the first electrode ohmic contact; Described first metal, insulating oxide, first electrode, the first conduction type implanted layer and the second conduction type interlayer form the groove MOS tubular construction; The described first conduction type implanted layer and the second conduction type interlayer form the PN junction district of contiguous described groove MOS pipe; Described groove MOS tubular construction constitutes rectification unit with the PN junction district of contiguous described groove MOS pipe; Described first metal and the first conduction type implanted layer, second conductive type layer and the second conduction type embracing layer electrically connect; Be coated with second metal level on second interarea of described semiconductor substrate, described second metal level and first conductivity type substrate be ohmic contact mutually.
2. superpotential barrier semiconductor rectifying device according to claim 1 is characterized in that: described first electrode comprises conductive polycrystalline silicon.
3. superpotential barrier semiconductor rectifying device according to claim 1 is characterized in that: described trench wall forms insulating oxide by heat growth or deposit.
4. superpotential barrier semiconductor rectifying device according to claim 1 is characterized in that: described first metal is provided with anode tap.
5. superpotential barrier semiconductor rectifying device according to claim 1 is characterized in that: described second metal level is provided with cathode terminal.
6. the manufacture method of a superpotential barrier semiconductor rectifying device is characterized in that, described manufacture method comprises the steps:
(a), provide the first conductive type semiconductor substrate with two relative interareas, the described first conductive type semiconductor substrate to comprise first conductivity type substrate that is positioned at the semiconductor substrate bottom and be positioned at the first conduction type drift region on semiconductor substrate top; The surface of described first conductivity type substrate is second interarea of semiconductor substrate, and the surface of the described first conduction type drift region is first interarea of semiconductor substrate;
(b), on above-mentioned first interarea, the deposit hard mask layer;
(c), optionally shelter and the etching hard mask layer, form the hard mask of etching groove, and etching forms groove on first interarea, described groove is coated with hard mask layer corresponding to the outer remainder of notch;
(d), the hard mask layer on described semiconductor substrate first interarea of removal;
(e), in above-mentioned trench wall superficial growth insulating oxide is arranged;
(f), in having the groove of insulating oxide, described growth forms first electrode;
(g), on first interarea of above-mentioned semiconductor substrate, inject the ion of first conduction type, above the outer wall side of described groove, form the first conduction type implanted layer;
(h), selectivity is laid mask layer, the notch of described mask layer covering groove on first interarea of described semiconductor substrate; Form contact hole by exposing, being developed on first interarea, the bottom of described contact hole is positioned at first conduction type implanted layer below;
(i), on first interarea of above-mentioned semiconductor substrate, inject the ion of second conduction type, form the second conduction type embracing layer in the bottom of contact hole, the described second conduction type embracing layer coats the bottom of contact hole;
(j), the mask layer on described semiconductor substrate first interarea of removal;
(k), on first interarea of above-mentioned semiconductor substrate, inject the ion of second conduction type, and the high temperature knot forms second conductive type layer in semiconductor substrate, described second conductive type layer be positioned at the first conduction type implanted layer under; Described second conductive type layer contacts with the second conduction type embracing layer; Described second conductive type layer is positioned at the top of above-mentioned groove bottom land;
(1), on first interarea of described semiconductor substrate deposit first metal, the described first metal filled contact hole; By etching first metal optionally, on first interarea of described semiconductor substrate, form the first metal layer; The first electrode ohmic contact in described the first metal layer and the groove, and electrically connect with the first conduction type implanted layer, second conductive type layer and the second conduction type embracing layer;
(m), on second interarea of described semiconductor substrate, cover second metal level, the first conductivity type substrate ohmic contact of described second metal level and semiconductor substrate.
7. the manufacture method of superpotential barrier semiconductor rectifying device according to claim 6 is characterized in that: described hard mask layer is that LPTEOS, thermal oxidation silicon dioxide add chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.
8. the manufacture method of superpotential barrier semiconductor rectifying device according to claim 6 is characterized in that: described mask layer comprises photoresist.
9. the manufacture method of superpotential barrier semiconductor rectifying device according to claim 6 is characterized in that: the material of described semiconductor substrate comprises silicon.
10. the manufacture method of superpotential barrier semiconductor rectifying device according to claim 6 is characterized in that: the described first conduction type implanted layer, second conductive type layer, the second conduction type embracing layer and the first electrode equipotential.
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| US8841664B2 (en) * | 2011-03-04 | 2014-09-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| CN103337523B (en) * | 2013-06-19 | 2016-03-02 | 张家港凯思半导体有限公司 | A kind of valley gutter Superpotential barrier rectification device and manufacture method thereof |
| CN103400840B (en) * | 2013-07-01 | 2016-01-27 | 中航（重庆）微电子有限公司 | A kind of super barrier rectifier and preparation method thereof |
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| CN106098686B (en) * | 2016-07-11 | 2019-05-21 | 华润微电子（重庆）有限公司 | A kind of super barrier rectifier and preparation method thereof |
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| CN106684127A (en) * | 2016-12-26 | 2017-05-17 | 东莞市联洲知识产权运营管理有限公司 | Super barrier rectifier and production method thereof |
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| CN108767000B (en) * | 2018-08-16 | 2024-04-09 | 无锡新洁能股份有限公司 | Insulated gate bipolar semiconductor device and manufacturing method thereof |
| CN109585572A (en) * | 2018-12-29 | 2019-04-05 | 矽力杰半导体技术(杭州)有限公司 | Semiconductor devices and its manufacturing method |
| CN111834437B (en) * | 2019-04-17 | 2021-05-07 | 南京芯舟科技有限公司 | Cellular structure and semiconductor assembly using same |
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| US6580141B2 (en) * | 2001-06-01 | 2003-06-17 | General Semiconductor, Inc. | Trench schottky rectifier |
| US6621107B2 (en) * | 2001-08-23 | 2003-09-16 | General Semiconductor, Inc. | Trench DMOS transistor with embedded trench schottky rectifier |
| US7453119B2 (en) * | 2005-02-11 | 2008-11-18 | Alphs & Omega Semiconductor, Ltd. | Shielded gate trench (SGT) MOSFET cells implemented with a schottky source contact |
| US7285822B2 (en) * | 2005-02-11 | 2007-10-23 | Alpha & Omega Semiconductor, Inc. | Power MOS device |
| CN201829501U (en) * | 2010-03-17 | 2011-05-11 | 无锡新洁能功率半导体有限公司 | Super potential barrier semiconductor rectifying device |
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