CN109585572A - Semiconductor devices and its manufacturing method - Google Patents
Semiconductor devices and its manufacturing method Download PDFInfo
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- CN109585572A CN109585572A CN201811637754.2A CN201811637754A CN109585572A CN 109585572 A CN109585572 A CN 109585572A CN 201811637754 A CN201811637754 A CN 201811637754A CN 109585572 A CN109585572 A CN 109585572A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 368
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 116
- 239000002184 metal Substances 0.000 claims abstract description 75
- 229910052751 metal Inorganic materials 0.000 claims abstract description 75
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 28
- 229920005591 polysilicon Polymers 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 16
- 230000004888 barrier function Effects 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 15
- 239000011159 matrix material Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 7
- 239000002019 doping agent Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000007423 decrease Effects 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 230000005684 electric field Effects 0.000 description 10
- 230000001965 increasing effect Effects 0.000 description 8
- 238000009826 distribution Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000005036 potential barrier Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 150000001875 compounds Chemical group 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Embodiment according to the present invention discloses a kind of semiconductor devices and its manufacturing method, including semiconductor substrate, the first metal layer of the upper surface of semiconductor substrate is covered, using the first electrode as semiconductor devices；The second metal layer for covering the lower surface of semiconductor substrate, using the second electrode as semiconductor devices；And structure is exhausted in the semiconductor substrate；The structure that exhausts is not as the electrode of semiconductor devices.Semiconductor devices increases the doping concentration of semiconductor substrate to reduce pressure drop when forward conduction between the first metal layer and second metal layer；And guarantee that the reverse withstand voltage between the second metal layer and the first metal layer requires.
Description
Technical field
The present invention relates to technical field of semiconductors, relate more specifically to a kind of semiconductor devices and its manufacturing method.
Background technique
Barrier diode is that the metal-semiconductor junction principle formed using metal and semiconductor contact is fabricated.It passes
The barrier diode of system usually deposits upper metal layer by the N- epitaxially grown layer top surface of low doping concentration and forms barrier contact, constitutes
The anode of barrier diode；Bottom surface and lower metal layer form Ohmic contact, constitute the cathode of barrier diode.Metal and N-type list
The work function difference of crystal silicon forms potential barrier, and the height of the potential barrier determines that the characteristic of barrier diode, lower potential barrier can reduce
Forward conduction cut-in voltage, but reverse leakage current can be made to increase, reverse BV reduces；Conversely, higher potential barrier can increase
Big forward conduction cut-in voltage, while reduce reverse leakage, reverse blocking capability enhancing.But compared with PN junction diode,
Barrier diode still has that reverse leakage current is bigger than normal, the low problem of reverse BV.
Summary of the invention
In view of this, according to an embodiment of the present invention, a kind of semiconductor devices and its manufacturing method are provided, passes through and introduces one
It is longitudinal exhaust structure make semiconductor devices reduced forward conduction voltage simultaneously, do not sacrifice the property of breakdown reverse voltage
Energy.
According to a first aspect of the embodiments of the present invention, a kind of semiconductor devices is provided, comprising: semiconductor substrate；Covering institute
The first metal layer for stating the upper surface of semiconductor substrate, using the first electrode as the semiconductor devices；It covers and described partly leads
The second metal layer of the lower surface of body matrix, using the second electrode as the semiconductor devices；Positioned at the semiconductor substrate
In exhaust structure；The structure that exhausts is not as the electrode of the semiconductor devices；Increase the doping of the semiconductor substrate
Concentration is to reduce pressure drop when forward conduction between the first metal layer and the second metal layer；And when described second
Between metal layer and the first metal layer apply backward voltage when, by it is described exhaust it is semiconductor-based described in structure assisted depletion
Body, to guarantee the requirement of the reverse withstand voltage between the second electrode and the first electrode.
Preferably, the concentration of structure and/or shape are exhausted described in setting makes its non-uniform structure.
Preferably, the structure that exhausts is made of conductive material.
Preferably, the structure that exhausts is contacted with the first metal layer.
Preferably, it is described exhaust structure extended to by the interface of the first metal layer and the semiconductor substrate it is described
The inside of semiconductor substrate, and end to the inside of the semiconductor substrate.
Preferably, the structure that exhausts is configured as groove structure, comprising: positioned at the bottom and inside of the groove structure
Insulating layer on wall surface；And the conductive semiconductor layer on the surface of the insulating layer.
Preferably, close to the first metal layer and the semiconductor substrate interface the conductive semiconductor layer
Concentration is greater than the concentration of the conductive semiconductor layer of the interface far from the first metal layer and the semiconductor substrate.
Preferably, close to the first metal layer and the semiconductor substrate interface the conductive semiconductor layer
Width is greater than the width of the conductive semiconductor layer of the interface far from the first metal layer and the semiconductor substrate.
Preferably, the width of the conductive semiconductor layer from top to bottom successively decreases.
Preferably, the insulating layer is oxide skin(coating).
Preferably, the conductive semiconductor layer is polysilicon layer.
Preferably, further includes: extended to and described partly led by the interface of the first metal layer and the semiconductor substrate
The inside of body matrix, and end to the first semiconductor region of the inside of the semiconductor substrate；First semiconductor region and institute
State exhaust structure lateral wall it is adjacent；And it is extended to by the interface of the first metal layer and the semiconductor substrate described
The inside of first semiconductor region, and end to the second semiconductor region of the inside of first semiconductor region.
Preferably, the semiconductor devices further include: the first half on two adjacent the first semiconductor regions lead
Body layer；And the second semiconductor layer positioned at first semiconductor layer；First semiconductor layer, described the second half lead
Body layer, first semiconductor region and second semiconductor region form a kind of MOS channel structure.
Preferably, the first metal layer covers first semiconductor layer, second semiconductor layer, and described the first half
Conductor region, second semiconductor region and described exhausts structure.
Preferably, the semiconductor substrate includes the semiconductor layer and partly lead positioned at what the N-type was lightly doped that N-type is lightly doped
The semiconductor layer of the N-type heavy doping of the lower surface of body layer, the second metal layer are located at the semiconductor layer of the N-type heavy doping
Lower surface；The structure that exhausts is located in the semiconductor layer that the N-type is lightly doped.
According to a second aspect of the embodiments of the present invention, a kind of manufacturing method of barrier semiconductor device is provided, comprising: formed
Semiconductor matrix；The specified region of the semiconductor substrate is etched, groove is formed；Depositing insulating layer in the groove, with
Cover bottom and the inner sidewall of the groove；Conductive semiconductor layer is deposited in the groove, and fills the full groove, with shape
At exhausting structure；Electrode of the conductive semiconductor layer not as the semiconductor devices；Deposition the first metal layer is described to cover
The upper surface of semiconductor substrate and the groove, as first electrode；Depositing second metal layer is to cover the semiconductor substrate
Lower surface, as second electrode.
Preferably, further includes: in the upper surface deposited oxide layer of the semiconductor substrate；Pattern the oxide layer；With
The oxide layer after patterning is mask, the semiconductor substrate is etched, to form the groove.
Preferably, the forming method for exhausting structure, comprising: upper surface and the groove in the semiconductor substrate
Interior depositing insulating layer, to cover the upper surface of the semiconductor substrate and bottom and the inner sidewall of the groove；Deposition first
Polysilicon layer, to cover a part of the bottom of the groove and the inner sidewall of the groove.
Preferably, further includes: etch the residue positioned at the upper surface of the semiconductor substrate and the inner sidewall of the groove
Partial insulating layer, with the thickness for the insulating layer being thinned on the remaining inner sidewall of the groove；Continue to deposit the polycrystalline
Silicon layer, to continue to fill up the groove.
Preferably, further includes: in the inner sidewall for the groove not covered by polysilicon layer, repeat in claim 20
Processing step, until polysilicon layer fills the full groove.
Preferably, further includes: deposition gate oxide, with cover the semiconductor substrate upper surface and the groove it is upper
Surface；Patterned second polysilicon layer is formed in the upper surface of the gate oxide.
Preferably, further includes: in the semiconductor-based internal injecting p-type dopant, form P-doped zone, the p-type is mixed
Miscellaneous area extends to inside the semiconductor substrate from the upper surface of the semiconductor substrate, and first side exhausts structure with described
Lateral wall it is adjacent, second side extends to the lower section of second polysilicon layer；N-type doping is injected in the P-doped zone
Agent, forms N-doped zone, and the N-type is extended to the inside of the P-doped zone by the upper surface of the semiconductor substrate.
Preferably, further includes: etching is exposed to the gate oxide of the upper surface of the semiconductor substrate, with exposed institute
State P-doped zone and the N-doped zone；The first metal layer covers second polysilicon layer, the P-doped zone, N
The upper surface of type doped region and the groove.
Preferably, the forming method of the semiconductor substrate, comprising: the semiconductor layer of N-type heavy doping is provided；In the N
The semiconductor layer that the upper surface growth N-type of the semiconductor layer of type heavy doping is lightly doped；The N-type heavy doping is thinned from the bottom to top
The lower surface of semiconductor layer, and deposited metal layer on it, to form the second metal layer.
Semiconductor devices and its manufacturing method according to an embodiment of the present invention:
In a first aspect, the semiconductor devices in compared with the existing technology, the concentration of semiconductor substrate can be accordingly increased,
Its resistivity is reduced, to reduce the pressure drop between the first electrode and second electrode of the semiconductor devices forward conduction, is mentioned
High efficiency；
Second aspect, it is increased to be located at semiconductor when applying backward voltage although the concentration of semiconductor substrate increases
Exhausting structure and can will not sacrifice the breakdown reverse voltage of semiconductor devices with the concentration of assisted depletion semiconductor substrate in matrix
Performance will not reduce so that improving the breakdown reverse voltage of barrier semiconductor device, be allowed to can be applied to the occasion of more high voltage；
The third aspect, the shape and position for exhausting structure can be flexibly controllable, come control exhaust structure constituent it is dense
Degree distribution, more optimizes the distribution of electric field, improves performance.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, the above and other purposes of the present invention, feature and
Advantage will be apparent from, in the accompanying drawings:
Fig. 1 show the diagrammatic cross-section of the semiconductor devices of first embodiment according to the present invention；
Fig. 2 show the diagrammatic cross-section of the semiconductor devices of second embodiment according to the present invention；
Fig. 3 show the process flow chart of the manufacturing method of the semiconductor devices of an embodiment according to the present invention；
Fig. 4 A- Fig. 4 K show the manufacturing method of the semiconductor devices of another embodiment according to the present invention in each step
The diagrammatic cross-section of the semiconductor structure of formation.
Specific embodiment
Below based on embodiment, present invention is described, but the present invention is not restricted to these embodiments.Under
Text is detailed to describe some specific detail sections in datail description of the invention.Do not have for a person skilled in the art
The present invention can also be understood completely in the description of these detail sections.
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached
Icon is remembered to indicate.In addition, it should be understood by one skilled in the art that attached drawing is provided to the mesh of explanation provided herein
, and attached drawing is not necessarily drawn to scale.Furthermore, it is possible to which certain well known parts are not shown.For brevity, may be used
To describe the semiconductor structure obtained after several steps in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
Many specific details of the invention, such as structure, material, size, the processing work of device is described hereinafter
Skill and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not be according to this
Some specific details realize the present invention.
With reference to Fig. 1, it show the schematic diagram of the section structure of the semiconductor devices of an embodiment according to the present invention.
According to the semiconductor devices 100 of the embodiment, including consisting of part:
Semiconductor substrate, doping type are the first doping type, for example, N-type；
The first metal layer 7 for covering the upper surface of the semiconductor substrate, using the first electrode as the semiconductor devices；
The second metal layer 8 for covering the lower surface of the semiconductor substrate, using the second electrode as the semiconductor devices；
Structure 2 is exhausted inside semiconductor substrate；
Exhausting structure 2 can be in extend to inside semiconductor substrate from the interface of the first metal layer 7 and semiconductor substrate
Groove shape；
Exhausting structure 2 includes the insulating layer 21 on channel bottom and interior side-wall surface and filling out on insulating layer 21
Semiconductor layer 22 full of groove.Here, semiconductor layer 22 can be made of conductive semiconductor or metal material, such as this
It is polysilicon in embodiment, also, semiconductor layer 22 is used not as the electrode of semiconductor devices.
Wherein, semiconductor substrate can be compound structure, such as may include semiconductor layer 1 and N-type that N-type is lightly doped
The semiconductor layer (being not drawn into figure) of heavy doping.The first metal layer 7 is located at the upper surface for the semiconductor layer that the N-type is lightly doped, consumption
Most structure 2 is located at the inside for the semiconductor layer that the N-type is lightly doped, and the semiconductor layer that N-type is lightly doped is located at the half of the N-type heavy doping
The upper surface of conductor layer, second metal layer 8 are located at the lower surface of the semiconductor layer of the N-type heavy doping.Wherein, the N-type is heavily doped
Miscellaneous semiconductor layer is semiconductor substrate, and the semiconductor layer 1 that the N-type is lightly doped is N-type lightly doped epitaxial layer.
According to the semiconductor devices of the embodiment, due to increasing in semiconductor substrate (i.e. N-type be lightly doped semiconductor layer 1)
Add and exhausted structure 2, therefore the concentration of semiconductor layer 1 that N-type is lightly doped can be increase accordingly, to reduce resistivity, has come
The pressure drop of first electrode and second electrode (between anode and cathode) when reduction by 100 forward conduction of semiconductor devices, improves effect
Rate.
On the other hand, increased when applying backward voltage although the concentration for the semiconductor layer 1 that N-type is lightly doped increases
The structure 2 that exhausts in the semiconductor layer 1 that N-type is lightly doped can be with the current-carrying for the semiconductor layer 1 that assisted depletion N-type is lightly doped
Son is allowed to can be applied to the occasion of more high voltage because of the breakdown reverse voltage without reducing semiconductor devices 100.
Further, semiconductor devices 100 can also include:
Semiconductor region 5 positioned at the inside of semiconductor substrate 1, doping type is different from semiconductor substrate, such as can be with
For p-type doping.Semiconductor region 5 extends to inside semiconductor substrate 1 from the interface of semiconductor substrate 1 and the first metal layer 7, and
It is adjacent with the lateral wall for exhausting structure 2.
Semiconductor region 6 inside semiconductor region 5, doping type is different from semiconductor region 5, such as can be N-type
Doping.Semiconductor region 6 extends to inside semiconductor region 5 from the interface of semiconductor substrate 1 and the first metal layer 7.
Patterned semiconductor layer 3 on the upper surface of semiconductor substrate 1, and the upper table positioned at semiconductor layer 3
Patterned semiconductor layer 4 on face.
Semiconductor layer 3 can be located at the top for adjacent two semiconductor region 5 not being in contact with certain intervals, with
And the top positioned at part semiconductor area 6.
Here, the semiconductor devices 100 of the present embodiment is super barrier diode, and semiconductor layer 3 can be set to gate oxidation
Layer, semiconductor layer 4 can be set to polysilicon layer, and semiconductor region 5 can be set to the area PXing Ti, and semiconductor region 6 can be set to
N-type heavily doped region N+, wherein semiconductor layer 4 is grid, and semiconductor region 6 is source/drain, and grid and semiconductor region 6 are shorted, with
First electrode connection, the second electrode at the back side are drain source.Its working principle is that being more son creation one super by MOS channel
Potential barrier, while reducing barrier height, the further forward voltage drop for reducing diode using the bulk effect of MOS, at the same guarantee compared with
Small leakage current further to reduce reverse leakage.
When adding reverse bias between the first electrode and the second electrode, there are potential differences between cathode and anode, by body
The PN junction that the semiconductor layer 1 that area 5 and N-type are lightly doped is constituted starts to exhaust, because the doping concentration in body area 5 is gently mixed much larger than N-type
The doping concentration of miscellaneous semiconductor layer 1, the semiconductor layer 1 that reverse-biased depletion layer is mainly lightly doped to N-type extend.At this point, exhausting knot
The semiconductor layer 1 that semiconductor layer 22 and N-type in structure are lightly doped is also at reverse-biased, and exhausting structure also can further assist consuming
The semiconductor layer 1 that most N-type is lightly doped, thus even if increasing N-type is lightly doped half to obtain lower positive on state voltage
Conductor layer 1, exhaust the presence of structure also can the semiconductor layer 1 that is lightly doped of assisted depletion N-type so that depletion layer is lightly doped in N-type
Semiconductor layer 1 in extend it is wider, to ensure that the pressure resistance of semiconductor devices.
It is worth noting that, the setting for exhausting 21 thickness of insulating layer in structure 2 works as insulating layer there is also an optimal value
When 21 thickness increases, it can reduce and exhaust the semiconductor layer in structure 2 22 in the spike electric field of end, and then improve the resistance to of device
Pressure, but when thickness of insulating layer continues to increase, will affect the depletion action of semiconductor layer 22 again, therefore those skilled in the art can
Optimal value is chosen according to actual device architecture.
Can be for semiconductor layer 22 uniform perhaps uneven can be set by the number or doping shape of dopant
It sets.
According to a kind of implementation, the shape of semiconductor layer 22 can be the shape of uniform rule, for example, shown in Fig. 1
Embodiment in exhaust structure 2.The semiconductor layer 1 that semiconductor layer 22 is lightly doped by the first metal layer 7 and semiconductor substrate N-type
Interface extend downwardly, and end the inside for the semiconductor layer 1 being lightly doped to N-type.The width of semiconductor layer 22 is under upper
Keep uniformity.Thickness positioned at the insulating layer 21 of the inner sidewall and bottom of groove structure is also consistent.Such reality
Existing mode, the formation of groove structure and fill process can be relatively simple.If semiconductor layer 22 is polysilicon, also may be selected
Doped p-type impurity inside it, with exhausting for the semiconductor layer 1 that further assists N-type to be lightly doped, doping concentration is also possible to
Uniformly it is also possible to non-uniform.
According to another implementation, the shape of semiconductor layer 22 can be set to non-uniform shape, come preferably excellent
Change the distribution of electric field.For example, being located at the concentration and/or width of the concentration for exhausting the upper part of structure and/or width greater than lower part
Degree.More preferably, the concentration of semiconductor layer 22 and/or width are passed downwards by the boundary of the first metal layer 7 and semiconductor substrate 1
Subtract.
With reference to Fig. 2, it show the schematic diagram of the section structure of the semiconductor devices 200 of another embodiment according to the present invention.?
It in the embodiment, is repeated no more with the identical component part in semiconductor devices 100 shown in FIG. 1, the difference is that exhausting knot
The structure of structure 2 '.
It according to the embodiment, exhausts structure 2 ' and is extended downwardly by the interface of the first metal layer 7 and semiconductor substrate, and cut
The inside for the semiconductor layer being only lightly doped to N-type.Exhaust the insulation that structure 2 ' includes the inner sidewall and bottom positioned at groove structure
Layer 21 ' and the semiconductor layer 22 ' for being located on the surface of insulating layer 21 ' and filling full groove structure.
Width of the semiconductor layer 22 ' in the part close to the first metal layer 7 and the interface of semiconductor substrate 1 is big as a result,
Width in the part of the semiconductor layer 22 ' far from the first metal layer 7 and the interface of semiconductor substrate 1.More preferably, semiconductor
The width of layer 22 ' is successively successively decreased under upper by the interface of the first metal layer 7 and semiconductor substrate.
In the embodiment of fig. 2, semiconductor layer 22 ' includes positioned at the boundary close to the first metal layer 7 and semiconductor substrate
The width of the biggish first part 222 ' of the width in face and the interface for being located remotely from the first metal layer 7 and semiconductor substrate is smaller
Second part 221 '.
The thickness of insulating layer 21 ' also changes accordingly.Connect with the semiconductor layer 22 ' of the biggish first part 222 ' of width
212 ' the thickness of insulating layer of touching is smaller, the insulating layer being in contact with the semiconductor layer 22 ' of the lesser second part 221 ' of width
211 ' thickness are larger.
When between the first electrode and the second electrode plus when reverse bias, semiconductor layer structure that You Tiqu 5 and N-type are lightly doped
At PN junction start to exhaust, namely electric field is maximum at the PN junction being made of the semiconductor layer that body area 5 and N-type are lightly doped, far from PN
Electric field at knot is smaller.This implementation to be successively decreased by designing 22 ' width of semiconductor layer, increases close to the first metal layer
7 and semiconductor substrate interface at semiconductor layer 22 ' width, also just increase its semiconductor layer 1 that N-type is lightly doped
Assisted depletion so that the electric field at PN junction will not rise it is too fast, field distribution more evenly, and far from PN junction local electric field
It is smaller, assisted depletion is carried out by the lesser semiconductor layer 221 ' of width, to optimize the entire electric field in semiconductor substrate
Distribution so that semiconductor devices pressure resistance it is higher.Reduce semiconductor devices forward conduction when pressure drop while, will not
Sacrifice reverse withstand voltage performance.In addition, exhausting the length of the wider semiconductor layer 222 ' and relatively narrow semiconductor layer 221 ' in structure
There is also an optimal values for degree ratio, and the doping concentration etc. of the voltage class with device, the semiconductor layer that N-type is lightly doped has
It closes, those skilled in the art is needed to carry out simulation optimization in design.
Further, the portion of the interface of the close the first metal layer 7 and semiconductor substrate of also settable semiconductor layer 22 '
The concentration divided is greater than the concentration of the part of the semiconductor layer 22 ' of the interface far from the first metal layer 7 and semiconductor substrate 1, with
Preferably optimization electric field.
Illustrate the manufacturing method of the semiconductor devices below according to specific embodiment.
With reference to Fig. 3, it show the process flow chart of the manufacturing method of the semiconductor devices of an embodiment according to the present invention.
In this embodiment, the manufacturing method 300 of barrier semiconductor device at least includes the following steps:
S31: semiconductor matrix is formed；
S32: etching the specified region of the semiconductor substrate, forms groove；
S33: depositing insulating layer in the groove, to cover bottom and the inner sidewall of the groove；
S34: deposited semiconductor layer in the groove, and the full groove is filled, structure is exhausted to be formed；
Here, the semiconductor layer is conductive layer, and the semiconductor layer is not as the electrode of the semiconductor devices；
S35: the first metal layer is deposited to cover the upper surface of the semiconductor substrate and the groove, as the first electricity
Pole；
S36: depositing second metal layer is to cover the lower surface of the semiconductor substrate, as second electrode.
Here, before depositing second metal layer, technique that the thickness of the lower surface of thinned semiconductor substrate can be increased
Step, the depositing second metal layer on it again after the thickness that semiconductor substrate is thinned.
The barrier semiconductor device formed as a result, according to the manufacturing method, exhausts due to increasing in semiconductor substrate
Structure, therefore the concentration of semiconductor substrate appropriate can increase, so that resistivity is reduced, to reduce semiconductor devices forward direction
The pressure drop of first electrode and second electrode (between anode and cathode) when conducting, improves efficiency.
On the other hand, increased to be located at semiconductor when applying backward voltage although the concentration of semiconductor substrate increases
In matrix exhaust structure can with assisted depletion semiconductor substrate, will not reduce even improve barrier semiconductor device reversely hit
Voltage is worn, is allowed to can be applied to the occasion of more high voltage.
With reference to each processing step that Fig. 4 A to 4K is according to the manufacturing method of the semiconductor devices of another embodiment of the present invention
Formation semiconductor structure sectional view.It is appreciated that semiconductor structure shown in each sectional view can be for by more than
The semiconductor structure formed after one processing step.
In the step shown in Fig. 4 A, it is initially formed semiconductor matrix, and in the upper surface deposited oxide of semiconductor substrate
Layer is used as mask, and the specified region for etching and patterning the oxide layer with bare semiconductor matrix, then etching forms groove 42.
Wherein, the semiconductor substrate includes semiconductor substrate (being not drawn into figure) and is lightly doped half in the semiconductor substrate
Conductor layer 41, the semiconductor layer 41 that is lightly doped is the second doping type, such as N-type or p-type；Then the first doping type is, for example,
P-type or N-type.In this implementation, the first doping type selects p-type.
In the step shown in Fig. 4 B, the depositing insulating layer 43 in the upper surface and groove 42 that semiconductor layer 41 is lightly doped,
To cover upper surface and bottom and the inner sidewall of groove 42 that semiconductor layer 41 is lightly doped.Here, insulating layer 43 can be two
Silicon oxide layer.
In the step shown in Fig. 4 C, the first polysilicon layer 44 is filled in groove 42 and is returned and is carved, with covering groove 42
The insulating layer of the upper surface of semiconductor layer 41 is lightly doped in the lower half inner sidewall and partial etching of bottom and groove 42.Wherein,
Electrode of the polysilicon layer 44 not as the semiconductor devices.
In the step shown in Fig. 4 D, isotropic etching technique continues to etch the upper surface that semiconductor layer 41 is lightly doped
The exhausted of the upper surface of semiconductor layer 41 is lightly doped with all removals in insulating layer on the inner sidewall of insulating layer and exposed groove 42
Edge layer, and the insulating layer of the inner sidewall upper portion of exposed groove 42 is thinned.
In the step shown in Fig. 4 E, the first polysilicon layer 44 is continued to fill up in groove 42 and is returned and is carved, to fill full ditch
Slot 42.
Here, the step of Fig. 4 D and 4E can be repeated as many times, and the width of the first polysilicon layer 44 is made to successively decrease from the bottom to top,
In order to preferably optimize semiconductor devices electric field distribution.
In the step shown in Fig. 4 F, gate oxide 45 is deposited, to cover upper surface and the groove 42 of semiconductor substrate
Upper surface；And patterned second polysilicon layer 46 is formed in the upper surface of gate oxide 45.
In the step shown in Fig. 4 G, injecting p-type dopant, 42 side wall along groove, in semiconductor substrate 41
Form P-doped zone 47；P-doped zone 47 extends to the inside of semiconductor substrate 41 from the upper surface of semiconductor substrate 41, the
One side extends to the lower section of the second polysilicon layer 46, and second side is adjacent with the lateral wall of groove 42.
In the step shown in Fig. 4 H, N type dopant is injected in P-doped zone 47 and forms N-doped zone 48.N-type is mixed
Miscellaneous area 47 extends to the inside of semiconductor substrate 41 from the upper surface of semiconductor substrate 41, and first side extends to the second polysilicon
The lower section of layer 46, second side and the lateral wall of groove 42 are non-conterminous.
In the step shown in Fig. 4 I, the gate oxide 45 not covered by the second polysilicon layer 46 is removed, is mixed with exposed p-type
Miscellaneous area 47 and N-doped zone 48.
In the step shown in Fig. 4 J, the first metal layer 49 is deposited, to cover the second polysilicon layer 46, the p-type doping
Area 47, N-doped zone 48 and groove 42, using the anode as semiconductor devices.
In the step shown in Fig. 4 K, from bottom to up be thinned semiconductor substrate 41 thickness namely thinned semiconductor substrate
Thickness, and the depositing second metal layer 50 on the lower surface of semiconductor substrate, using the cathode as semiconductor devices.
Here, semiconductor substrate 1 can be the semiconductor layer or be compound structure that single N-type is lightly doped.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
As described above according to the embodiment of the present invention, these embodiments details all there is no detailed descriptionthe is also unlimited
Making the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This specification
These embodiments are chosen and specifically described, are principle and practical applications in order to better explain the present invention, to make affiliated skill
Art field technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention is only wanted by right
Ask the limitation of book and its full scope and equivalent.
Claims (24)
1. a kind of semiconductor devices, comprising:
Semiconductor substrate；
The first metal layer for covering the upper surface of the semiconductor substrate, using the first electrode as the semiconductor devices；
The second metal layer for covering the lower surface of the semiconductor substrate, using the second electrode as the semiconductor devices；
Structure is exhausted in the semiconductor substrate；The structure that exhausts is not as the electrode of the semiconductor devices；
It is positive between the first metal layer and the second metal layer to reduce to increase the doping concentration of the semiconductor substrate
Pressure drop when conducting；And
When applying backward voltage between the second metal layer and the first metal layer, structure auxiliary is exhausted by described
The semiconductor substrate is exhausted, to guarantee the requirement of the reverse withstand voltage between the second electrode and the first electrode.
2. semiconductor devices according to claim 1, which is characterized in that exhaust the concentration and/or shape of structure described in setting
Shape makes its non-uniform structure.
3. semiconductor devices according to claim 1, which is characterized in that the structure that exhausts is made of conductive material.
4. semiconductor devices according to claim 1, which is characterized in that the structure that exhausts connects with the first metal layer
Touching.
5. semiconductor devices according to claim 1, which is characterized in that it is described exhaust structure by the first metal layer and
The interface of the semiconductor substrate extends to the inside of the semiconductor substrate, and ends to the semiconductor substrate
Portion.
6. semiconductor devices according to claim 1, which is characterized in that the structure that exhausts is configured as groove structure,
Include:
Insulating layer on the bottom and interior side-wall surface of the groove structure；And
Conductive semiconductor layer on the surface of the insulating layer.
7. semiconductor devices according to claim 6, which is characterized in that close to the first metal layer and the semiconductor
The concentration of the conductive semiconductor layer of the interface of matrix is greater than far from the first metal layer and the semiconductor substrate
The concentration of the conductive semiconductor layer of interface.
8. semiconductor devices according to claim 6, which is characterized in that close to the first metal layer and the semiconductor
The width of the conductive semiconductor layer of the interface of matrix is greater than far from the first metal layer and the semiconductor substrate
The width of the conductive semiconductor layer of interface.
9. semiconductor devices according to claim 8, which is characterized in that the width of the conductive semiconductor layer is from top to bottom
Successively decrease.
10. semiconductor devices according to claim 6, which is characterized in that the insulating layer is oxide skin(coating).
11. semiconductor devices according to claim 6, which is characterized in that the conductive semiconductor layer is polysilicon layer.
12. semiconductor devices according to claim 1, which is characterized in that further include:
The inside of the semiconductor substrate is extended to by the interface of the first metal layer and the semiconductor substrate, and is ended
To the first semiconductor region of the inside of the semiconductor substrate；
First semiconductor region is adjacent with the lateral wall for exhausting structure；And
The inside of first semiconductor region is extended to by the interface of the first metal layer and the semiconductor substrate, and is cut
Only to the second semiconductor region of the inside of first semiconductor region.
13. semiconductor devices according to claim 12, which is characterized in that further include:
The first semiconductor layer on two adjacent the first semiconductor regions；And
Positioned at the second semiconductor layer of first semiconductor layer；
First semiconductor layer, second semiconductor layer, first semiconductor region and second semiconductor region are formed
A kind of MOS channel structure.
14. semiconductor devices according to claim 13, which is characterized in that the first metal layer covering described the first half
Conductor layer, second semiconductor layer, first semiconductor region and described exhaust structure at second semiconductor region.
15. semiconductor devices according to claim 1, which is characterized in that the semiconductor substrate includes what N-type was lightly doped
The semiconductor layer of the N-type heavy doping of the lower surface of semiconductor layer and the semiconductor layer being lightly doped positioned at the N-type, second gold medal
Belong to the lower surface that layer is located at the semiconductor layer of the N-type heavy doping；The structure that exhausts is located at the semiconductor that the N-type is lightly doped
In layer.
16. a kind of manufacturing method of barrier semiconductor device, comprising:
Form semiconductor matrix；
The specified region of the semiconductor substrate is etched, groove is formed；
Depositing insulating layer in the groove, to cover bottom and the inner sidewall of the groove；
Conductive semiconductor layer is deposited in the groove, and fills the full groove, exhausts structure to be formed；The conduction is partly led
Electrode of the body layer not as the semiconductor devices；
The first metal layer is deposited to cover the upper surface of the semiconductor substrate and the groove, as first electrode；
Depositing second metal layer is to cover the lower surface of the semiconductor substrate, as second electrode.
17. the manufacturing method of semiconductor devices according to claim 16, which is characterized in that further include:
In the upper surface deposited oxide layer of the semiconductor substrate；
Pattern the oxide layer；
Using the oxide layer after patterning as mask, the semiconductor substrate is etched, to form the groove.
18. the manufacturing method of semiconductor devices according to claim 16, which is characterized in that the formation for exhausting structure
Method, comprising:
The depositing insulating layer in the upper surface of the semiconductor substrate and the groove, to cover the upper table of the semiconductor substrate
The bottom and inner sidewall of face and the groove；
The first polysilicon layer is deposited, to cover a part of the bottom of the groove and the inner sidewall of the groove.
19. the manufacturing method of semiconductor devices according to claim 18, which is characterized in that further include:
Etching is located at the insulating layer of the remainder of the upper surface of the semiconductor substrate and the inner sidewall of the groove, to be thinned
The thickness of insulating layer on the remaining inner sidewall of the groove；
Continue to deposit the polysilicon layer, to continue to fill up the groove.
20. the manufacturing method of semiconductor devices according to claim 19, which is characterized in that further include:
In the inner sidewall for the groove not covered by polysilicon layer, the processing step in claim 20 is repeated, until polycrystalline
Silicon layer fills the full groove.
21. the manufacturing method of semiconductor devices according to claim 18, which is characterized in that further include:
Gate oxide is deposited, to cover the upper surface of the semiconductor substrate and the upper surface of the groove；
Patterned second polysilicon layer is formed in the upper surface of the gate oxide.
22. the manufacturing method of semiconductor devices according to claim 21, which is characterized in that further include:
In the semiconductor-based internal injecting p-type dopant, P-doped zone is formed, the P-doped zone is from described semiconductor-based
The upper surface of body extends to inside the semiconductor substrate, and first side is adjacent with the lateral wall for exhausting structure, and second
Side extends to the lower section of second polysilicon layer；
The P-doped zone inject N type dopant, formed N-doped zone, the N-type by the semiconductor substrate upper table
Face extends to the inside of the P-doped zone.
23. the manufacturing method of semiconductor devices according to claim 21, which is characterized in that further include:
Etching is exposed to the gate oxide of the upper surface of the semiconductor substrate, with the exposed P-doped zone and the N
Type doped region；
The first metal layer covers second polysilicon layer, the P-doped zone, N-doped zone and the groove it is upper
Surface.
24. the manufacturing method of semiconductor devices according to claim 16, which is characterized in that the shape of the semiconductor substrate
At method, comprising:
The semiconductor layer of N-type heavy doping is provided；
In the semiconductor layer that the upper surface growth N-type of the semiconductor layer of the N-type heavy doping is lightly doped；
The lower surface of the semiconductor layer of the N-type heavy doping, and deposited metal layer on it are thinned from the bottom to top, described in being formed
Second metal layer.
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