CN109427909A - Semiconductor element and its manufacturing method - Google Patents
Semiconductor element and its manufacturing method Download PDFInfo
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- CN109427909A CN109427909A CN201710741887.3A CN201710741887A CN109427909A CN 109427909 A CN109427909 A CN 109427909A CN 201710741887 A CN201710741887 A CN 201710741887A CN 109427909 A CN109427909 A CN 109427909A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 230000002262 irrigation Effects 0.000 claims abstract description 36
- 238000003973 irrigation Methods 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical group CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 5
- 239000011159 matrix material Substances 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000000034 method Methods 0.000 description 31
- 229910052751 metal Inorganic materials 0.000 description 14
- 239000002184 metal Substances 0.000 description 14
- 238000012545 processing Methods 0.000 description 11
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000004070 electrodeposition Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000004575 stone Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical compound [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
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Abstract
A kind of semiconductor element and its manufacturing method.Semiconductor element includes substrate, epitaxial layer, third dielectric layer, shielded layer, the 4th dielectric layer, grid, multiple doped regions and the 5th dielectric layer.Epitaxial layer is located on substrate.Third dielectric layer is set in the first irrigation canals and ditches of epitaxial layer, and forms the second irrigation canals and ditches in the first irrigation canals and ditches.Shielded layer has top half and lower half portion, and wherein lower half portion is set in the second irrigation canals and ditches, and top half protrudes from third dielectric layer.Grid be set in epitaxial layer on third dielectric layer, wherein the 4th dielectric layer is set between shielded layer and grid.Doped region is set in the epitaxial layer of the surrounding of grid.5th dielectric layer is set between doped region and grid.Semiconductor element because the dielectric layer being located at beside grid thinner thickness, in addition, the enough thickness of the thickness of square dielectric layer under the gate, so semiconductor element is allow to carry higher revers voltage while with low conducting voltage.
Description
Technical field
The invention relates to a kind of semiconductor elements and its manufacturing method.
Background technique
Power semiconductor is still the main element of many power electronic systems.In the application field of power semiconductor now
In, the height of low conducting voltage and revers voltage multiplies loading capability and is very important capacity index.
In order to further improve every characteristic of power semiconductor, related fields is there's no one who doesn't or isn't painstakingly developed.How to mention
It is real to belong to one of current important research and development project for a kind of semiconductor with preferable characteristic, also become currently associated field and needs to change
Into target.
Summary of the invention
A technology aspect of the invention is to be set providing a kind of semiconductor element and its manufacturing method by structure appropriate
Meter makes semiconductor element have lower conducting voltage and can carry higher revers voltage.In addition, utilizing special processing procedure
Design, will be effectively reduced manufacturing cost.
According to an embodiment of the present invention, a kind of manufacturing method of semiconductor element comprises the steps of.Firstly, being formed of heap of stone
Crystal layer is on substrate.Then, the first irrigation canals and ditches are formed in epitaxial layer.Later, sequentially form the first dielectric layer, the second dielectric layer with
And third dielectric layer, on epitaxial layer, wherein third dielectric layer forms the second irrigation canals and ditches, and the second irrigation canals and ditches are located in the first irrigation canals and ditches.Again
Come, forms shielded layer in the second irrigation canals and ditches.Then, the top half for removing third dielectric layer, so that the top half of shielded layer
Protrude from third dielectric layer.Later, the 4th dielectric layer is formed in the top half of shielded layer.Come again, removes not by third dielectric
The second dielectric layer and the first dielectric layer of layer covering, with exposed epitaxial layer.Then, the 5th dielectric layer is formed.Later, grid is formed
In on third dielectric layer, and make the 5th dielectric layer between grid and epitaxial layer.Finally, forming multiple doped regions in grid
In the epitaxial layer of surrounding.
In one or more embodiments, the 4th dielectric layer is to be formed by thermal oxide shielded layer.
In one or more embodiments, the apical side height of shielded layer is lower than the apical side height of epitaxial layer.
In one or more embodiments, forming multiple doped regions includes forming the first doped region, positioned at the surrounding of grid
In epitaxial layer, with as matrix area, and the second doped region is formed, in the upper surface of the first doped region of surrounding for being located at grid portion
In point, as source area.
It further include forming groove in the second doped region after forming the second doped region in one or more embodiments, with
And according to groove location, third doped region is formed in the first doped region.
It further include forming third doped region in the first doped region after forming the second doped region in one or more embodiments
In, wherein the bottom depth of third doped region is greater than the bottom depth of the second doped region.
In one or more embodiments, the apical side height of the 4th dielectric layer is greater than or equal to the apical side height of epitaxial layer.
Another embodiment according to the present invention, a kind of semiconductor element include substrate, epitaxial layer, third dielectric layer, shielding
Layer, the 4th dielectric layer, grid, multiple doped regions and the 5th dielectric layer.Epitaxial layer is located on substrate.Third dielectric layer is set to
In first irrigation canals and ditches of epitaxial layer, and the second irrigation canals and ditches are formed in the first irrigation canals and ditches.Shielded layer has top half and lower half portion,
Middle lower half portion is set in the second irrigation canals and ditches, and top half protrudes from third dielectric layer.4th dielectric layer is set to top half
On.Grid be set in epitaxial layer on third dielectric layer, wherein the 4th dielectric layer is set between shielded layer and grid.Doping
Area is set in the epitaxial layer of the surrounding of grid.5th dielectric layer is set between doped region and grid.
In one or more embodiments, the apical side height of shielded layer is lower than the apical side height of epitaxial layer, at least partly grid
Positioned at the top of the top half of shielded layer.
In one or more embodiments, the material of third dielectric layer is tetraethoxysilane, and semiconductor element also includes the
One dielectric layer and the second dielectric layer.First dielectric layer is set between epitaxial layer and the first dielectric layer, wherein the first dielectric layer
Material be silica.Second dielectric layer is set between the first dielectric layer and third dielectric layer, the material of the second dielectric layer
For silicon nitride.
In one or more embodiments, doped region includes the first doped region and the second doped region.First doped region is located at grid
In the epitaxial layer of the surrounding of pole, with as matrix area, the second doped region is located at the upper surface of the first doped region of surrounding of grid portion
In point, as source area.
In one or more embodiments, semiconductor element further includes third doped region, is located in the first doped region, wherein the
Two doped regions have groove, and the position of third doped region corresponds to the position of groove.
In one or more embodiments, the bottom depth of third doped region is greater than the bottom depth of the second doped region.
In the semiconductor element, because of the short-channel effect that grid can produce, semiconductor element will be can produce
Similar to the low conducting voltage of Schottky diode.Then, the conducting loss of efficacy of semiconductor element will reduce, while can be with
Excellent reliability performance when with high temperature.Furthermore, it is understood that because of the thinner thickness for the dielectric layer being located at beside grid,
The conducting voltage of semiconductor element can further decrease.
This manufacturing method can be compatible to the related process of conventional power semiconductors element, therefore only need to finely tune original processing procedure
Semiconductor element can be manufactured.In addition, the thickness of square dielectric layer is enough thick under the gate, so making semiconductor element with low
Higher revers voltage can be carried while conducting voltage.
Furthermore, it is understood that in the way of thermal oxide shielded layer, it is only necessary to can be formed and be set to using a processing procedure
Dielectric layer between grid and shielded layer.Then, compared to conventional process, processing procedure needed for manufacturing semiconductor element will be substantially
It reduces, and then manufacturing cost is effectively reduced.
Detailed description of the invention
Figure 1A to Fig. 1 G is painted the section of each step of manufacturing method according to the semiconductor element of an embodiment of the present invention
Figure；
Fig. 2 is painted the sectional view of each step of manufacturing method of the semiconductor element according to another embodiment of the present invention；
Fig. 3 is painted the sectional view of each step of manufacturing method according to the semiconductor element of a further embodiment of this invention；
Fig. 4 A to Fig. 4 C is painted to be cutd open according to manufacturing method each step of the semiconductor element of a further embodiment of this invention
Face figure；
Fig. 5 is painted the sectional view of each step of manufacturing method according to the semiconductor element of a further embodiment of the present invention；
Fig. 6 is painted the sectional view of each step of manufacturing method according to the semiconductor element of a further embodiment of the present invention.
Specific embodiment
Multiple embodiments of the invention will be disclosed with attached drawing below, as clearly stated, the details in many practices
It will be explained in the following description.It should be appreciated, however, that the details in these practices is not applied to limit the present invention.Also
It is to say, in some embodiments of the present invention, the details in these practices is non-essential.In addition, for the sake of simplifying attached drawing, one
A little known usual structures will be painted in a manner of simply illustrating in the accompanying drawings with element.
Figure 1A to Fig. 1 G is painted cuing open for each step of manufacturing method of the semiconductor element 100 according to an embodiment of the present invention
Face figure.
As depicted in Figure 1A, firstly, forming epitaxial layer 120 on substrate 110.Specifically, the material of substrate 110 can be
Monocrystalline silicon.The material of epitaxial layer 120 can be monocrystalline silicon.
Then, the first irrigation canals and ditches 121 are formed in epitaxial layer 120.Specifically, the forming method of irrigation canals and ditches 121 is, for example, to lose
It carves.
Then, the first dielectric layer 131, the second dielectric layer 132, third dielectric layer 133 are sequentially formed on epitaxial layer 120,
Wherein third dielectric layer 133 forms the second irrigation canals and ditches 134, and the second irrigation canals and ditches 134 are located in the first irrigation canals and ditches 121.Specifically, first is situated between
The material of electric layer 131 can be silica.The material of second dielectric layer 132 can be silicon nitride.The material of third dielectric layer 133 can
For tetraethoxysilane (Tetraethoxysilane, TEOS).First dielectric layer 131 can pass through 120 shape of thermal oxide epitaxial layer
At.Second dielectric layer 132, third dielectric layer 133 can pass through physical vapour deposition (PVD), chemical vapor deposition or combinations thereof shape respectively
At.
As depicted in Figure 1B, shielded layer 140 is formed in the second irrigation canals and ditches 134.Specifically, being initially formed shielded layer 140
In on third dielectric layer 133 (on the top surface i.e. in irrigation canals and ditches 134 with dielectric layer 133).Then, partly shielding effect layer 140 is removed, is only stayed
The shielded layer 140 being located at down in the second irrigation canals and ditches 134.The material of shielded layer 140 can be polysilicon.Shielded layer 140 can pass through physics
Vapor deposition, chemical vapor deposition or combinations thereof and formed.The removing method of shielded layer 140 can be etching.In addition, shielded layer
Height of the height of 140 top surface lower than the top surface of epitaxial layer 120.
As depicted in Fig. 1 C, removes the top half of third dielectric layer 133 and leave the third in the first irrigation canals and ditches 121
Dielectric layer 133, so that the top half 140u of shielded layer 140 protrudes from third dielectric layer 133.Specifically, third dielectric layer
133 removing method can be wet etching.
As depicted in Fig. 1 D, the 4th dielectric layer 135 is formed on the top half 140u of shielded layer 140, thus makes the 4th
The top half 140u of the covering shielded layer 140 of dielectric layer 135.Specifically, the material of the 4th dielectric layer 135 can be titanium dioxide
Silicon.4th dielectric layer 135 is to be formed by thermal oxide shielded layer 140.Herein it should be noted that the second dielectric layer 132 can
To protect the other structures (such as first dielectric layer 131) being located under it unaffected when thermal oxide shielded layer 140.
As depicted in Fig. 1 D and Fig. 1 E, the top half for the second dielectric layer 132 not covered by third dielectric layer 133 is removed
(i.e. setting height be greater than the apical side height of third dielectric layer 133 part), so that the apical side height of the second dielectric layer 132 and the
The apical side height of three dielectric layers 133 is roughly the same.Specifically, the removing method of the second dielectric layer 132 can be wet etching.
Then, (it is big that height is arranged in the top half for removing the first dielectric layer 131 not covered by third dielectric layer 133
In the part of the setting height of the top surface of third dielectric layer 133) so that the apical side height of the first dielectric layer 131 and third dielectric
The apical side height of layer 133 is roughly the same, and the top half of exposed epitaxial layer 120.Specifically, the shifting of the first dielectric layer 131
Except method can be wet etching.
Come again, forms the 5th dielectric layer 137 above exposed epitaxial layer 120.Specifically, the 5th dielectric layer 137
Material can be silica.5th dielectric layer 137 can be formed by thermal oxide epitaxial layer 120.
Later, grid 150 is formed in irrigation canals and ditches 138 and on third dielectric layer 133, and makes the 5th dielectric layer 137 between grid
Between pole 150 and epitaxial layer 120.Specifically, being initially formed top surface of the grid 150 in irrigation canals and ditches 138 with third dielectric layer 133
On.Then, the top half for removing grid 150, only leaves the grid 150 in irrigation canals and ditches 138.Then, grid 150 is set to
First dielectric layer 131, the second dielectric layer 132 on third dielectric layer 133 and directly contact the 5th dielectric layer 137.Grid 150
Material can be polysilicon.Grid 150 can be formed by physical vapour deposition (PVD), chemical vapor deposition or combinations thereof.Grid 150
Removing method can be etching.
As depicted in Fig. 1 F, the first doped region 122 is formed in the epitaxial layer 120 for the surrounding for being located at grid 150 (irrigation canals and ditches 138)
In, as matrix area (Body).The forming method of first doped region 122 is ion implant (Ion Implantation) and drives
Enter diffusion (Drive In).
Then, the first doped region 122 for forming the second doped region 123 in the surrounding for being located at grid 150 (irrigation canals and ditches 138) is (of heap of stone
Crystal layer 120) the upper surface of in part, as source area (Source).Specifically, the forming method of the second doped region 123 is
Ion implant and drive in diffusion.
As depicted in Fig. 1 F and Fig. 1 G, groove 129 is formed in the second doped region 123.Specifically, the shape of groove 129
It can be etching at method.
Then, it according to 129 position of groove, carries out ion implant and drives in diffusion, to form third doped region 124 in being located at
In first doped region 122 (epitaxial layer 120) of the surrounding of grid 150 (irrigation canals and ditches 138).
Come again, remove the dielectric layer 137 being located on the top surface of the second doped region 123, and forms metal silicified layer 171 in the
On two doped regions 123, third doped region 124 and grid 150.Specifically, (can be moved by etching after removing dielectric layer 137
Except), metal layer is initially formed on the second doped region 123, third doped region 124 and grid 150.In some embodiments,
The material of metal layer can be titanium.The generation type of metal layer can for physical vapour deposition (PVD), chemical vapor deposition, or combinations thereof and shape
At.Then, temperature is promoted to proper temperature.Then, metal layer by be located at its under the second doped region 123, third doped region
124 and with grid 150 in conjunction with and form metal silicified layer 171.Metal silicified layer 171 is electrically connected the second doped region 123, third
Doped region 124 and grid 150.In some embodiments, the material of metal silicified layer 171 can be titanium silicide.
Finally, forming metal layer 172 on metal silicified layer 171.Specifically, the material of metal layer 172 can for aluminium or
Copper.Metal layer 172 can pass through electrochemical deposition processing procedure (Electrochemical Deposition), physical vapour deposition (PVD) system
Journey, chemical vapor deposition process or combinations thereof formation.
In the present embodiment, the first doped region 122 is P-type.Second doped region 123 is N+ type.Third doped region 124
For P+ type.It will be understood that the specific implementation of the first doped region 122 provided above, the second doped region 123 and third doped region 124
Mode is only to illustrate, and is not intended to limit the invention, persond having ordinary knowledge in the technical field of the present invention, should regard practical need
It wants, the specific embodiment of the first doped region 122 of elasticity selection, the second doped region 123 and third doped region 124.
In semiconductor element 100, because of short-channel effect (the Short Channel that grid 150 can produce
Effect), so semiconductor element 100 will can produce the low conducting voltage for being similar to Schottky diode.Then, semiconductor
The conducting loss of efficacy of element 100 will reduce, while can have reliability performance excellent when high temperature.Furthermore, it is understood that
Because being located at the thinner thickness of the dielectric layer 137 on 150 side of grid, the conducting voltage of semiconductor element 100 can be into one
Step reduces.
This manufacturing method can be compatible to the related process of conventional power semiconductors element, therefore only need to finely tune original processing procedure
Semiconductor element 100 can be manufactured.In addition, the first dielectric layer 131, the second dielectric layer 132, third below grid 150 are situated between
The enough thickness of the thickness of electric layer 133, so it is higher reverse to carry semiconductor element 100 while with low conducting voltage
Voltage.
Furthermore, it is understood that in the way of thermal oxide shielded layer 140, it is only necessary to setting can be formed using a processing procedure
The 4th dielectric layer 135 between grid 150 and shielded layer 140.Then, compared to conventional process, semiconductor element 100 is manufactured
Required processing procedure will be greatly decreased, and then manufacturing cost is effectively reduced.
Fig. 2 is painted the sectional view of each step of manufacturing method of the semiconductor element 100 according to another embodiment of the present invention.
As illustrated in Figure 2, the manufacturing method of present embodiment and the manufacturing method of aforementioned embodiments are roughly the same, it is main it is different
In, after forming second doped region 123, groove 129 is not formed as Fig. 1 G in the second doped region 123, but directly
Third doped region 124 is formed in the first doped region 122 and the second doped region 123, wherein the bottom depth of third doped region 124
Greater than the bottom depth of the second doped region 123.
Fig. 3 is painted the sectional view of each step of manufacturing method according to the semiconductor element 100 of a further embodiment of this invention.
To show as depicted in fig. 3, the manufacturing method of present embodiment is roughly the same with the manufacturing method of Fig. 1 G, and it is mainly different to be, in this reality
It applies in mode, does not form groove 129 and third doped region 124.In addition, the first doped region 122 is P-type.Second doped region
123 be P+ type.It will be understood that the specific embodiment of the first doped region 122 provided above and the second doped region 123 only for
Show, be not intended to limit the invention, persond having ordinary knowledge in the technical field of the present invention should regard actual needs, elasticity choosing
Select the specific embodiment of the first doped region 122 and the second doped region 123.
Fig. 4 A to Fig. 4 B is painted manufacturing method each step according to the semiconductor element 100 of a further embodiment of this invention
Sectional view.The manufacturing method of present embodiment and the manufacturing method of aforementioned embodiments are roughly the same, will mainly introduce it below
Deviation.
As depicted in Fig. 4 A, when removing partly shielding effect layer 140, make the top surface 140t's of the shielded layer 140 left
The setting height that height is approximately equal to the top surface 120t of epitaxial layer 120 is set.
As depicted in Fig. 4 B, when forming grid 150, because the setting height of the top surface of the 4th dielectric layer 135 is big
In or equal to epitaxial layer 120 top surface 120t setting height, so grid 150 will not be set to the upper half of shielded layer 140
The top of part 140u.In other words, grid 150 is not provided on the top surface of the 4th dielectric layer 135.
As depicted in Fig. 4 C, present embodiment, which is formed by semiconductor element 100 and is substantially formed by with Fig. 1 G, partly to be led
Volume elements part 100 is identical, and main difference is, in the present embodiment, the setting height of the top surface 140t of shielded layer 140 is approximately equal to
(the first doped region 122, the second doped region 123 and third doped region 124 are shape to the setting height of the top surface 120t of epitaxial layer 120
At in epitaxial layer 120), so grid 150 is not provided in the top of the top half 140u of shielded layer 140.Further come
It says, in preceding process, because the setting height of the top surface of the 4th dielectric layer 135 is greater than or equal to the top surface of epitaxial layer 120
The setting height of 120t, so the 4th dielectric layer 135 of part will protrude from epitaxial layer 120.Formed metal silicified layer 171 it
Before, the dielectric layer 135 that will protrude above epitaxial layer 120 removes, thus exposed shielded layer 140.Then, metal silicified layer 171 is also electric
Property connection shielded layer 140.Specifically, the method for removing the 4th dielectric layer 135 for protruding from epitaxial layer 120 can be chemical machinery
Planarization process (Chemical Mechanical Planarization, CMP).
Fig. 5 is painted the sectional view of each step of manufacturing method according to the semiconductor element 100 of a further embodiment of the present invention.
Show as shown graphically in fig 5, the manufacturing method of present embodiment is roughly the same with the manufacturing method of earlier figures 4A to Fig. 4 C embodiment, main
It wants different to be, after forming second doped region 123, does not form the directly formation third doped region 124 of groove 129 and mixed in first
In miscellaneous area 122 and the second doped region 123, wherein the bottom depth of third doped region 124 is greater than the bottom depth of the second doped region 123
Degree.
Fig. 6 is painted the sectional view of each step of manufacturing method according to the semiconductor element 100 of a further embodiment of the present invention.
As depicted in Fig. 6, the manufacturing method of present embodiment is roughly the same with the manufacturing method of Fig. 4 A to Fig. 4 C, mainly different to be,
In the present embodiment, groove 129 and third doped region 124 are not formed.In addition, the first doped region 122 is P-type.Second mixes
Miscellaneous area 123 is P+ type.It will be understood that the specific embodiment of the first doped region 122 provided above and the second doped region 123 is only
It illustrates, is not intended to limit the invention, persond having ordinary knowledge in the technical field of the present invention, actual needs should be regarded, elasticity
Select the specific embodiment of the first doped region 122 and the second doped region 123.
In the semiconductor element, because of the short-channel effect that grid can produce, semiconductor element will be can produce
Similar to the low conducting voltage of Schottky diode.Then, the conducting loss of efficacy of semiconductor element will reduce, while can be with
Excellent reliability performance when with high temperature.Furthermore, it is understood that because of the thinner thickness for the dielectric layer being located at beside grid,
The conducting voltage of semiconductor element can further decrease.
This manufacturing method can be compatible to the related process of conventional power semiconductors element, therefore only need to finely tune original processing procedure
Semiconductor element can be manufactured.In addition, the thickness of square dielectric layer is enough thick under the gate, so making semiconductor element with low
Higher revers voltage can be carried while conducting voltage.
Furthermore, it is understood that in the way of thermal oxide shielded layer, it is only necessary to can be formed and be set to using a processing procedure
Dielectric layer between grid and shielded layer.Then, compared to conventional process, processing procedure needed for manufacturing semiconductor element will be substantially
It reduces, and then manufacturing cost is effectively reduced.
Although the present invention is disclosed above with embodiment, however, it is not to limit the invention, any to be familiar with this skill
Person, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations, therefore protection scope of the present invention is worked as
Subject to the scope of which is defined in the appended claims.
Claims (15)
1. a kind of manufacturing method of semiconductor element, characterized by comprising:
An epitaxial layer is formed on a substrate；
One first irrigation canals and ditches are formed in the epitaxial layer；
One first dielectric layer, one second dielectric layer and a third dielectric layer are sequentially formed on the epitaxial layer, wherein the third
Dielectric layer forms one second irrigation canals and ditches, which is located in first irrigation canals and ditches；
A shielded layer is formed in second irrigation canals and ditches；
A top half of the third dielectric layer is removed, so that a top half of the shielded layer protrudes from the third dielectric layer；
One the 4th dielectric layer is formed in the top half of the shielded layer；
Second dielectric layer and first dielectric layer not covered by the third dielectric layer are removed, with the exposed epitaxial layer；
Form one the 5th dielectric layer；
A grid is formed on the third dielectric layer, and makes the 5th dielectric layer between the grid and the epitaxial layer；And
Multiple doped regions are formed in the epitaxial layer of the surrounding of the grid.
2. the manufacturing method of semiconductor element according to claim 1, which is characterized in that the 4th dielectric layer is to pass through heat
It aoxidizes the shielded layer and is formed.
3. the manufacturing method of semiconductor element according to claim 1, which is characterized in that the apical side height of the shielded layer is low
In the apical side height of the epitaxial layer.
4. the manufacturing method of semiconductor element according to claim 1, which is characterized in that form multiple doped region packet
It includes:
One first doped region is formed, in the epitaxial layer of surrounding for being located at the grid, as a matrix area；And
One second doped region is formed, in the upper surface of first doped region of surrounding for being located at grid part, as a source
Polar region.
5. the manufacturing method of semiconductor element according to claim 4, which is characterized in that after forming second doped region,
Further include:
A groove is formed in second doped region；And
According to the groove location, a third doped region is formed in first doped region.
6. the manufacturing method of semiconductor element according to claim 4, which is characterized in that after forming second doped region,
Further include:
A third doped region is formed in first doped region, wherein the bottom depth of the third doped region is greater than second doping
The bottom depth in area.
7. the manufacturing method of semiconductor element according to claim 1, which is characterized in that the top surface of the 4th dielectric layer is high
Degree is greater than or equal to the apical side height of the epitaxial layer.
8. a kind of semiconductor element, characterized by comprising:
One substrate；
One epitaxial layer is located on the substrate；
One third dielectric layer is set in one first irrigation canals and ditches of the epitaxial layer, and forms one second irrigation canals and ditches in first irrigation canals and ditches；
One shielded layer has a top half and a lower half portion, and wherein the lower half portion is set in second irrigation canals and ditches, on this
Half part protrudes from the third dielectric layer；
One the 4th dielectric layer；
One grid, be set in the epitaxial layer on the third dielectric layer, wherein the 4th dielectric layer be set to the shielded layer with
Between the grid；
Multiple doped regions are set in the epitaxial layer of the surrounding positioned at the grid；And
One the 5th dielectric layer, is set between the doped region and the grid.
9. semiconductor element according to claim 8, which is characterized in that the apical side height of the shielded layer is lower than the epitaxial layer
Apical side height, at least partly grid top that is located at the top half of the shielded layer.
10. semiconductor element according to claim 8, which is characterized in that the apical side height of the 4th dielectric layer be greater than or
Equal to the apical side height of the epitaxial layer.
11. semiconductor element according to claim 8, which is characterized in that the 4th dielectric layer passes through the thermal oxide shielding
Layer is formed.
12. semiconductor element according to claim 8, which is characterized in that also include:
The material of the third dielectric layer is tetraethoxysilane；
One first dielectric layer is set between the epitaxial layer and first dielectric layer, and wherein the material of first dielectric layer is two
Silica；And
One second dielectric layer is set between first dielectric layer and the third dielectric layer, wherein the material of second dielectric layer
For silicon nitride.
13. semiconductor element according to claim 8, which is characterized in that the multiple doped region includes:
One first doped region, in the epitaxial layer of the surrounding of the grid, as a matrix area；And
One second doped region, in the upper surface of first doped region of surrounding of grid part, as source region.
14. semiconductor element according to claim 13, which is characterized in that further include:
One third doped region is located in first doped region, and wherein second doped region has a groove, the third doped region
Position corresponds to the position of the groove.
15. semiconductor element according to claim 13, which is characterized in that further include:
One third doped region is located in first doped region, and wherein the bottom depth of the third doped region is greater than second doping
The bottom depth in area.
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Application publication date: 20190305 |