CN110504218A - The manufacturing method of semiconductor devices and the method for forming cmos device - Google Patents
The manufacturing method of semiconductor devices and the method for forming cmos device Download PDFInfo
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- CN110504218A CN110504218A CN201910807815.3A CN201910807815A CN110504218A CN 110504218 A CN110504218 A CN 110504218A CN 201910807815 A CN201910807815 A CN 201910807815A CN 110504218 A CN110504218 A CN 110504218A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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Abstract
The present invention relates to a kind of manufacturing methods of semiconductor devices and the method for forming cmos device.The manufacturing method of the semiconductor devices is the following steps are included: provide semiconductor structure, the semiconductor structure includes substrate and high pressure trap, the first low pressure trap and the second low pressure trap on the substrate, the first gate oxide is covered on the high pressure trap, the first low pressure trap and the second low pressure trap have exposed silicon face；The second gate oxide is formed together on the first low pressure trap and the second low pressure trap；The protective mulch on the high pressure trap and the first low pressure trap；And the second gate oxide on the second low pressure trap is thinned, form third gate oxide.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of semiconductor devices for being used to form cmos device
Manufacturing method.
Background technique
With the rapid development of super large-scale integration, the integrated level of semiconductor chip is higher and higher.In semiconductor element
In the manufacturing process of part, need to form required semiconductor devices using the numerous and complicated process of multiple tracks.Metal oxide
Semiconductor transistor (MOSFET, Metal-Oxide-Semiconductor Field-Effect Transistor) is integrated
A kind of important basic component in circuit, mainly by semiconductor substrate, gate oxide, polysilicon gate, gate lateral wall layer
It is formed with source drain doped region.Complementary metal oxide semiconductor (CMOS, Complementary Metal Oxide
Semiconductor it) receives and is widely applied due to that can include N-channel and P-channel field-effect transistor (PEFT) pipe simultaneously.
However during forming the semiconductor devices for being used for cmos device, the process of multiple tracks complexity is needed, is produced into
This height, the period is long, and production efficiency is low.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of low costs, the manufacturing method of high-efficient semiconductor devices
And the method according to semiconductor devices formation cmos device.
The present invention is to solve above-mentioned technical problem and the technical solution adopted is that propose a kind of manufacturer of semiconductor devices
Method, comprising the following steps: provide semiconductor structure, the semiconductor structure includes substrate and the high pressure on the substrate
Trap, the first low pressure trap and the second low pressure trap are covered with the first gate oxide, the first low pressure trap and second on the high pressure trap
Low pressure trap has exposed silicon face；The second gate oxide is formed together on the first low pressure trap and the second low pressure trap；In
Protective mulch on the high pressure trap and the first low pressure trap；And the second gate oxidation on the second low pressure trap is thinned
Layer forms third gate oxide.
In one embodiment of this invention, the second gate is formed together on the first low pressure trap and the second low pressure trap
The step of oxide layer includes: to carry out furnace process to the semiconductor structure, in the first low pressure trap and the second low pressure trap
The silicon face forms second gate oxide.
In one embodiment of this invention, the semiconductor structure includes the high pressure trap, multiple of multiple doping types
The first low pressure trap of doping type and/or the second low pressure trap of multiple doping types, and it is each described including being isolated
The fleet plough groove isolation structure of high pressure trap, the first low pressure trap and/or the second low pressure trap.
In one embodiment of this invention, the operating voltage of the first low pressure trap is higher than the work of the second low pressure trap
Voltage.
In one embodiment of this invention, the method that the second gate oxide on the second low pressure trap is thinned includes wet process
Etching.
In one embodiment of this invention, the step of forming the semiconductor structure includes: offer initial semiconductor structure,
The initial semiconductor structure includes substrate and high pressure trap, the first low pressure trap and the second low pressure trap on the substrate, institute
It states and is covered with initial gate oxide on high pressure trap, the first low pressure trap and the second low pressure trap are covered with sacrificial layer；And it is thinned
The initial gate oxide and the sacrificial layer is removed together, so that first gate oxide is formed in the high pressure trap, and
Keep the silicon face of the first low pressure trap and the second low pressure trap exposed.
In one embodiment of this invention, the initial gate oxide is thinned and removes the method packet of the sacrificial layer together
Include wet etching.
In one embodiment of this invention, the above method further includes in the high pressure trap, the first low pressure trap and the second low pressure
Trap is respectively formed cmos device.
In one embodiment of this invention, the protective layer is photoresist layer.
Also a kind of method for forming cmos device of the present invention, the manufacturing method including semiconductor devices as described above.
Manufacturing method according to the invention can remove on the first low pressure trap and the second low pressure trap simultaneously in one step
Sacrificial layer, and form on the first low pressure trap and the second low pressure trap the second gate that a layer thickness is suitable for the first low pressure trap together
Oxide layer, and the second gate oxide being thinned on the second low pressure trap on this basis, to form thickness suitable for the second low pressure trap
Third gate oxide reduces the process of manufacture；In this manufacturing method, it is only necessary to low to form first using a furnace process
The gate oxide on trap and the second low pressure trap is pressed, the cost of manufacturing process is reduced, and shortens and generates the period, is improved on the whole
Production efficiency.
Detailed description of the invention
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates, in which:
Figure 1A to 1H is to form gate oxide corresponding to the first low pressure trap and the second low pressure trap in the semiconductor device
Example process schematic diagram；
Fig. 2 is the exemplary process flow diagram of the manufacturing method of the semiconductor devices of one embodiment of the invention；
Fig. 3 A to 3D corresponds to the manufacturing process schematic diagram of the semiconductor devices of flow chart shown in Fig. 2.
Specific embodiment
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
It is different from other way described herein using other and implements, therefore the present invention is by the limit of following public specific embodiment
System.
As shown in the application and claims, unless context clearly prompts exceptional situation, " one ", "one", " one
The words such as kind " and/or "the" not refer in particular to odd number, may also comprise plural number.It is, in general, that term " includes " only prompts to wrap with "comprising"
Include clearly identify the step of and element, and these steps and element do not constitute one it is exclusive enumerate, method or apparatus
The step of may also including other or element.
When describing the embodiments of the present invention, for purposes of illustration only, indicating that the sectional view of device architecture can disobey general proportion work
Partial enlargement, and the schematic diagram is example, should not limit the scope of protection of the invention herein.In addition, in practical system
It should include the three-dimensional space of length, width and depth in work.
For the convenience of description, herein may use such as " under ", " lower section ", " being lower than ", " following ", " top ", "upper"
Etc. spatial relationship word the relationships of an elements or features shown in the drawings and other elements or feature described.It will reason
Solve, these spatial relationship words be intended to encompass in use or device in operation, other than the direction described in attached drawing
Other directions.For example, being described as be in other elements or feature " below " or " under " if overturning the device in attached drawing
Or the direction of the element of " following " will be changed to " top " in the other elements or feature.Thus, illustrative word " under
Side " and " following " can include upper and lower both direction.Device may also have other directions (to be rotated by 90 ° or in its other party
To), therefore spatial relation description word used herein should be interpreted accordingly.In addition, it will also be understood that being referred to as when one layer at two layers
" between " when, it can be only layer between described two layers, or there may also be one or more intervenient layers.
In the context of this application, structure of the described fisrt feature in the "upper" of second feature may include first
Be formed as the embodiment directly contacted with second feature, also may include that other feature is formed between the first and second features
Embodiment, such first and second feature may not be direct contact.
It is referred to as " on the other part " it should be appreciated that working as a component, " being connected to another component ", " is coupled in
When another component " or " contacting another component ", it can directly on another component, be connected or coupled to,
Or another component is contacted, or may exist insertion part.In contrast, when a component is referred to as " directly another
On a component ", " being directly connected in ", " being coupled directly to " or when " directly contact " another component, insertion part is not present.Together
Sample, when first component referred to as " is in electrical contact " or " being electrically coupled to " second component, in the first component and this second
There is the power path for allowing electric current flowing between part.The power path may include capacitor, the inductor of coupling and/or permission electricity
Other components of flowing, or even do not contacted directly between conductive component.
Figure 1A to 1H is to form gate oxide corresponding to the first low pressure trap and the second low pressure trap in the semiconductor device
Example process schematic diagram.Below in conjunction with Figure 1A to Fig. 1 H, to the first low pressure trap and the second low pressure trap in the semiconductor devices
The forming process of corresponding gate oxide is illustrated.
With reference to shown in Figure 1A, substrate 101, high-pressure trap area 110, the first low pressure well region have been formd on the semiconductor devices
120 and the second low pressure well region 130.Wherein, between high-pressure trap area 110, the first low pressure well region 120 and the second low pressure well region 130
It is formed with shallow trench isolation region (STI, Shallow Trench Isolation) 140.Different doping classes in the same region
Shallow trench isolation region 140 is also formed between the trap of type.For example, being formed with the first p-type trap 112, N-type trap in high-pressure trap area 110
113 and the second p-type trap 114.Between first P type trap zone 112 and N-type well region 113 and N-type well region 113 and the second p-type
Shallow trench isolation region 140 is formed between well region 114.Equally, in the first low pressure well region 120 and the second low pressure well region 130 not
With between doping type well region also have shallow trench isolation region 140.For example, including p-type trap 122 and N in the first low pressure well region 120
Type trap 123 is formed with shallow trench isolation region 140 between the p-type trap 122 and N-type trap 123；Include in the second low pressure well region 130
N-type trap 132 and p-type trap 133 are also formed with shallow trench isolation region 140 between the N-type trap 132 and p-type trap 133.
Shallow trench isolation region 140 can be used for being isolated different regions.Formed shallow trench isolation region 140 technique may include every
Slot is formed from oxide deposition, mask layer deposition (such as nitride), etching, fills deposition of insulative material (as aoxidized in slot
Object), the techniques such as planarization process.
With reference to shown in Figure 1A, one layer of gate oxide 111 is formed in the top of high-pressure trap area 110.In the first low pressure well region
120 and second the top of low pressure well region 130 be respectively formed with one layer of sacrificial layer 121,131.It needs to distinguish in subsequent processing procedure
Corresponding gate oxide is formed in the top of the first low pressure well region 120 and the second low pressure well region 130.It is eventually formed in high-pressure trap area
110, the thickness of the gate oxide of 130 top of the first low pressure well region 120 and the second low pressure well region is different, mesohigh trap
The thickness of the gate oxide of 110 top of area is most thick, and the thickness of the gate oxide of 120 top of the first low pressure well region takes second place, and second is low
Press the thickness of the gate oxide of 130 top of well region most thin.The thickness of gate oxide and the region are formed by opening for cmos device
Open voltage correlation, in general, the thickness of gate oxide is thicker, corresponding to cut-in voltage it is higher.
With reference to shown in Figure 1B, in this step, one layer of photoresist layer 150 is covered in the top of entire semiconductor devices.
With reference to shown in Fig. 1 C, in this step, by techniques such as photoetching developments, remove on the first low pressure well region 120
The photoresist layer 150 of side will need to form partially opening for gate oxide above first low pressure well region 120 and prepare in order to subsequent.
After removing removing photoresistance layer 150, in order to which follow-up process is prepared, need necessary clear to being carried out above the first low pressure well region 120
Wash step.Therefore, Fig. 1 C has corresponded to two steps.
With reference to shown in Fig. 1 D, in this step, using wet etching by the sacrificial layer 121 of the top of the first low pressure well region 120
Remove, exposes substrate.Meanwhile it being also all removed positioned at the photoresist layer in other regions 150.
With reference to shown in Fig. 1 E, in this step, it is necessary first to carrying out growth of gate oxide layer above the first low pressure well region 120
Pre-cleaning process before.Then gate oxide 122 is grown above the first low pressure well region 120 using boiler tube method.It is formed by
The thickness of gate oxide 122 meets the requirement of cmos device.It is appreciated that Fig. 1 E has corresponded to two steps.
With reference to shown in Fig. 1 F, before this step, it is omitted and covers one layer of photoresist layer in the top of entire semiconductor devices
150 the step of.Then, by techniques such as photoetching developments, remove the photoresist layer 150 above the second low pressure well region 130.Cause
This, Fig. 1 F has corresponded to two steps.
With reference to shown in Fig. 1 G, in this step, using wet etching by the sacrificial layer 121 of the top of the second low pressure well region 130
Remove, exposes substrate.Meanwhile it being also all removed positioned at the photoresist layer in other regions 150.
With reference to shown in Fig. 1 H, in this step, it is necessary first to carrying out growth of gate oxide layer above the second low pressure well region 130
Pre-cleaning process before.Then gate oxide 132 is grown above the second low pressure well region 130 using boiler tube method.It is formed by
The thickness of gate oxide 132 meets the requirement of cmos device.It is appreciated that Fig. 1 H has corresponded to two steps.
By the process of above-mentioned Figure 1A to 1H, the high-pressure trap area 110 of the semiconductor devices, the first low pressure well region 120 and
The top of two low pressure well regions 130, which respectively corresponds, is formed with gate oxide 111,122 and 132, and the thickness of three gate oxides
Degree is different from, and wherein the gate oxide 111 of high-pressure trap area 110 is most thick, the thickness of the gate oxide 122 of the first low pressure well region 120
Degree takes second place, and the thickness of the gate oxide 132 of the second low pressure well region 130 is most thin.
In addition to Figure 1A, from Figure 1B to 1H include at least 11 steps, wherein also do not include may need cleaning or
Planarization process.Wherein, in order to be respectively formed the gate oxide 122 of the first low pressure well region 120 and the grid of the second low pressure well region 130
Oxide layer 132 has used boiler tube method twice altogether.Whole process step is more, long using the at high cost of boiler tube method, process time.
Fig. 2 is the exemplary process flow diagram of the manufacturing method of the semiconductor devices of one embodiment of the invention.Fig. 3 A to 3D
Correspond to the manufacturing process schematic diagram of the semiconductor devices of flow chart shown in Fig. 2.In conjunction with shown in Fig. 2 and Fig. 3 A to 3D, the reality
Apply the manufacturing method of example the following steps are included:
Step 210, semiconductor structure is provided.
With reference to shown in Fig. 3 A, the semiconductor structure provided in this step includes substrate 301 and the height on substrate 301
Trap 310, the first low pressure trap 320 and the second low pressure trap 330 are pressed, the first gate oxide 311 is covered on the high pressure trap 310, the
One low pressure trap 320 and the second low pressure trap 330 have exposed silicon face.
The substrate 301 in provided semiconductor structure can be well-known to those skilled in the art in step 210
Various semiconductor materials, for example, silicon substrate (Si), germanium substrate (Ge), silicon-Germanium substrate (SiGe), silicon-on-insulator (SOI,
Silicon on Insulator) or germanium on insulator (GOI, Germanium on Insulator) etc..Wherein, silicon substrate can
To include monocrystalline substrate, multicrystalline silicon substrate etc..Silicon substrate, therefore the first low pressure trap 320 are used in an embodiment of the present invention
There is exposed silicon face with the second low pressure trap 330.
In the semiconductor structure, the operating voltage of high pressure trap 310 is higher than the first low pressure trap 320 and the second low pressure trap 330.
In some embodiments, the operating voltage of the first low pressure trap 320 is higher than the operating voltage of the second low pressure trap 330.Here work
Voltage can refer to the cut-in voltage or threshold voltage of the cmos device formed according to the semiconductor structure.
It is appreciated that the semiconductor structure in this step is a certain stage institute shape in the manufacturing process of semiconductor devices
At semiconductor structure.
In some embodiments, the step of forming the semiconductor structure of this step may comprise steps of:
Step 201, initial semiconductor structure is provided, which includes substrate 301 and be located on substrate 301
High pressure trap 310, the first low pressure trap 320 and the second low pressure trap 330, be covered with initial gate oxide on the high pressure trap 310, this
One low pressure trap 320 and the second low pressure trap 330 are covered with sacrificial layer.
Provided initial semiconductor structure can refer to Figure 1A in step 201.With reference to shown in Figure 1A, high pressure therein
Well region 110 corresponds to the high pressure trap 310 in this step, and the first low pressure well region 120 corresponds to the first low pressure trap 320, the second low pressure
Well region 130 corresponds to the second low pressure trap 330.With semiconductor structure shown in figure 1A the difference is that provided in step 201
The thickness of the initial gate oxide covered on high pressure trap 310 is greater than the gate oxide 111 on the high-pressure trap area 110 in Figure 1A
Thickness.
Step 202, the initial gate oxide is thinned and removes the sacrificial layer together, to form first in high pressure trap 310
Gate oxide 311, and keep the silicon face of the first low pressure trap 320 and the second low pressure trap 330 exposed.
In some embodiments, the technique that can use wet etching, the upper surface of initial semiconductor structure is integrally subtracted
It is thin.By the control to wet-etching technology, the sacrificial layer on the first low pressure trap 320 and the second low pressure trap 330 can be made complete
It is removed, while the initial gate oxide on high pressure trap 310 is also got rid of into a part, form the first grid as shown in Figure 3A
Oxide layer 311.The thickness of first gate oxide 311 can according to user the characteristic of cmos device to be formed determine.
In step 201, the thickness of the initial gate oxide on high pressure trap 310 should be greater than or equal to the thickness of the first gate oxide 311
Degree and the sum of the thickness of sacrificial layer on the first low pressure trap 320 and the second low pressure trap 330.
According to step 201 and 202, semiconductor structure as shown in Figure 3A can be both obtained.
In some embodiments, which includes the high pressure trap 310 of multiple doping types, multiple doping types
Second low pressure trap 330 of the first low pressure trap 320 and/or multiple doping types, and it is low including each high pressure trap 310, first is isolated
Press the fleet plough groove isolation structure 340 of trap 320 and/or the second low pressure trap 330.
With reference to shown in Fig. 3 A, in these embodiments, in high pressure trap 310 including multiple doping types high pressure trap 312a,
312b and 313, wherein high pressure trap 312a and 312b can have same doping type, such as p-type doping；High pressure trap 313 has
There are the doping type different from high pressure trap 312a and 312b, such as n-type doping.It include multiple doping classes in first low pressure trap 320
First low pressure trap 322 and 323 of type, wherein the doping type of the first low pressure trap 322 and the first low pressure trap 323 can be difference
, such as the first low pressure trap 322 is p-type doping, and the first low pressure trap 323 is n-type doping.It include more in second low pressure trap 330
Second low pressure trap 332 and 333 of a doping type, wherein the doping type of the second low pressure trap 332 and the second low pressure trap 333 can
To be different, such as the second low pressure trap 332 is n-type doping, and the second low pressure trap 333 is p-type doping.
In an embodiment of the present invention, p-type Doped ions can be for example: indium ion, boron ion, gallium ion, aluminium ion,
It is fluorinated boron ion etc.；N-type doping ion can be for example: arsenic ion, phosphonium ion, antimony ion etc..
Fig. 3 A is not used in high pressure trap 310, the first low pressure trap 320 and the second low pressure trap 330 in the limitation embodiment of the present invention
Quantity, size, depth in the substrate and doping type etc..Those skilled in the art can be on the basis of the embodiment of the present invention
On make arbitrary transformation.
With reference to shown in Fig. 3 A, the first gate oxide 311 covered on high pressure trap 310 is not placed only in high pressure trap 310
On upper surface, also it is covered on the upper surface of surrounding substrate 301.And the upper surface of first gate oxide 311 is one
Plane.
The upper surface of fleet plough groove isolation structure 340 between each trap is higher by the upper surface of the first gate oxide 311.
The technique for forming the fleet plough groove isolation structure 340 may include isolating oxide layer deposition, mask layer deposition (such as nitride), etching
It forms slot, fill deposition of insulative material (such as oxide), planarization process technique in slot.
Step 220, the second gate oxide is formed together on the first low pressure trap and the second low pressure trap.
With reference to shown in Fig. 3 B, in this step, second is formed together on the first low pressure trap 320 and the second low pressure trap 330
Gate oxide 321.For the convenience of description, the first low pressure trap 322 and 323 of doping types different in Fig. 3 A is referred to as in figure 3b
For the first low pressure trap 320, and the second low pressure trap 332 and 333 of different doping types is referred to as the second low pressure trap 330.
Since second gate oxide 321 is formed together using a procedure, in the first low pressure trap 320 and the
The thickness that the second gate oxide 321 is formed by two low pressure traps 330 is consistent.In this step, second gate oxide
321 thickness is controlled based on the thickness requirement to the gate oxide on the first low pressure trap 320.In the embodiment of the present invention
In, the thickness of second gate oxide 321 is less than the thickness of the first gate oxide 311 on high pressure trap 310.
The embodiment of the present invention does not limit the method for forming the second gate oxide 321, can use thermal oxidation method
(RTO, Rapid Thermal Oxidation) or situ steam method of formation (ISSG, In-situ Stream Generation)
The silicon oxide layer of formation forms second gate oxide 321.
In a preferred embodiment, the second gate oxide is formed together on the first low pressure trap 320 and the second low pressure trap 330
321 the step of includes: to carry out furnace process to semiconductor structure, in the silicon face of the first low pressure trap 320 and the second low pressure trap 330
Form the second gate oxide 321.
It should be noted that before forming the second gate oxide 321 according to furnace process, it is also necessary to semiconductor structure
The process cleaned of surface.It therefore actually include two steps in step 220.
With reference to shown in Fig. 3 B, which is not placed only in the first low pressure trap 320 and the second low pressure trap 330
Upper surface on, be also covered on the upper surface of surrounding substrate 301.And the upper surface of second gate oxide 321 is
One plane.The upper surface of fleet plough groove isolation structure 340 between each trap is higher by the upper surface of the second gate oxide 321.
Step 230, the protective mulch on high pressure trap and the first low pressure trap.
With reference to shown in Fig. 3 C, in this step, protective layer 350 is covered on high pressure trap 310 and the first low pressure trap 320.
For the convenience of description, high pressure trap 312a, 312b and 313 of doping types different in Fig. 3 A is referred to as high pressure trap in fig. 3 c
310.With reference to shown in Fig. 3 C, which is not placed only on high pressure trap 310 and the first low pressure trap 320, is also covered on its week
On the upper surface of the substrate 301 enclosed.And the upper surface of the protective layer 350 is a flat surface.
In actual process, a protective layer 350 is all covered in the upper surface of the semiconductor structure first, then again
A part of protective layer 350 for being located at 330 top of the second low pressure trap is removed, the second grid of 330 top of the second low pressure trap is exposed
Oxide layer 321.Therefore, Fig. 3 C has corresponded to two steps.
In some embodiments, which is photoresist layer.In these embodiments, photoetching development can be passed through
Technique removes a part of protective layer 350 above the second low pressure trap 330.
Step 240, the second gate oxide on the second low pressure trap is thinned, forms third gate oxide.
With reference to shown in Fig. 3 D, the second gate oxide 321 on the second low pressure trap 330 is thinned, forms third gate oxide
331.Thickness of the thickness of the third gate oxide 331 less than the second gate oxide 321.In this step, while position is eliminated
Protective layer 350 on high pressure trap 310 and the first low pressure trap 320.This step can be executed using the technique of wet etching.Root
The third gate oxide 331 on the second low pressure trap 330 is not only formd due to the technique using wet etching according to this step, also
The second gate oxide 321 on first low pressure trap 320 is cleaned, realizes two in original technique in one step
A step.
In addition to the step 201 in step 210, with reference to Fig. 3 A to 3D and step 202,220-240, the embodiment of the present invention
The manufacturing method of semiconductor devices mainly include 6 steps.It is compared with original manufacturing process, number of steps substantially reduces.And
And in the manufacturing method of semiconductor devices of the invention, a furnace process need to be only used in a step 220, it can same
When the silicon face of the first low pressure trap 320 and the second low pressure trap 330 formed gate oxide, reduce the cost in manufacturing process,
Manufacturing time is saved.
It, can be in high pressure trap 310, the first low pressure trap 320 and the second low pressure trap 330 in the follow-up process of the manufacturing method
On be respectively formed cmos device.For example, forming source, leakage and the grid of cmos device in each high pressure trap 310.
The invention also includes a kind of methods for forming cmos device, and this method is according to previously described semiconductor devices
On the basis of manufacturing method semiconductor devices obtained, corresponding cmos device can be formed.And it is possible to according to wanted shape
At the characteristic of cmos device determine the thickness of the first gate oxide 311, the second gate oxide 321 and third gate oxide 331
Degree, to meet requirement of the different cmos devices to its operating voltage.
In the context of the present invention, some steps are omitted in the manufacturing method of semiconductor devices, such as planarize
Processing, surface clean, descum etc..The emphasis of these and non-present invention, herein not reinflated description.Those skilled in the art
It can according to need and increase or decrease it in the manufacturing method of semiconductor devices of the invention and the method for formation cmos device
In step.It is appreciated that these steps may include in the manufacturing method of existing semiconductor devices, also may include
In the manufacturing method of semiconductor devices of the invention, therefore, the manufacturing method of semiconductor devices of the invention and existing manufacture
Method is compared, and is still reduced the process of manufacture, is saved manufacturing time and production cost.
Although the present invention is described with reference to current specific embodiment, those of ordinary skill in the art
It should be appreciated that above embodiment is intended merely to illustrate the present invention, can also make in the case where no disengaging spirit of that invention
Various equivalent change or replacement out, therefore, as long as to the variation of above-described embodiment, change in spirit of the invention
Type will all be fallen in the range of following claims.
Claims (10)
1. a kind of manufacturing method of semiconductor devices, comprising the following steps:
Semiconductor structure is provided, the semiconductor structure includes substrate and high pressure trap, the first low pressure trap on the substrate
With the second low pressure trap, the first gate oxide is covered on the high pressure trap, the first low pressure trap and the second low pressure trap have naked
The silicon face of dew；
The second gate oxide is formed together on the first low pressure trap and the second low pressure trap；
The protective mulch on the high pressure trap and the first low pressure trap；And
The second gate oxide on the second low pressure trap is thinned, forms third gate oxide.
2. the method as described in claim 1, which is characterized in that formed together on the first low pressure trap and the second low pressure trap
The step of second gate oxide includes: to carry out furnace process to the semiconductor structure, in the first low pressure trap and the
The silicon face of two low pressure traps forms second gate oxide.
3. the method as described in claim 1, which is characterized in that the semiconductor structure includes the height of multiple doping types
Trap, the first low pressure trap of multiple doping types and/or the second low pressure trap of multiple doping types are pressed, and including isolation
The fleet plough groove isolation structure of each high pressure trap, the first low pressure trap and/or the second low pressure trap.
4. the method as described in claim 1, which is characterized in that it is low that the operating voltage of the first low pressure trap is higher than described second
Press the operating voltage of trap.
5. the method as described in claim 1, which is characterized in that the side of the second gate oxide on the second low pressure trap is thinned
Method includes wet etching.
6. the method as described in claim 1, which is characterized in that the step of forming the semiconductor structure include:
There is provided initial semiconductor structure, the initial semiconductor structure includes substrate and high pressure trap on the substrate, the
One low pressure trap and the second low pressure trap are covered with initial gate oxide, the first low pressure trap and the second low pressure on the high pressure trap
Trap is covered with sacrificial layer；And
The initial gate oxide is thinned and removes the sacrificial layer together, to form first grid oxygen in the high pressure trap
Change layer, and keeps the silicon face of the first low pressure trap and the second low pressure trap exposed.
7. method as claimed in claim 6, which is characterized in that the initial gate oxide is thinned and removes the sacrifice together
The method of layer includes wet etching.
8. the method as described in claim 1, which is characterized in that further include low in the high pressure trap, the first low pressure trap and second
Pressure trap is respectively formed cmos device.
9. the method as described in claim 1, which is characterized in that the protective layer is photoresist layer.
10. a kind of method for forming cmos device, including such as the described in any item methods of claim 1-9.
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