CN105355596A - Method for manufacturing CMOS device - Google Patents
Method for manufacturing CMOS device Download PDFInfo
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- CN105355596A CN105355596A CN201410411754.6A CN201410411754A CN105355596A CN 105355596 A CN105355596 A CN 105355596A CN 201410411754 A CN201410411754 A CN 201410411754A CN 105355596 A CN105355596 A CN 105355596A
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- oxide layer
- grid oxide
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- tension apparatus
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Abstract
The invention relates to the field of semiconductors, and provides a method for manufacturing a CMOS device. The method includes the following steps: growing a first gate oxide layer on a substrate surface; coating a surface of the first gate oxide layer of a high-voltage device part with photoresist and photo-etching the surface of the first gate oxide layer; etching the first gate oxide layer to etch off the first gate oxide layer of a low-voltage device part; growing a second gate oxide layer on the substrate surface, wherein the thickness of the second gate oxide layer is less than that of the first gate oxide layer; coating the surface of the first gate oxide layer of the high-voltage device part with photoresist and photo-etching the surface of the first gate oxide layer; performing threshold injection on a substrate; and growing polycrystalline silicon on the first gate oxide layer and the second gate oxide layer. According to the method, the CMOS device with a low-voltage device and a high-voltage device can be manufactured, and meanwhile, the threshold injection can be performed to adjust the threshold voltage of the low-voltage device, and ions cannot enter the high-voltage device, so that the threshold voltage of the high-voltage device can be reduced.
Description
Technical field
The present invention relates to semiconductor applications, particularly relate to the manufacture method of a kind of CMOS (ComplementaryMetalOxideSemiconductor complementary metal oxide semiconductors (CMOS)) device.
Background technology
The cmos device that conventional CMOS device manufacturing process produces is merely able to the power supply requirement meeting 5V, but along with the development of technology, creates and go for high-tension high tension apparatus.When starting pipe or drive circuit owing to making of high tension apparatus, its threshold voltage is much larger than common CMOS, and the voltage being less than this threshold voltage cannot drive high tension apparatus to carry out work, and increases the risk that voltage brings and be just to puncture grid, causes the damage of device.Therefore need the threshold voltage of high tension apparatus to do little when manufacturing and there is the cmos device of high tension apparatus as far as possible.
As shown in Figure 1, have in the cmos device of high tension apparatus that to have a kind of be have low-voltage device and high tension apparatus simultaneously, the oxide layer of this device surface comprises field oxide (being called for short field oxygen), grid oxic horizon.Low-voltage device comprises PMOS (PositiveChannelMetalOxideSemiconductorP NMOS N-channel MOS N) device and NMOS (NegativeChannelMetalOxideSemiconductorN NMOS N-channel MOS N) device, because the threshold voltage of PMOS device and nmos device is asymmetric, the ion that therefore must inject such as boron ion when manufacturing cmos device carries out the adjustment of the threshold voltage of low-voltage device.And when carrying out threshold value injection in traditional handicraft, ion can be injected in high tension apparatus, and the threshold value of high tension apparatus will become large, opposing with the object of the threshold voltage reducing high tension apparatus.
Therefore, need a kind of method, when manufacture has the cmos device of low-voltage device and high tension apparatus simultaneously, threshold value can either be carried out and inject with the threshold voltage regulating low-voltage device, can prevent again ion from entering high tension apparatus, thus the threshold voltage of high tension apparatus can be reduced.
Summary of the invention
The embodiment provides a kind of cmos device manufacture method, the cmos device that manufacture has low-voltage device and high tension apparatus simultaneously can be applied to, while realizing that threshold voltage adjustments is carried out to low-voltage device, reduce the threshold voltage of high tension apparatus.
In order to reach above-mentioned purpose, The embodiment provides a kind of manufacture method comprising the cmos device of high tension apparatus part and low-voltage device part, comprising the following steps:
The first grid oxic horizon is grown at substrate surface.At the first grid oxide layer surface-coated photoresist of high tension apparatus part, and photoetching is carried out to first grid oxide layer.First grid oxide layer is etched, to etch away the first grid oxide layer of low-voltage device part.Grow the second grid oxic horizon at substrate surface, the thickness of second grid oxide layer is less than the thickness of described first grid oxide layer.At the first grid oxide layer surface-coated photoresist of high tension apparatus part, and photoetching is carried out to first grid oxide layer.Threshold value injection is carried out to substrate.Growing polycrystalline silicon in first grid oxide layer and second grid oxide layer.
Use the cmos device manufacture method of above-mentioned steps when manufacture has the cmos device of low-voltage device and high tension apparatus simultaneously, while realizing carrying out threshold voltage adjustments to low-voltage device, the threshold voltage of high tension apparatus can be reduced.
Preferably, after first grid oxide layer is etched, removal photoresist is also comprised.
Remove photoresist after first grid oxide layer is etched, can more successfully grow the second grid oxic horizon.
Preferably, after carrying out the injection of substrate threshold value, removal photoresist is also comprised.
After threshold value is injected, remove photoresist, more successfully can carry out the growth of polysilicon.
Preferably, wet etching technique is used to etch first grid oxide layer.
Owing to there is no very high requirement for the thickness after first grid oxide layer etching in such scheme, but therefore select the not high selectivity of precision higher, use wet etching technique widely to etch.
The embodiment provides the another kind of manufacture method comprising the cmos device of high tension apparatus part and low-voltage device part based on same design, comprise the following steps: grow the first grid oxic horizon at substrate surface.The first grid oxide layer of high tension apparatus part applies photoresist, and photoetching is carried out to first grid oxide layer.Described first grid oxide layer is etched, with by the first grid oxide layer of low-voltage device part etching for thickness is the second grid oxide layer of the first thickness, the first thickness is less than the thickness of first grid oxide layer.Threshold value injection is carried out to substrate.Growing polycrystalline silicon in first grid oxide layer and second grid oxide layer.
Compared with the method that said method and the last embodiment of the present invention provide, owing to not needing growth second grid oxic horizon, therefore, it is possible to control the thickness of the first grid oxide layer of high tension apparatus part better, also save raw material simultaneously.
Preferably, after threshold value injection is carried out to substrate, remove photoresist.
After threshold value is injected, remove photoresist, more successfully can carry out the growth of polysilicon.
Preferably, ion beam milling lithographic technique is used to etch first grid oxide layer.
Owing to having requirement for the thickness of the grid oxic horizon of the low-voltage device after etching in this manufacture method, the ion beam milling lithographic technique that therefore choice accuracy is higher carries out the etching to first grid oxide layer.
The cmos device manufacture method that the embodiment of the present invention provides is by using the photoresist shade high tension apparatus part after photoetching when carrying out threshold value and injecting, when manufacture has the cmos device of low-voltage device and high tension apparatus simultaneously, while realizing that threshold voltage adjustments is carried out to low-voltage device, reduce the threshold voltage of high tension apparatus.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the cmos device simultaneously with low-voltage device and high tension apparatus.
The flow chart of a kind of cmos device manufacture method that Fig. 2 provides for the embodiment of the present invention.
Fig. 3 a-Fig. 3 h is the schematic diagram processing cmos device in Fig. 2 in cmos device manufacture method in each step.
The flow chart of the another kind of cmos device manufacture method that Fig. 4 provides for the embodiment of the present invention.
Fig. 5 a-Fig. 5 f is the schematic diagram processing cmos device in Fig. 4 in cmos device manufacture method in each step.
Embodiment
As shown in Fig. 2 and Fig. 3 a-Fig. 3 h, the flow chart of a kind of cmos device manufacture method that the embodiment of the present invention provides, mainly comprises following key step:
S201, as shown in Figure 3 a, grow the first grid oxic horizon at substrate surface.In the present embodiment, substrate is P type substrate (P-Sub), and the thickness of first grid oxide layer is
and first grid oxide layer is generated by thermal oxidation substrate surface.
S202, as shown in Figure 3 b, after the first grid oxide layer surface-coated photoresist of high tension apparatus part, photoetching is carried out to first grid oxide layer.
S203, as shown in Figure 3 c, first grid oxide layer to be etched, the first grid oxide layer of low-voltage device part is carved complete eating away, and the first grid oxide layer of high tension apparatus part can be retained completely due to the existence of photoresist.After first grid oxide layer is etched, preferably, photoresist be removed.About the removal of photoresist, the method for stripping can be adopted also can to adopt additive method.And for the selection of lithographic method, wet etching preferably can be selected, because this time etching required precision to etching is not high, selectivity therefore can be adopted higher, use wet etching method widely to etch.
S204, as shown in Figure 3 d, grow the second grid oxic horizon at substrate surface, the thickness of the Thickness Ratio first grid oxide layer of second grid oxide layer is little.Because the first grid oxide layer of low-voltage device part has been etched away, therefore the surface of low-voltage device part only has second grid oxide layer.In the present embodiment, the thickness of second grid oxide layer is
due to before this, having defined thickness on high tension apparatus surface is
grid oxic horizon, therefore second time thermal oxidation is minimum at the thickness of the second grid oxide layer of high tension apparatus surface formation, therefore, in the present embodiment, still the grid oxic horizon through growing the high tension apparatus surface after the second grid oxic horizon is called first grid oxide layer.In addition, second grid oxide layer is generated by thermal oxidation substrate surface in the present embodiment.
S205, as shown in Figure 3 e, at the first grid oxide layer surface-coated photoresist of high tension apparatus part, and carry out photoetching to first grid oxide layer, in this time photoetching, photoresist only covers the first grid oxide layer on high tension apparatus surface.
S206, as illustrated in figure 3f, carry out threshold value injection to substrate, inject boron ion, energy is 25 kilo electron volts, and dosage is 9E11 atom/square centimeter.Have the photoresist through photoetching to cover due to above now high tension apparatus, therefore boron ion can not enter into high tension apparatus inside through photoresist.Therefore, now because boron ion can not enter high tension apparatus inside, the threshold voltage of high tension apparatus can not rise, and the threshold voltage of low-voltage device obtains adjustment because low-voltage device obtains the injection of boron ion.
S207, as shown in figure 3g, removes photoresist.The method of stripping can be adopted to remove photoresist and also can adopt additive method.
S208, as illustrated in figure 3h, in first grid oxide layer and second grid oxide layer, growing polycrystalline silicon forms polysilicon layer.
As shown in Fig. 4 and Fig. 5 a-Fig. 5 f, the embodiment of the present invention provides the flow chart of another kind of cmos device manufacture method, mainly comprises following key step:
S401, as shown in Figure 5 a, grow the first grid oxic horizon at substrate surface.In the present embodiment, to be the thickness of P type substrate (P-Sub) first grid oxide layer be substrate
and grown at substrate surface by thermal oxidation.
S402, as shown in Figure 5 b, apply photoresist in the first grid oxide layer of high tension apparatus part, and photoetching is carried out to first grid oxide layer.
S403, as shown in Figure 5 c, first grid oxide layer to be etched.When wherein etching, the moment notes the thickness of grid oxic horizon, and the first grid oxide layer of low-voltage device part is etched to the second grid oxide layer that thickness is less than first grid oxidated layer thickness, in this embodiment, the thickness of second grid oxide layer is
Owing to not being etching away low-voltage device part completely, carry out second time thermal oxidation again, therefore now, the grid oxic horizon of high tension apparatus part can not increase again, therefore this method is conducive to the thickness of the grid oxic horizon controlling high tension apparatus part, and also saves raw material simultaneously.
Meanwhile, in the present embodiment, use the method for ion beam milling to etch, owing to now having specific requirement for the thickness after the first grid oxide layer etching of low-voltage device, therefore adopt the method for the higher ion beam milling of etching precision to etch.
S404, as fig 5d, carry out threshold value injection, inject boron ion, energy is 25 kilo electron volts, and dosage is 9E11 atom/square centimeter.Have the photoresist through overexposure to cover due to above now high tension apparatus, therefore boron ion can not enter into high tension apparatus inside through photoresist.Therefore, now because boron ion can not enter high tension apparatus inside, the threshold voltage of high tension apparatus can not rise, and the threshold voltage of low-voltage device obtains adjustment because low-voltage device obtains the injection of boron ion.
S405, as depicted in fig. 5e, removes photoresist.The method of stripping can be adopted to remove photoresist and also can adopt additive method.
S406, as shown in figure 5f, in first grid oxide layer and second grid oxide layer, growing polycrystalline silicon is to form polysilicon layer.
In this embodiment owing to not carrying out the growth of second time grid oxic horizon, therefore save raw material, and be also conducive to the thickness of the grid oxic horizon controlling high tension apparatus part.
The cmos device manufacture method that the embodiment of the present invention provides is by the shade high tension apparatus part when carrying out threshold value and injecting, have on the cmos device of low-voltage device and high tension apparatus at the same time, while realizing that threshold voltage adjustments is carried out to low-voltage device, reduce the threshold voltage of high tension apparatus.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (7)
1. a complementary metal oxide semiconductors (CMOS) cmos device manufacture method, described cmos device comprises high tension apparatus part and low-voltage device part, it is characterized in that, comprising:
The first grid oxic horizon is grown at substrate surface;
At the first grid oxide layer surface-coated photoresist of high tension apparatus part, and photoetching is carried out to described first grid oxide layer;
Described first grid oxide layer is etched, to etch away the first grid oxide layer of low-voltage device part;
Grow the second grid oxic horizon at described substrate surface, the thickness of described second grid oxide layer is less than the thickness of described first grid oxide layer;
At the first grid oxide layer surface-coated photoresist of high tension apparatus part, and photoetching is carried out to described first grid oxide layer;
Threshold value injection is carried out to described substrate;
Growing polycrystalline silicon in described first grid oxide layer and second grid oxide layer.
2. the method for claim 1, is characterized in that, after etching, also comprises: remove described photoresist described first grid oxide layer.
3. the method for claim 1, is characterized in that, after injecting, also comprises: remove described photoresist described substrate threshold value.
4. the method for claim 1, is characterized in that, carries out etching comprise described first grid oxide layer: use wet etching technique to etch described first grid oxide layer.
5. a complementary metal oxide semiconductors (CMOS) cmos device manufacture method, described cmos device comprises high tension apparatus part and low-voltage device part, it is characterized in that, comprising:
The first grid oxic horizon is grown at substrate surface;
The first grid oxide layer of high tension apparatus part applies photoresist, and photoetching is carried out to described first grid oxide layer;
Described first grid oxide layer is etched, with by the first grid oxide layer of low-voltage device part etching for thickness is the second grid oxide layer of the first thickness, described first thickness is less than the thickness of first grid oxide layer;
Threshold value injection is carried out to described substrate;
Growing polycrystalline silicon in described first grid oxide layer and second grid oxide layer.
6. method as claimed in claim 5, is characterized in that, after carrying out threshold value injection, also comprise: remove described photoresist to described substrate.
7. method as claimed in claim 5, is characterized in that, carry out etching comprise described first grid oxide layer: use ion beam milling lithographic technique to etch described first grid oxide layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410411754.6A CN105355596A (en) | 2014-08-20 | 2014-08-20 | Method for manufacturing CMOS device |
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| CN201410411754.6A CN105355596A (en) | 2014-08-20 | 2014-08-20 | Method for manufacturing CMOS device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110504218A (en) * | 2019-08-29 | 2019-11-26 | 长江存储科技有限责任公司 | The manufacturing method of semiconductor devices and the method for forming cmos device |
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| KR100279951B1 (en) * | 1999-01-25 | 2001-01-15 | 황인길 | Method for manufacturing split gate oxynitride of cmos transistor |
| JP2001176983A (en) * | 1999-12-20 | 2001-06-29 | Nec Corp | Semiconductor device and producing method therefor |
| CN1405846A (en) * | 2001-08-10 | 2003-03-26 | 三洋电机株式会社 | Grid insulated film forming method |
| JP2007165361A (en) * | 2005-12-09 | 2007-06-28 | Renesas Technology Corp | Semiconductor integrated circuit device and its manufacturing method |
| KR20090056261A (en) * | 2007-11-30 | 2009-06-03 | 주식회사 하이닉스반도체 | Method of forming transistor in semiconductir device |
| CN103871855A (en) * | 2012-12-17 | 2014-06-18 | 北大方正集团有限公司 | Preparation method of integrated circuit dual gate oxide |
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2014
- 2014-08-20 CN CN201410411754.6A patent/CN105355596A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100279951B1 (en) * | 1999-01-25 | 2001-01-15 | 황인길 | Method for manufacturing split gate oxynitride of cmos transistor |
| JP2001176983A (en) * | 1999-12-20 | 2001-06-29 | Nec Corp | Semiconductor device and producing method therefor |
| CN1405846A (en) * | 2001-08-10 | 2003-03-26 | 三洋电机株式会社 | Grid insulated film forming method |
| JP2007165361A (en) * | 2005-12-09 | 2007-06-28 | Renesas Technology Corp | Semiconductor integrated circuit device and its manufacturing method |
| KR20090056261A (en) * | 2007-11-30 | 2009-06-03 | 주식회사 하이닉스반도체 | Method of forming transistor in semiconductir device |
| CN103871855A (en) * | 2012-12-17 | 2014-06-18 | 北大方正集团有限公司 | Preparation method of integrated circuit dual gate oxide |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110504218A (en) * | 2019-08-29 | 2019-11-26 | 长江存储科技有限责任公司 | The manufacturing method of semiconductor devices and the method for forming cmos device |
| CN110504218B (en) * | 2019-08-29 | 2020-08-14 | 长江存储科技有限责任公司 | Method of manufacturing semiconductor device and method of forming CMOS device |
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