JP2007165361A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make the dual gate of a semiconductor integrated circuit device wherein a high withstand voltage complementary MISFET and a low withstand voltage complementary MISFET are formed on the same semiconductor substrate. <P>SOLUTION: An energy for implanting P ions to adjust a threshold voltage of a high withstand voltage p-channel MISFET is made larger than an energy for implanting B ions to adjust a threshold voltage of a high withstand voltage n-channel MISFET. In addition, when the B ions are implanted into an undoped silicon film in a p-channel MISFET formation area so as to convert it into a p-type silicon film 9p, the concentration of B of the p-type silicon film 9p adjacent to the boundary with a gate insulating film 8 is controlled to 2×10<SP>20</SP>atoms/cm<SP>3</SP>or less. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a semiconductor integrated circuit device in which a high withstand voltage complementary MISFET and a low withstand voltage complementary MISFET are formed on the same semiconductor substrate, and a technique effective in application to the manufacture thereof. .

  In recent years, a semiconductor device that constitutes a circuit using a complementary MISFET is configured such that the gate electrode of an n-channel MISFET is composed of an n-type polycrystalline silicon film, and the gate electrode of a p-channel MISFET is a p-type polycrystalline silicon film. The dual gate structure is used.

  This is because when the gate electrode of the n-channel type MISFET and the gate electrode of the p-channel type MISFET are both made of an n-type polycrystalline silicon film, the p-channel type MISFET becomes a buried channel type, which is short when the device is miniaturized. This is because the channel effect becomes prominent, and it is necessary to adopt a dual gate structure even if the number of steps is increased and to suppress the short channel effect and promote the miniaturization of the element.

As for semiconductor integrated circuit devices having dual-gate complementary MISFETs, for example, Japanese Patent Application Laid-Open No. 11-195713 (Patent Document 1), Japanese Patent Application Laid-Open No. 9-260509 (Patent Document 2) and Japanese Patent Application Laid-Open No. 10-50857. (Patent Document 3) and the like.
JP-A-11-195713 JP-A-9-260509 Japanese Patent Laid-Open No. 10-50857

  An electrically rewritable nonvolatile memory is composed of a memory array and a peripheral circuit, and the peripheral circuit further includes a circuit composed of a low-voltage complementary MISFET and a circuit composed of a high-voltage complementary MISFET. Consists of. The circuit composed of the low withstand voltage complementary MISFET is, for example, a sense amplifier, a column decoder, or a row decoder, and the circuit composed of the high withstand voltage complementary MISFET is, for example, a booster circuit.

  Even in the nonvolatile memory, when the p-channel type MISFET is configured as a buried channel type, a short channel effect such as a variation in threshold voltage becomes apparent as the element is miniaturized. Is desired to be the same surface channel type as that of the n-channel type MISFET.

  However, in the nonvolatile memory, when the p-channel type MISFET of the booster circuit is changed to the surface channel type, there is a problem that the NBT life is deteriorated, so that it is difficult to adopt the dual gate structure.

NBT lifetime deterioration is a phenomenon in which holes present in the channel of a p-channel MISFET cause an electrochemical reaction with Si bonding at the substrate interface, resulting in threshold voltage fluctuations and current deterioration. Yes, it has the property of being accelerated by high temperatures and negative gate bias. The buried channel type n ⁺ gate p-channel MISFET has a work function difference of about 1 V compared to the surface channel type p ⁺ gate p-channel MISFET, and the voltage applied to the gate electrode of the MISFET is high. NBT life is unlikely to deteriorate. On the other hand, when the p-channel type MISFET of the booster circuit in which a high voltage of 5 V or higher is applied to the gate electrode is made to be a surface channel type, the NBT lifetime deteriorates remarkably, leading to a decrease in reliability. .

  An object of the present invention is to provide a technique for realizing dual gate formation of a semiconductor integrated circuit device in which a high breakdown voltage complementary MISFET and a low breakdown voltage complementary MISFET are formed on the same semiconductor substrate.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

In the present invention, a low breakdown voltage p-channel MISFET is formed in a first region of a semiconductor substrate, a low breakdown voltage n-channel MISFET is formed in a second region of the semiconductor substrate, and a high breakdown voltage p-channel is formed in a third region of the semiconductor substrate. A method of manufacturing a semiconductor integrated circuit device, wherein a channel type MISFET is formed and a high breakdown voltage n-channel type MISFET is formed in a fourth region of the semiconductor substrate,
(A) implanting an n-type impurity for adjusting a threshold voltage of the low breakdown voltage p-channel MISFET into the first region of the semiconductor substrate with a first energy;
(B) A step of ion-implanting an n-type impurity for adjusting a threshold voltage of the high-breakdown-voltage p-channel MISFET with a third energy larger than the first energy into the third region of the semiconductor substrate. When,
(C) forming a first gate insulating film in the first and second regions of the semiconductor substrate;
(D) forming a second gate insulating film thicker than the first gate insulating film in the third and fourth regions of the semiconductor substrate;
(E) forming the low breakdown voltage p-channel MISFET having a gate electrode including a p-type silicon film in a first region of the semiconductor substrate, and having a gate electrode including an n-type silicon film in the second region of the semiconductor substrate; The low breakdown voltage n-channel MISFET is formed, the high breakdown voltage p-channel MISFET having a gate electrode including a p-type silicon film is formed in the third region of the semiconductor substrate, and the n-type is formed in the fourth region of the semiconductor substrate. Forming a high breakdown voltage n-channel MISFET having a gate electrode including a silicon film.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Even if the high breakdown voltage p-channel type MISFET is made the surface channel type, the deterioration of the NBT life can be suppressed. Therefore, the dual gate of the semiconductor integrated circuit device in which the high breakdown voltage complementary MISFET and the low breakdown voltage complementary MISFET are formed on the same semiconductor substrate can be realized. Can be realized.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
The manufacturing method of the nonvolatile memory according to the present embodiment will be described in the order of steps with reference to FIGS. This nonvolatile memory is composed of a memory array and a peripheral circuit, and the peripheral circuit is further composed of a circuit composed of a low withstand voltage complementary MISFET and a circuit composed of a high withstand voltage complementary MISFET. A voltage of, for example, 1.5 V is applied to the gate electrode of the low withstand voltage complementary MISFET, and a voltage of, for example, 5 V or more is applied to the gate electrode of the high withstand voltage complementary MISFET.

  The circuit composed of the low withstand voltage complementary MISFET is, for example, a sense amplifier, a column decoder, or a row decoder, and the circuit composed of the high withstand voltage complementary MISFET is, for example, a booster circuit. Therefore, the figure shows a low breakdown voltage complementary MISFET formation region and a high breakdown voltage complementary MISFET formation region as peripheral circuit regions in addition to the memory array region. Further, the dose amount and the implantation energy of impurities shown below show one preferable embodiment, and are not limited thereto.

Note that the expression “p-type” in this embodiment refers to a p-type conductivity type into which an impurity such as boron (B) or boron fluoride (BF ₂ ) is implanted. Similarly, an n-type conductivity type in which impurities such as phosphorus (P) and arsenic (As) are implanted is expressed as n-type.

  First, as shown in FIG. 1, an element isolation trench 2 is formed in a semiconductor substrate (hereinafter simply referred to as a substrate) 1 made of p-type single crystal silicon. In order to form the element isolation trench 2, for example, a trench is formed on the substrate 1 by dry etching using a silicon nitride film as a mask, and then a silicon oxide film 3 is deposited on the substrate 1 by a CVD method. The external silicon oxide film 3 is removed by a chemical mechanical polishing method.

Next, as shown in FIG. 2, P (phosphorus) ions are implanted into the entire surface of the substrate 1. This ion implantation is performed to form an n-type buried layer for well isolation. The dose amount of P is 1 × 10 ¹³ atom / cm ² and the implantation energy is 1000 keV.

Next, as shown in FIG. 3, a photoresist film 40 is formed on the substrate 1, and P (phosphorus) is ion-implanted into the substrate 1 in the high breakdown voltage p-channel type MISFET formation region using the photoresist film 40 as a mask. To do. The implantation energy of P is set to three types of 500 keV, 200 keV, and 60 keV, and the dose amount is set to 1 × 10 ¹² atom / cm ² . Here, P implanted with energy of 500 keV and 200 keV is for forming an n-type well. Further, P implanted with energy of 60 keV is for adjusting the threshold voltage of the high breakdown voltage p-channel type MISFET.

Next, as shown in FIG. 4, a photoresist film 41 is formed on the substrate 1, and B (boron) is formed on the substrate 1 in the memory array region and the high breakdown voltage n-channel MISFET formation region using the photoresist film 41 as a mask. ) Is ion-implanted. The implantation energy and dose of B are (1) 300 keV, 5 × 10 ¹² atom / cm ² , (2) 150 keV, 3 × 10 ¹² atom / cm ² , (3) 50 keV, 1 × 10 ¹² atom / cm ^2. These are the three types. Here, B implanted with energy of 300 keV and 150 keV is for forming a p-type well. Further, B implanted with an energy of 50 keV is for adjusting the threshold voltage of the memory cell transistor and the high breakdown voltage n-channel MISFET.

Next, as shown in FIG. 5, a photoresist film 42 is formed on the substrate 1, and P is ion-implanted into the substrate 1 in the low breakdown voltage p-channel type MISFET formation region using the photoresist film 42 as a mask. The implantation energy and dose of P are (1) 300 keV, 2 × 10 ¹³ atom / cm ² , (2) 100 keV, 2 × 10 ¹² atom / cm ² , (3) 40 keV, 1 × 10 ¹³ atom / cm ^2. These are the three types. Here, P implanted with energy of 300 keV and 100 keV is for forming an n-type well. Further, P implanted with energy of 40 keV is for adjusting the threshold voltage of the low breakdown voltage p-channel type MISFET.

  That is, in this embodiment, P ion implantation energy performed for adjusting the threshold voltage of the high breakdown voltage p-channel type MISFET is used as the P ion implantation energy performed for adjusting the threshold voltage of the low breakdown voltage p-channel type MISFET. Larger than the ion implantation energy. In other words, the threshold voltage adjustment well (semiconductor region) of the high breakdown voltage p-channel type MISFET is formed at a deeper position from the substrate surface than the threshold voltage adjustment well (semiconductor region) of the low breakdown voltage p-channel type MISFET. Yes. That is, it is formed so that the concentration peak is at a deep position.

Next, as shown in FIG. 6, a photoresist film 43 is formed on the substrate 1, and B and BF ₂ (fluoride) are applied to the substrate 1 in the low breakdown voltage n-channel MISFET formation region using the photoresist film 43 as a mask. Boron) is ion-implanted. The implantation energy and dose amount of B are (1) 200 keV, 2 × 10 ¹³ atom / cm ² and (2) 50 keV, 2 × 10 ¹² atom / cm ² , and the implantation energy and dose amount of BF ₂ are , 60 keV, 2 × 10 ¹³ atom / cm ² . Here, B implanted with an energy of 200 keV is for forming a p-type well. Further, B implanted with an energy of 50 keV and BF ₂ implanted with an energy of 60 keV are for adjusting the threshold voltage of the low breakdown voltage n-channel MISFET.

  The order of ion implantation performed using the above-described four types of photoresist films 40, 41, 42, and 43 as a mask is arbitrary.

  Next, as shown in FIG. 7, the substrate 1 is heat-treated to activate the above-described impurities in the substrate 1, thereby forming the n-type buried layer 4 on the entire surface of the substrate 1. Further, a p-type well 5p is formed in the memory cell region of the substrate 1 and the high breakdown voltage n-channel MISFET formation region, and an n-type well 5n is formed in the high breakdown voltage p-channel MISFET formation region. Further, a p-type well 6p is formed in the low breakdown voltage n-channel MISFET formation region of the substrate 1, and an n-type well 6n is formed in the low breakdown voltage p-channel MISFET formation region. In the present embodiment, in order to facilitate understanding of the invention, the n-type buried layer 4 for well isolation shown in FIG. 2 and the n-type well 5n formed with an implantation energy of 500 keV shown in FIG. 4, the p-type well 5p formed with an implantation energy of 300 keV, the n-type well 6n formed with an implantation energy of 300 keV shown in FIG. 5, and the implantation energy shown in FIG. 6 of 200 keV. A p-type well 6p is shown as a representative. The same applies to the subsequent drawings.

  Next, as shown in FIG. 8, after the surface of the substrate 1 is wet-cleaned, the substrate 1 is thermally oxidized to form gate oxide films on the surfaces of the p-type wells 5p and 6p and the n-type wells 5n and 6n. 7 and 8 are formed. A thin gate oxide film 7 having a thickness of less than 10 nm, for example, about 3 to 4 nm is formed in the low breakdown voltage MISFET formation region, and the film thickness is ensured in the memory array region and the high breakdown voltage MISFET formation region in order to ensure breakdown voltage. A thick gate oxide film 8 having a thickness of 10 nm or more, for example, about 19 nm is formed.

  In order to form the two types of gate oxide films 7 and 8, the substrate 1 is first thermally oxidized to thicken the surfaces of the p-type wells 5p and 6p and the n-type wells 5n and 6n to a thickness of about 18 nm. A gate oxide film 8 is formed. Next, the upper portions of the high breakdown voltage MISFET formation region (p-type well 5p and n-type well 5n) and the memory array region (p-type well 5p) are covered with a photoresist film (not shown), and the low breakdown voltage MISFET formation region The gate oxide film 8 on the surface of the (p-type well 6p and n-type well 6n) is removed by wet etching. Next, after removing the photoresist film, the substrate 1 is thermally oxidized once more, so that a thin gate oxide film 7 of about 3 to 4 nm is formed on the surface of the low breakdown voltage MISFET formation region (p-type well 6p and n-type well 6n). Form.

  Next, as shown in FIG. 9, after depositing an undoped silicon film 9A having a thickness of about 250 nm on the substrate 1 by the CVD method, a film is formed on the upper portion by the CVD method in order to protect the surface of the undoped silicon film 9A. A thin silicon oxide film 11 having a thickness of about 20 nm is deposited.

Next, as shown in FIG. 10, a photoresist film 44 is formed on the silicon oxide film 11, and B (boron) is applied to the undoped silicon film 9A in the p-channel type MISFET formation region using the photoresist film 44 as a mask. By ion implantation, the undoped silicon film 9A in this region is converted into a p-type silicon film 9p. Here, by setting the dose amount of B to 4 × 10 ¹⁵ atoms / cm ² and the implantation energy to 10 keV, the B concentration of the p-type silicon film 9p in the vicinity of the interface with the gate oxide films 7 and 8 is 2 × 10. Control to ²⁰ atom / cm ³ or less.

Next, as shown in FIG. 11, a photoresist film 45 is formed on the silicon oxide film 11, and P (phosphorus) is applied to the undoped silicon film 9A in the n-channel MISFET formation region using the photoresist film 45 as a mask. By ion implantation, the undoped silicon film 9A in this region is changed to an n-type silicon film 9n. The dose amount of P is 4 × 10 ¹⁵ atoms / cm ² and the implantation energy is 20 keV. Note that the order of ion implantation performed using the two types of photoresist films 44 and 45 as a mask is arbitrary.

  Next, as shown in FIG. 12, the silicon oxide film 11, the n-type silicon film 9n, and the p-type silicon film 9p are dry-etched using the photoresist film 46 as a mask, so that the n-type silicon film 9n is formed in the memory array region. A control gate 12 is formed. Further, the gate electrode 13 made of the n-type silicon film 9n and the gate electrode 14 made of the p-type silicon film 9p are formed in the peripheral circuit region.

  Next, as shown in FIG. 13, after the ONO film 15 is formed on the substrate 1, the n-type polycrystalline silicon film 16n deposited by the CVD method on the ONO film 15 is anisotropically etched to control An n-type polycrystalline silicon film 16n is left on both side walls of the gate 12 and the gate electrodes 13 and 14 of the peripheral circuit. The ONO film 15 is an insulating film composed of a three-layer film of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The two-layer silicon oxide film is formed by thermally oxidizing the substrate 1, and the silicon nitride film is formed by a CVD method.

  Next, as shown in FIG. 14, the n-type polycrystalline silicon film 16n is etched by using a photoresist film (hereinafter not shown) covering a part of the memory cell region as a mask, so that the control gate 12 A memory gate 16 made of an n-type polycrystalline silicon film 16n is formed on one side wall. Subsequently, the ONO film 15 exposed on the surface of the substrate 1 is wet-etched with hydrofluoric acid and phosphoric acid, so that the region covered with the memory gate 16 (one side wall of the control gate 12 and the lower part of the memory gate 16 is removed). Only the ONO film 15 is left.

Next, as shown in FIG. 15, an n ⁻ type semiconductor region 17 is formed by ion implantation of P or As (arsenic) into the n channel MISFET formation region in the peripheral circuit region using the photoresist film as a mask. . At this time, the n ⁻ type semiconductor region 17 is formed by ion-implanting P or As into a part of the memory array region. The n ⁻ type semiconductor region 17 in the peripheral circuit region is an extension region for making the n-channel MISFET have an LDD structure, and the n ⁻ type semiconductor region 17 in the memory array region has an LDD structure for the control transistor of the memory cell. This is an extension area.

Next, p ⁻ type semiconductor region 18 is formed by ion-implanting BF ₂ into the p channel type MISFET formation region in the peripheral circuit region using the photoresist film as a mask. The p ⁻ type semiconductor region 18 is an extension region for making the p channel type MISFET into an LDD structure. The ion implantation for forming the n ⁻ type semiconductor region 17 and the ion implantation for forming the p ⁻ type semiconductor region 18 may be performed in the reverse order.

  Next, as shown in FIG. 16, side wall spacers 19 are formed on one side wall of each of the control gate 12 and the memory gate 16 formed in the memory array region. Further, sidewall spacers 19 are formed on both side walls of the gate electrode 13 and the gate electrode 14 in the peripheral circuit region. The side wall spacer 19 is formed by anisotropically etching a silicon oxide film deposited on the substrate 1 by the CVD method.

Next, P or As is ion-implanted into the memory array region and the n-channel MISFET formation region in the peripheral circuit region using the photoresist film as a mask. As a result, an n ⁺ type semiconductor region (source region, drain region) 21 is formed in the memory array region, and the memory cell MC is completed. Further, an n ⁺ type semiconductor region (source region, drain region) 21 is formed in the peripheral circuit region, and a low breakdown voltage n-channel MISFET (Q _LN ) and a high breakdown voltage n-channel MISFET (Q _HN ) are completed.

Next, B is ion-implanted into the p-channel type MISFET formation region in the peripheral circuit region using the photoresist film as a mask. As a result, a p ⁺ type semiconductor region (source region, drain region) 22 is formed in the peripheral circuit region, and a low breakdown voltage p-channel type MISFET (Q _LP ) and a high breakdown voltage p-channel type MISFET (Q _HP ) are completed.

  Next, as shown in FIG. 17, after depositing a silicon nitride film 23 and a silicon oxide film 24 on the substrate 1 by a CVD method, a contact hole 25 is formed in the silicon nitride film 23 and the silicon oxide film 24. Subsequently, after a plug 26 made of a titanium nitride (TiN) film and a tungsten (W) film is buried in the contact hole 25, data made of an aluminum (Al) alloy film is formed on the silicon oxide film 24 in the memory array region. A line DL is formed, and a wiring 27 made of an Al alloy film is formed on the silicon oxide film 24 in the peripheral circuit region. Thereafter, a plurality of wirings are formed in the upper layer of the wirings 27 with an interlayer insulating film interposed therebetween, but illustration thereof is omitted.

As described above, in this embodiment, the ion implantation energy of P, which is used to adjust the threshold voltage of the high breakdown voltage p-channel type MISFET (Q _HP ) constituting the booster circuit, is changed to the low breakdown voltage p channel type MISFET (Q _LP ) is made larger than the ion implantation energy of P to adjust the threshold voltage. Further, the B concentration in the gate electrode 14 of the high breakdown voltage p-channel type MISFET (Q _HP ) is controlled to be 2 × 10 ²⁰ atom / cm ³ or less in the vicinity of the interface with the gate oxide film 8.

Thereby, even if the high breakdown voltage p-channel type MISFET (Q _HP ) is made the surface channel type, the deterioration of the NBT life can be suppressed. The reason for this is as follows. By increasing the energy of channel ion implantation, the hole density of the channel can be lowered and the reaction between the holes and the substrate interface can be suppressed. Further, by setting the interface density to 2 × 10 ²⁰ atoms / cm ³ or less, the gate can be easily depleted and the electric field at the time of gate negative bias can be reduced.

Therefore, the high breakdown voltage p-channel type MISFET (Q _HP ) can be made to be a surface channel type without lowering the reliability, so that the sensitivity to the channel impurity variation becomes dull and the fluctuation of the threshold voltage is reduced. To do. Furthermore, since the short channel characteristics of the high breakdown voltage p-channel type MISFET (Q _HP ) are improved, miniaturization is facilitated.

When the high breakdown voltage p-channel type MISFET (Q _HP ) is a surface channel type, the carrier mobility is lower than that of the buried channel type, and the current is reduced in the MISFET of the same size. Thus, the element can be miniaturized, so that the current of the transistor can be increased as a whole.

(Embodiment 2)
With reference to FIGS. 18 to 26, the method of manufacturing the nonvolatile memory according to the present embodiment will be described in the order of steps. This nonvolatile memory is composed of a memory array and a peripheral circuit. The peripheral circuit is further composed of a circuit composed of a low withstand voltage complementary MISFET, a circuit composed of a medium withstand voltage complementary MISFET, and a high withstand voltage complementary MISFET. It consists of a configured circuit. For example, a voltage of 1.5 V is applied to the gate electrode of the low-voltage complementary MISFET, and a voltage of 3.3 V, for example, is applied to the gate electrode of the medium-voltage complementary MISFET. For example, a voltage of 5 V or more is applied.

  A circuit composed of the low withstand voltage complementary MISFET is, for example, a sense amplifier, a column decoder, a row decoder, or the like. A circuit composed of a medium-voltage complementary MISFET is, for example, an input / output circuit. A circuit composed of the high withstand voltage complementary MISFET is, for example, a booster circuit. This embodiment is the same as the manufacturing process of the first embodiment except that a manufacturing process of a medium-voltage complementary MISFET is added.

First, as shown in FIG. 18, an element isolation trench 2 is formed in the substrate 1 by the same method as in the first embodiment, and then an n-type buried layer for well isolation is formed as shown in FIG. For this purpose, P ions are implanted into the entire surface of the substrate 1. The dose amount of P is 1 × 10 ¹³ atom / cm ² and the implantation energy is 1000 keV.

Next, as shown in FIG. 20, a photoresist film 50 is formed on the substrate 1, and P is ion-implanted into the substrate 1 in the high breakdown voltage p-channel MISFET formation region using the photoresist film 50 as a mask. The implantation energy of P is set to three types of 500 keV, 200 keV, and 60 keV, and the dose amount is set to 1 × 10 ¹² atom / cm ² . Here, P implanted with energy of 500 keV and 200 keV is for forming an n-type well. Further, P implanted with energy of 60 keV is for adjusting the threshold voltage of the high breakdown voltage p-channel type MISFET.

Next, as shown in FIG. 21, a photoresist film 51 is formed on the substrate 1, and B is ion-implanted into the substrate 1 in the high breakdown voltage n-channel MISFET formation region using the photoresist film 51 as a mask. At this time, B ions are also implanted into the substrate 1 in the memory array region (not shown). The implantation energy and dose of B are (1) 300 keV, 5 × 10 ¹² atom / cm ² , (2) 150 keV, 3 × 10 ¹² atom / cm ² , (3) 50 keV, 1 × 10 ¹² atom / cm ^2. These are the three types. Here, B implanted with energy of 300 keV and 150 keV is for forming a p-type well. Further, B implanted with an energy of 50 keV is for adjusting the threshold voltage of the memory cell transistor and the high breakdown voltage n-channel MISFET.

Next, as shown in FIG. 22, a photoresist film 52 is formed on the substrate 1, and the low breakdown voltage p-channel type MISFET formation region and the medium breakdown voltage p-channel type MISFET formation region are formed using the photoresist film 52 as a mask. 1 is ion-implanted with P. The implantation energy and dose of P are (1) 300 keV, 2 × 10 ¹³ atom / cm ² , (2) 100 keV, 2 × 10 ¹² atom / cm ² , (3) 40 keV, 1 × 10 ¹³ atom / cm ^2. These are the three types. Here, P implanted with energy of 300 keV and 100 keV is for forming an n-type well. Further, P implanted with an energy of 40 keV is for adjusting the threshold voltage of the low breakdown voltage p-channel type MISFET and the medium breakdown voltage p-channel type MISFET.

  That is, in the present embodiment, as in the first embodiment, the ion implantation energy of P, which is used to adjust the threshold voltage of the high breakdown voltage p-channel MISFET, is set to the threshold voltage of the low breakdown voltage p-channel MISFET. The ion implantation energy of P used for adjusting the voltage is set larger.

Next, as shown in FIG. 23, a photoresist film 53 is formed on the substrate 1, and the substrate of the low breakdown voltage n-channel type MISFET formation region and the medium breakdown voltage n-channel type MISFET formation region using the photoresist film 53 as a mask. 1 is ion-implanted with B and BF ₂ . The implantation energy and dose amount of B are (1) 200 keV, 2 × 10 ¹³ atom / cm ² and (2) 50 keV, 2 × 10 ¹² atom / cm ² , and the implantation energy and dose amount of BF ₂ are , 60 keV, 2 × 10 ¹³ atom / cm ² . Here, B implanted with an energy of 200 keV is for forming a p-type well. Further, B implanted with an energy of 50 keV and BF ₂ implanted with an energy of 60 keV are for adjusting threshold voltages of the low breakdown voltage n-channel MISFET and the medium breakdown voltage n-channel MISFET.

  The order of ion implantation performed using the four types of photoresist films 50, 51, 52 and 53 as a mask is arbitrary.

  Next, as shown in FIG. 24, the substrate 1 is heat-treated and the impurities described above are activated in the substrate 1, thereby forming the n-type buried layer 4 on the entire surface of the substrate 1. Further, a p-type well 5p is formed in a memory cell region (not shown) and a high breakdown voltage n-channel MISFET formation region of the substrate 1, and an n-type well 5n is formed in the high breakdown voltage p-channel MISFET formation region. Further, a p-type well 6p is formed in the low breakdown voltage n-channel MISFET formation region and the medium breakdown voltage n-channel MISFET formation region of the substrate 1, and n is formed in the low breakdown voltage p-channel MISFET formation region and the medium breakdown voltage p-channel MISFET formation region. A mold well 6n is formed.

  Next, as shown in FIG. 25, after the surface of the substrate 1 is wet-cleaned, the substrate 1 is thermally oxidized to form the gate oxide film 7 on the surfaces of the p-type wells 5p and 6p and the n-type wells 5n and 6n. 8 and 10 are formed. A thin gate oxide film 7 having a film thickness of less than 10 nm, for example, about 2.5 nm is formed in the low breakdown voltage MISFET formation region, and the film thickness is secured in the memory array region and the high breakdown voltage MISFET formation region in order to ensure breakdown voltage. A thick gate oxide film 8 having a thickness of 10 nm or more, for example, about 19 nm is formed. In the medium breakdown voltage MISFET formation region, a gate insulating film 10 having a thickness of less than 10 nm and thicker than the gate oxide film 7, for example, about 6 nm is formed.

  In order to form the three types of gate oxide films 7, 8, and 10, first, the substrate 1 is thermally oxidized to form a film thickness of about 18 nm on the surfaces of the p-type wells 5p and 6p and the n-type wells 5n and 6n. A thick gate oxide film 8 is formed.

  Next, upper portions of the high breakdown voltage MISFET formation region (p-type well 5p and n-type well 5n), the memory array region (p-type well 5p) and the low breakdown voltage MISFET formation region (p-type well 6p and n-type well 6n). Is covered with a photoresist film (not shown), and the gate oxide film 8 on the surface of the medium breakdown voltage MISFET formation region (p-type well 6p and n-type well 6n) is removed by wet etching.

  Next, after removing the photoresist film, the substrate 1 is thermally oxidized to form a gate oxide film 10 having a thickness of about 6 nm on the surface of the medium breakdown voltage MISFET formation region (p-type well 6p and n-type well 6n). To do.

  Next, upper portions of the high breakdown voltage MISFET formation region (p-type well 5p and n-type well 5n), the memory array region (p-type well 5p) and the medium breakdown voltage MISFET formation region (p-type well 6p and n-type well 6n). Is covered with a photoresist film (not shown), and the gate oxide film 8 on the surface of the low breakdown voltage MISFET formation region (p-type well 6p and n-type well 6n) is removed by wet etching.

  Next, after removing the photoresist film, the substrate 1 is thermally oxidized to form a thin gate oxide film 7 of about 2.5 nm on the surface of the low breakdown voltage MISFET formation region (p-type well 6p and n-type well 6n). Form.

  Next, as shown in FIG. 26, a gate electrode 13 made of an n-type silicon film and a gate electrode 14 made of a p-type silicon film are formed in the peripheral circuit region. In addition, a control gate made of an n-type silicon film is formed in a memory array region (not shown). The gate electrodes 13 and 14 and the control gate are formed by forming the gate electrode 13 in the medium breakdown voltage n-channel MISFET formation region (p-type well 6p) and forming the medium breakdown voltage p-channel MISFET formation region (n-type well 6n). Except for forming the gate electrode 14, it is the same as in the first embodiment.

  Thereafter, using the same method as in the first embodiment, six types of MISFETs (low withstand voltage n-channel type MISFET, low withstand voltage p channel type MISFET, medium withstand voltage n channel type MISFET, medium withstand voltage p channel type MISFET are used in the peripheral circuit region. , High breakdown voltage n-channel MISFET and high breakdown voltage p-channel MISFET).

  According to the present embodiment, the same effect as in the first embodiment can be obtained.

(Embodiment 3)
The method for manufacturing the nonvolatile memory according to the present embodiment will be described in the order of steps with reference to FIGS. The present embodiment is the same as the manufacturing process of the first embodiment except that the gate electrode manufacturing method is different.

  First, as shown in FIG. 27, an undoped silicon film 9A having a film thickness of about 250 nm is deposited on the gate oxide films 7 and 8 by the CVD method, and then the upper surface of the undoped silicon film 9A is protected to protect the surface. A thin silicon oxide film 11 having a thickness of about 20 nm is deposited by CVD. The steps so far are the same as the steps shown in FIGS. 1 to 9 of the first embodiment.

  Next, as shown in FIG. 28, a photoresist film 46 is formed on the silicon oxide film 11, and the silicon oxide film 11 and the undoped silicon film 9A are dry-etched using the photoresist film 46 as a mask, thereby providing a memory. A control gate 12 made of an undoped silicon film 9A is formed in the array region. In addition, gate electrodes 13 and 14 made of an undoped silicon film 9A are formed in the peripheral circuit region. The photoresist film 46 has the same pattern as the photoresist film 46 used in the step shown in FIG. 12 of the first embodiment. The control gate 12 and the gate electrodes 13 and 14 obtained here are in an unfinished state since no impurities are introduced.

Next, according to the steps shown in FIGS. 13 to 15 of the first embodiment, the n ⁻ type semiconductor region 17 is formed in the p type wells 5p and 6p, and the p ⁻ type semiconductor region 18 is formed in the n type wells 5n and 6n. Form. A memory gate 16 is formed in the memory array region.

  Next, as shown in FIG. 29, sidewall spacers 19 are formed on both side walls of the gate electrode 13 and the gate electrode 14 in the peripheral circuit region. Further, a sidewall spacer 19 is formed on one side wall of each of the control gate 12 and the memory gate 16 in the memory array region. The side wall spacer 19 is formed by anisotropically etching a silicon oxide film deposited on the substrate 1 by the CVD method.

Next, B is ion-implanted into the p-channel type MISFET formation region in the peripheral circuit region using the photoresist film 47 as a mask. At this time, B is ion-implanted also into the undoped silicon film 9A constituting the gate electrode 14, so that the gate electrode 14 made of a p-type silicon film is completed. Further, a p ⁺ type semiconductor region (source region, drain region) 22 is formed in the peripheral circuit region, and a low breakdown voltage p-channel type MISFET (Q _LP ) and a high breakdown voltage p channel type MISFET (Q _HP ) are completed.

Next, as shown in FIG. 30, P or As is ion-implanted into the n-channel MISFET formation region in the memory array region and the peripheral circuit region using the photoresist film 48 as a mask. Here, the dose is 4 × 10 ¹⁵ atom / cm ² and the concentration of the gate electrode 13 is 2 × 10 ²⁰ atom / cm ³ or less. Thus, n ⁺ -type semiconductor region (source region, drain region) in the memory array region 21 is formed, n ⁺ -type semiconductor region (source region, drain region) in the peripheral circuit region 21 is formed. At this time, since P or As is ion-implanted also into the undoped silicon film 9A constituting the gate electrode 13 and the undoped silicon film 9A constituting the control gate 12, the gate electrode 13 and the control gate 12 made of an n-type silicon film are formed. Complete. Thereby, the memory cell MC, the low breakdown voltage n-channel type MISFET (Q _LN ), and the high breakdown voltage n-channel type MISFET (Q _HN ) are completed. The order of ion implantation performed using the two types of photoresist films 47 and 48 as a mask is arbitrary.

According to the present embodiment, the same effect as in the first embodiment can be obtained. Further, the conductivity type of the gate electrode 13 is changed to n-type by utilizing an ion implantation process for forming the n ⁺ -type semiconductor region (source region, drain region) 21, and the p ⁺ -type semiconductor region (source region, drain region) is formed. Since the conductivity type of the gate electrode 14 is changed to p-type by using the ion implantation process for forming 22, the number of processes and the number of photomasks can be reduced as compared with the first embodiment.

(Embodiment 4)
With reference to FIGS. 31 to 38, a method of manufacturing the nonvolatile memory according to the present embodiment will be described in the order of steps. Although the present embodiment is the same as the first embodiment up to the steps shown in FIGS. 1 to 7, the structure and manufacturing method of the subsequent nonvolatile memory cell are different.

  First, after the steps shown in FIGS. 1 to 7, as shown in FIG. 31, a gate insulating film 61, a charge storage film 62, an insulating film 63, a memory gate electrode 64, a cap of a nonvolatile memory cell are formed in the memory array region. After forming the insulating film 65, an insulating film 66 is formed on the side surface of the memory gate electrode 64. These films are formed by the following method, for example.

First, the substrate 1 is thermally oxidized to form a gate insulating film 61 made of a silicon oxide film having a thickness of about 1.1 nm on the surface thereof, and then a silicon nitride film having a thickness of about 16.5 nm is formed on the gate insulating film 61. A charge storage film 62 is formed. The charge storage film 62 is formed using a CVD method in which silane gas (SiH ₄ ) and ammonia gas (NH ₃ ) are chemically reacted. As another method, it can also be formed by an ALD (Atomic Layer Deposition) method. The charge storage film 62 may be an insulating film other than a silicon nitride film, such as a silicon oxynitride film (SiON), which includes a trap level in the film. It is also possible to form the charge storage film 62 with Si nanodots.

Next, an insulating film 63 made of a silicon oxide film having a thickness of about 3.0 nm is formed on the charge storage film 62. The insulating film 63 can be formed by a CVD method in which silane gas and oxygen gas (O ₂ ) are chemically reacted. Next, an n-type polycrystalline silicon film is formed on the insulating film 63. When forming the n-type polycrystalline silicon film, a conductive impurity such as phosphorus is added. Note that, after the formation of the undoped polycrystalline silicon film, the n-type polycrystalline silicon film may be formed by implanting conductive impurities into the undoped polycrystalline silicon film by using an ion implantation method. Next, a cap insulating film 65 made of a silicon oxide film is formed on the n-type polycrystalline silicon film using a CVD method. The cap insulating film 65 has a function of protecting the memory gate electrode 64 formed in the subsequent process. The cap insulating film 65 may be formed of a laminated film of a silicon oxide film and a silicon nitride film.

  Next, by patterning the plurality of films by dry etching using a photoresist as a mask, a memory gate electrode 64 made of an n-type polycrystalline silicon film is formed, and then the substrate 1 is thermally oxidized to thereby change the memory. An insulating film 66 made of a silicon oxide film is formed on the side surface of the gate electrode 64.

  Next, as shown in FIG. 32, a thin gate oxide film 7 having a film thickness of less than 10 nm, for example, about 3 to 4 nm, is formed in the low breakdown voltage MISFET formation region, and the film thickness is 10 nm or more in the high breakdown voltage MISFET formation region. For example, a thick gate oxide film 8 of about 19 nm is formed. The manufacturing method of the gate oxide films 7 and 8 is the same as that of the first embodiment. Moreover, although the example which uses a silicon oxide film as the gate oxide films 7 and 8 was shown, it is not restricted to this, For example, you may use the film | membrane of a material whose dielectric constant is higher than a silicon oxide, what is called a High-k film. . For example, it may be formed from a film of aluminum oxide, hafnium oxide, zirconium oxide, silicon nitride, or the like. Further, a laminated film in which the high dielectric constant film and the silicon oxide film are laminated may be used.

  Next, as shown in FIG. 33, for example, an undoped silicon film 9A is formed on the substrate 1 as a conductive film. The undoped silicon film 9A can be formed using, for example, a CVD method. Subsequently, in order to protect the surface of the undoped silicon film 9A, a thin silicon oxide film 11 having a thickness of, for example, about 20 nm is deposited as an insulating film thereon by a CVD method.

Next, as shown in FIG. 34, B (boron) is ion-implanted into the undoped silicon film 9A in the p-channel type MISFET formation region using the photoresist film 67 formed on the silicon oxide film 11 as a mask. The undoped silicon film 9A in this region is converted into a p-type silicon film 9p. Here, by setting the dose amount of B to 4 × 10 ¹⁵ atoms / cm ² and the implantation energy to 10 keV, the B concentration of the p-type silicon film 9p in the vicinity of the interface with the gate oxide films 7 and 8 is 2 × 10. Control to ²⁰ atom / cm ³ or less.

Next, as shown in FIG. 35, P (phosphorus) is ion-implanted into the undoped silicon film 9A in the n-channel MISFET formation region using the photoresist film 68 formed on the silicon oxide film 11 as a mask. The undoped silicon film 9A in this region is changed to an n-type silicon film 9n. The dose amount of P is 4 × 10 ¹⁵ atoms / cm ² and the implantation energy is 20 keV. The order of ion implantation performed using the two types of photoresist films 67 and 68 as a mask is arbitrary.

  Next, as shown in FIG. 36, by using the photoresist film 69 formed on the silicon oxide film 11 as a mask, the silicon oxide film 11, the n-type silicon film 9n, and the p-type silicon film 9p are dry-etched, A gate electrode 13 made of an n-type silicon film 9n and a gate electrode 14 made of a p-type silicon film 9p are formed in each of a high breakdown voltage MISFET formation region and a low breakdown voltage MISFET formation region in the peripheral circuit region. Although not shown, the side wall of the memory gate electrode 64 that has already been formed is not sufficiently etched, and an etching residue made of the undoped silicon film 9A may remain. Therefore, in order to remove this etching residue, the peripheral circuit region including the high breakdown voltage MISFET formation region and the low breakdown voltage MISFET formation region is covered with a resist film, and then dry etching is performed again to remove the etching residue. In this manner, the gate electrodes 13 and 14 are formed in the peripheral circuit region.

Next, as shown in FIG. 37, using a well-known photolithography technique and ion implantation method, a low-concentration n-type impurity diffusion region 70, a high-breakdown-voltage MISFET formation region, and a memory-cell formation region are formed in the low-breakdown-voltage MISFET formation region. A low concentration n-type impurity diffusion region 71 is formed. The low-concentration n-type impurity diffusion regions 70 and 71 introduce heat treatment for activating the introduced n-type impurities after introducing n-type impurities such as phosphorus (P) and arsenic (As) into the semiconductor substrate 1. Can be formed. Similarly, by introducing boron (B), boron fluoride (BF ₂ ) or the like into the low breakdown voltage MISFET formation region and the high breakdown voltage MISFET formation region and performing heat treatment for activation, the low concentration p-type impurity diffusion region 72 and 73 are formed.

  Next, as shown in FIG. 38, an insulating film made of a silicon oxide film or the like deposited on the substrate 1 is anisotropically etched to form side wall spacers 74 on the side walls of the gate electrodes 13 and 14 and the memory gate electrode 64. Form. Subsequently, using a well-known photolithography technique and ion implantation method, a high-concentration n-type impurity diffusion region 75 is formed in the memory cell formation region, and a high-concentration n-type is formed in the high breakdown voltage MISFET formation region and the low breakdown voltage MISFET formation region. Impurity diffusion region 76 and high concentration p-type impurity diffusion region 77 are formed.

As described above, when other nonvolatile memory cells are formed in the memory cell formation region, the high breakdown voltage p-channel type MISFET (Q _HP ) is formed on the surface without lowering the reliability as in the first embodiment. Since the channel type can be obtained, the sensitivity to variations in channel impurities becomes dull, and fluctuations in threshold voltage are reduced. Furthermore, since the short channel characteristics of the high breakdown voltage p-channel type MISFET (Q _HP ) are improved, miniaturization can be facilitated.

In addition, since the high breakdown voltage p-channel type MISFET (Q _HP ) is a surface channel type, the carrier mobility is lower than that of the buried channel type, and the current is reduced in the MISFET of the same size. Since the device can be miniaturized by the improvement, the current of the transistor can be increased as a whole.

  Further, in the method for manufacturing the nonvolatile memory cell according to the embodiment of the present application, the method for manufacturing the MISFET in the peripheral circuit region may be formed by another manufacturing method. For example, as in the second and third embodiments, a MISFET in the peripheral circuit region can be formed. In this case, the same effect can be obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above embodiment, the case where the present invention is applied to a nonvolatile memory has been described. However, the present invention is not limited to this, and a semiconductor integrated circuit device in which a high breakdown voltage complementary MISFET and a low breakdown voltage complementary MISFET are formed on the same semiconductor substrate. Can be widely applied in the manufacture of

  The present invention is used in a semiconductor integrated circuit device in which a high breakdown voltage complementary MISFET and a low breakdown voltage complementary MISFET are formed on the same semiconductor substrate.

It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 1. FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 2. FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 3. FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 4. FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 5. FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 7. FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 8. FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 9; FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 11. FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 12; FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 13; FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 14; FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 15; FIG. 17 is a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 16; It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. FIG. 19 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 18; FIG. 20 is a fragmentary cross-sectional view of the semiconductor substrate showing the method of manufacturing the semiconductor integrated circuit device following FIG. 19; FIG. 21 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 20; FIG. 22 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 21. FIG. 23 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 22; FIG. 24 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 23. FIG. 25 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 24. FIG. 26 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 25. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. FIG. 28 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 27; FIG. 29 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 28. FIG. 30 is a main-portion cross-sectional view of the semiconductor substrate, which illustrates the manufacturing method of the semiconductor integrated circuit device following FIG. 29; It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. FIG. 32 is a main-portion cross-sectional view of the semiconductor substrate, which illustrates the manufacturing method of the semiconductor integrated circuit device following FIG. 31; FIG. 33 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 32; FIG. 34 is a main part cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 33; FIG. 35 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 34. FIG. 36 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device following FIG. 35. FIG. 37 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device subsequent to FIG. 36; FIG. 38 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device subsequent to FIG. 37;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation groove 3 Silicon oxide film 4 N type buried layer 5p, 6p P type well 5n, 6n N type well 7, 8 Gate oxide film 9A Undoped silicon film 9p P type silicon film 9n N type silicon film 10 Gate Oxide film 11 Silicon oxide film 12 Control gates 13 and 14 Gate electrode 15 ONO film 16 Memory gate 16n n-type polycrystalline silicon film 17 n ⁻ type semiconductor region (extension region)
18 p ⁻ type semiconductor region (extension region)
19 Side wall spacer 21 n ⁺ type semiconductor region (source region, drain region)
22 p ⁺ type semiconductor region (source region source region)
23 Silicon nitride film 24 Silicon oxide film 25 Contact hole 26 Plug 27 Wiring 40-47, 50-54 Photoresist film 61 Gate insulating film 62 Charge storage film 63 Insulating film 64 Memory gate electrode 65 Cap insulating film 66 Insulating films 67, 68 69 Photoresist film 70 Low-concentration n-type impurity diffusion region 71 Low-concentration n-type impurity diffusion region 72 Low-concentration p-type impurity diffusion region 73 Low-concentration p-type impurity diffusion region 74 Side wall spacer 75 High-concentration n-type impurity diffusion region 76 High concentration n type impurity diffusion region 77 High concentration p type impurity diffusion region DL Data line MC Memory cell Q _HN High breakdown voltage n channel type MISFET
Q _LN low breakdown voltage n-channel MISFET
Q _HP high breakdown voltage p-channel MISFET
Q _LP low breakdown voltage p-channel MISFET

Claims (21)

A low breakdown voltage p-channel MISFET is formed in the first region of the semiconductor substrate, a low breakdown voltage n-channel MISFET is formed in the second region of the semiconductor substrate, and a high breakdown voltage p-channel MISFET is formed in the third region of the semiconductor substrate. Forming a high breakdown voltage n-channel MISFET in a fourth region of the semiconductor substrate;
(A) implanting an n-type impurity for adjusting a threshold voltage of the low breakdown voltage p-channel MISFET into the first region of the semiconductor substrate with a first energy;
(B) A step of ion-implanting an n-type impurity for adjusting a threshold voltage of the high-breakdown-voltage p-channel MISFET with a third energy larger than the first energy into the third region of the semiconductor substrate. When,
(C) forming a first gate insulating film in the first and second regions of the semiconductor substrate;
(D) forming a second gate insulating film thicker than the first gate insulating film in the third and fourth regions of the semiconductor substrate;
(E) forming the low breakdown voltage p-channel MISFET having a gate electrode including a p-type silicon film in a first region of the semiconductor substrate, and having a gate electrode including an n-type silicon film in the second region of the semiconductor substrate; The low breakdown voltage n-channel MISFET is formed, the high breakdown voltage p-channel MISFET having a gate electrode including a p-type silicon film is formed in the third region of the semiconductor substrate, and the n-type is formed in the fourth region of the semiconductor substrate. Forming the high breakdown voltage n-channel MISFET having a gate electrode including a silicon film;
A method for manufacturing a semiconductor integrated circuit device, comprising:   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a voltage of 5 V or more is applied to each of the gate electrodes of the high breakdown voltage p-channel MISFET and the high breakdown voltage n-channel MISFET.   2. The semiconductor integrated circuit device according to claim 1, wherein the oxide equivalent film thickness of the first gate insulating film is less than 10 nm, and the oxide film equivalent film thickness of the second gate insulating film is 10 nm or more. Production method.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the high breakdown voltage p-channel type MISFET and the high breakdown voltage n-channel type MISFET constitute a booster circuit of a nonvolatile memory. The step (e)
(E1) forming an undoped silicon film on the semiconductor substrate;
(E2) converting a p-type silicon film by ion-implanting p-type impurities into the undoped silicon film in the first and third regions of the semiconductor substrate;
(E3) a step of ion-implanting n-type impurities into the undoped silicon films in the second and fourth regions of the semiconductor substrate to convert them into n-type silicon films;
(E4) After the step (e3), by patterning the p-type silicon film and the n-type silicon film using a third photoresist film as a mask, the first and third regions of the semiconductor substrate are formed. Forming a gate electrode including the p-type silicon film, and forming a gate electrode including the n-type silicon film in the second and fourth regions of the semiconductor substrate;
The method of manufacturing a semiconductor integrated circuit device according to claim 1, comprising: The p-type impurity concentration in the p-type silicon film constituting the gate electrode of the high breakdown voltage p-channel type MISFET is set to 2 × 10 ²⁰ atom / cm ³ or less near the interface with the second gate insulating film. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is manufactured. The step (e)
(E1) forming an undoped silicon film on the semiconductor substrate;
(E2) forming a gate electrode including the undoped silicon film in each of the first to fourth regions of the semiconductor substrate by patterning the undoped silicon film;
(E3) After the step (e2), the source and drain of the low breakdown voltage p-channel MISFET are formed in the first region by ion-implanting p-type impurities into the first and third regions of the semiconductor substrate. Forming a source and drain of the high breakdown voltage p-channel MISFET in the third region, and converting the undoped silicon film in the first and third regions into a p-type silicon film;
(E4) After the step (e2), the source and drain of the low breakdown voltage n-channel MISFET are formed in the second region by ion-implanting n-type impurities into the second and fourth regions of the semiconductor substrate. Forming a source and a drain of the high breakdown voltage n-channel MISFET in the fourth region, and converting the undoped silicon film in the second and fourth regions into an n-type silicon film;
The method of manufacturing a semiconductor integrated circuit device according to claim 1, comprising: After the step (a)
(F) a step of ion-implanting a p-type impurity for adjusting a threshold voltage of the low breakdown voltage n-channel MISFET into the second region of the semiconductor substrate with a second energy;
(G) implanting a p-type impurity for adjusting a threshold voltage of the high-breakdown-voltage n-channel MISFET into the fourth region of the semiconductor substrate with a fourth energy;
2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising: A low breakdown voltage p-channel MISFET is formed in the first region of the semiconductor substrate, a low breakdown voltage n-channel MISFET is formed in the second region of the semiconductor substrate, and a high breakdown voltage p-channel MISFET is formed in the third region of the semiconductor substrate. Forming a high breakdown voltage n-channel MISFET in the fourth region of the semiconductor substrate, forming a medium breakdown voltage p-channel MISFET in the fifth region of the semiconductor substrate, and forming a medium breakdown voltage n in the sixth region of the semiconductor substrate; A method of manufacturing a semiconductor integrated circuit device for forming a channel type MISFET,
(A) n-type impurities for adjusting threshold voltages of the low breakdown voltage p-channel type MISFET and the medium breakdown voltage p-channel type MISFET in the first and fifth regions of the semiconductor substrate with the first energy. A step of ion implantation;
(B) A step of ion-implanting an n-type impurity for adjusting a threshold voltage of the high-breakdown-voltage p-channel MISFET with a third energy larger than the first energy into the third region of the semiconductor substrate. When,
(C) forming a first gate insulating film in the first and second regions of the semiconductor substrate;
(D) forming a second gate insulating film thicker than the first gate insulating film in the third and fourth regions of the semiconductor substrate;
(E) forming a third gate insulating film thicker than the first gate insulating film and thinner than the second gate insulating film in the fifth and sixth regions of the semiconductor substrate;
(F) forming the low breakdown voltage p-channel MISFET having a gate electrode including a p-type silicon film in a first region of the semiconductor substrate, and having a gate electrode including an n-type silicon film in the second region of the semiconductor substrate; The low breakdown voltage n-channel MISFET is formed, the high breakdown voltage p-channel MISFET having a gate electrode including a p-type silicon film is formed in the third region of the semiconductor substrate, and the n-type is formed in the fourth region of the semiconductor substrate. Forming the high breakdown voltage n-channel MISFET having a gate electrode including a silicon film; forming the medium breakdown voltage p-channel MISFET having a gate electrode including a p-type silicon film in a fifth region of the semiconductor substrate; Forming the medium withstand voltage n-channel MISFET having a gate electrode including an n-type silicon film in a sixth region of the substrate;
A method for manufacturing a semiconductor integrated circuit device, comprising:   10. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein a voltage of 5 V or more is applied to each of the gate electrodes of the high breakdown voltage p-channel MISFET and the high breakdown voltage n-channel MISFET.   10. The semiconductor integrated circuit according to claim 9, wherein the equivalent oxide thickness of the first and third gate insulating films is less than 10 nm, and the equivalent oxide thickness of the second gate insulating film is 10 nm or more. A method of manufacturing a circuit device.   10. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein the high breakdown voltage p-channel type MISFET and the high breakdown voltage n-channel type MISFET constitute a booster circuit of a nonvolatile memory. The step (f)
(F1) forming an undoped silicon film on the semiconductor substrate;
(F2) a step of ion-implanting p-type impurities into the undoped silicon films in the first, third and fifth regions of the semiconductor substrate to convert them into p-type silicon films;
(F3) a step of ion-implanting n-type impurities into the undoped silicon films in the second, fourth and sixth regions of the semiconductor substrate to convert them into n-type silicon films;
(F4) After the step (f3), by patterning the p-type silicon film and the n-type silicon film using a third photoresist film as a mask, the first, third and third of the semiconductor substrate are patterned. Forming a gate electrode including the p-type silicon film in five regions, and forming a gate electrode including the n-type silicon film in the second, fourth, and sixth regions of the semiconductor substrate;
10. The method of manufacturing a semiconductor integrated circuit device according to claim 9, further comprising: The p-type impurity concentration in the p-type silicon film constituting the gate electrode of the high breakdown voltage p-channel type MISFET is set to 2 × 10 ²⁰ atom / cm ³ or less near the interface with the second gate insulating film. 14. The method of manufacturing a semiconductor integrated circuit device according to claim 9, After the step (a)
(G) p-type impurities for adjusting the threshold voltages of the low withstand voltage n-channel MISFET and the medium withstand voltage n-channel MISFET with the second energy in the second and sixth regions of the semiconductor substrate; A step of ion implantation;
(H) a step of ion-implanting a p-type impurity with a fourth energy for adjusting a threshold voltage of the high-breakdown-voltage n-channel MISFET into the fourth region of the semiconductor substrate;
10. The method of manufacturing a semiconductor integrated circuit device according to claim 9, further comprising: A plurality of first MISFETs formed on a semiconductor substrate;
A semiconductor integrated circuit device having a plurality of second MISFETs driven at a voltage relatively lower than that of the first MISFET,
The plurality of first MISFETs include a p-channel MISFET and an n-channel MISFET,
The plurality of second MISFETs include a p-channel MISFET and an n-channel MISFET,
The p-channel MISFETs of the plurality of first and second MISFETs have a gate electrode containing a p-type impurity,
The n-channel MISFETs of the plurality of first and second MISFETs have gate electrodes containing n-type impurities,
The concentration peak of the semiconductor region for threshold adjustment of the p-channel type MISFETs of the plurality of first MISFETs is formed at a position deeper than the concentration peak of the semiconductor region for threshold adjustment of the p-channel type MISFETs of the plurality of second MISFETs. A semiconductor integrated circuit device.   17. The semiconductor integrated circuit device according to claim 16, wherein a voltage applied to the gate electrode during the operation of the plurality of first MISFETs is 5 V or more.   18. The semiconductor integrated circuit device according to claim 16, wherein a film thickness of the gate insulating film of the plurality of first MISFETs is larger than a film thickness of the gate insulating film of the plurality of second MISFETs.   19. The semiconductor integrated circuit device according to claim 18, wherein the thickness of the gate insulating film of the plurality of first MISFETs is 10 nm or more. The gate electrodes of the plurality of first MISFETs are composed of polycrystalline silicon films having p-type impurities,
The impurity concentration of the polycrystalline silicon film in the vicinity of the interface between the gate insulating film of the first MISFET and the polycrystalline silicon film is 2 × 10 ²⁰ atoms / cm ³ or less. Semiconductor integrated circuit device.   17. The semiconductor integrated circuit device according to claim 16, wherein gate lengths of the gate electrodes of the plurality of first MISFETs are longer than gate lengths of the gate electrodes of the plurality of second MISFETs.

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