JP2005005508A - Semiconductor device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which does not show deterioration of element isolation performance and a method of manufacturing this semiconductor device in higher manufacturing yield. <P>SOLUTION: In a method of manufacturing semiconductor device forming different side wall spacer widths W<SB>1</SB>and W<SB>2</SB>with a high voltage resistance transistor having a first gate electrode 10a and a low voltage resistance transistor having a second gate electrode 10b, etching stopper layers 12, 13 to protect an element isolating insulation film 2 and a side wall spacer forming layer 14 are sequentially laminated on the surface of a semiconductor substrate 1, and the side wall spacer forming layer 14 is etched to respectively form a first side wall spacer remaining a part of the side wall spacer forming layer 14 to the side surfaces of the first gate electrode 10a and the second gate electrode 10b. Moreover, the first side wall spacer in the side of the second gate electrode 10b is removed by the etching process, and the etching stopper layers 12, 13 are removed from the surface of the semiconductor surface 1 with the etching process. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, a semiconductor device in which a high-voltage driving circuit and a low-voltage driving circuit are mixedly mounted on the same chip, a manufacturing method thereof, and a semiconductor device in which a nonvolatile semiconductor memory cell array is integrated And a manufacturing method thereof.
[0002]
[Prior art]
In recent years, there has been an increasing need for a semiconductor integrated circuit in which a logic circuit that is driven at a high speed is mounted on the same chip together with a nonvolatile memory cell array to increase added value. In this type of semiconductor device, as a peripheral circuit of the memory cell array, a high breakdown voltage transistor that constitutes a drive circuit that handles a high voltage required for driving a memory cell and a logic circuit that operates at a low voltage at high speed are constituted. A low voltage transistor circuit is used.
The high voltage transistor is used to generate and transfer a high voltage of several tens of volts, such as programming / erasing, but as a nonvolatile memory, it is necessary to ensure the reliability of error-free programming / erasing over tens of thousands of times. Therefore, it is necessary to sufficiently ensure the junction breakdown voltage of a high breakdown voltage transistor that handles a high voltage.
[0003]
As described above, as a technique for sufficiently ensuring the junction withstand voltage of the high voltage transistor, a method is disclosed in which the side wall spacer is separately formed into a structure in which the side wall spacer width of the high voltage transistor is wider than the side wall spacer width of the low voltage transistor. (For example, refer to Patent Document 1).
[0004]
[Patent Document 1]
JP 2001-93984 A
[0005]
The manufacturing process of the conventional semiconductor device disclosed in Patent Document 1 will be briefly described with reference to FIGS. 21 to 24, (a) shows the high voltage transistor side, and (b) shows the low voltage transistor side.
First, as shown in FIG. 21, a plurality of element isolation insulating films 102, an N well 103 and a P well 104 in a high breakdown voltage transistor formation region A, and an N well layer 118 and a P well layer 119 in a low voltage transistor formation region B are provided. Between the element isolation insulating film 102 on the surface of the semiconductor substrate 101, a gate insulating film 108 and a gate electrode 110a for a high voltage transistor, and a gate insulating film 109 and a gate electrode 110b for a low voltage transistor are formed.
[0006]
Next, as shown in FIG. 22, LDD (Lightly Doped Drain) is selectively implanted into the high breakdown voltage transistor formation region A and the low voltage transistor formation region B using the gate electrodes 110a and 110b as masks. ) Regions 111 and 120 are formed.
Subsequently, as shown in FIG. 23, a first insulating film 112 for a sidewall spacer made of a silicon oxide film, a silicon nitride film, or the like is formed, and the insulating film 112 in the low voltage transistor formation region B is removed, The insulating film 112 is left only in the withstand voltage transistor region A. Here, for partial removal of the first insulating film 112 in the low-voltage transistor formation region B, a photoresist 115 having an opening only in the low-voltage transistor formation region B is formed, and this is used as a mask in the middle of the insulating film 112. Even if anisotropic etching is used, the underlying element isolation insulating film can be obtained by adopting a method of removing by performing dry etching after wet etching until a dry etching or a method using a silicon nitride film or a silicon oxynitride film as the insulating film 112 In this way, the etching is not excessively etched.
[0007]
Next, a second insulating film 113 is deposited on the entire surface of the semiconductor substrate 101 and etched back on the entire surface, so that the high breakdown voltage transistor formation region A and the low voltage transistor region B are different as shown in FIG. A side wall spacer having a width is formed. Thereafter, high concentration impurity implantation for source / drain formation is performed using each gate electrode 110a, 110b and each sidewall spacer as a mask. Thereafter, although not shown, the surface of the semiconductor substrate 101 is salicided, an insulating film is formed on the entire surface by a method such as CVD, a contact hole is opened, a conductive film is buried therein, and a desired electrode is connected to form a high breakdown voltage. A semiconductor device including a transistor and a low voltage transistor is obtained.
[0008]
In such a conventional semiconductor device manufacturing method, in the high breakdown voltage transistor, the low concentration diffusion layer (LDD) is deeply diffused and at the same time, the high concentration diffusion layer (source / drain) and the tip of the low concentration diffusion layer are formed. The distance is large, and the depletion layer is easy to extend, so that the junction breakdown voltage is sufficiently secured. On the other hand, in a low-voltage transistor, a high-performance logic transistor in which drive current loss and deterioration of short channel characteristics are suppressed by a shallow LDD layer can be formed.
[0009]
[Problems to be solved by the invention]
However, when the nonvolatile semiconductor memory device and the low voltage logic circuit are mixedly mounted in one chip by the conventional manufacturing method, the first insulating film (side wall spacer) in the low voltage transistor formation region B is removed. Since there is no stopper film or the like that protects the element isolation insulating film 102, it is actually difficult to control etching stop with the element isolation insulating film 102. In actual manufacturing processes, the element isolation insulating film 102 is excessively etched. As a result, it has been a problem that the element isolation performance is deteriorated.
Further, in the low voltage transistor, as in the high voltage transistor, when the LDD implantation for forming the low concentration region is performed after the formation of the gate electrode 110b, impurities are diffused immediately below the gate in the subsequent heat treatment process such as the formation of the sidewall spacer. As a result, the concentration of the transistor is reduced, resulting in an increase in the short channel effect and deterioration of transistor performance such as insufficient driving current, which hinders miniaturization of the transistor. On the other hand, it is conceivable to perform LDD implantation while leaving the first insulating film (sidewall spacer) in the low-voltage transistor formation region B. In this case, however, the low-concentration diffusion region remains just below the channel even after the subsequent heat treatment. As a result, the effective channel length increases, resulting in an increase in threshold voltage and a decrease in the current drive capability of the transistor, making it impossible to obtain a desired transistor.
[0010]
One of the main objects of the present invention is to provide a semiconductor device in which the element isolation performance is not deteriorated and a manufacturing method capable of manufacturing the semiconductor device with a high yield.
[0011]
[Means for Solving the Problems]
Thus, according to the present invention, in a manufacturing method of manufacturing a semiconductor device including a high voltage transistor and a low voltage transistor having different sidewall spacer widths between element isolation insulating films on the surface of a semiconductor substrate,
A first gate insulating film and a first gate electrode for a high breakdown voltage transistor are formed in a high breakdown voltage transistor formation region on the surface of the semiconductor substrate, and a low voltage transistor first region is formed in the low voltage transistor formation region on the surface of the semiconductor substrate. After the step (a) of forming the two-gate insulating film and the second gate electrode,
A step (b) of sequentially stacking an etching stopper layer and a sidewall spacer forming layer for protecting the element isolation insulating film on the surface of the semiconductor substrate;
Etching the sidewall spacer forming layer to form first sidewall spacers each having a part of the sidewall spacer forming layer remaining on each side surface of the first gate electrode and the second gate electrode. (C),
Removing the first sidewall spacer on the second gate electrode side by etching (d);
And a step (e) of removing the etching stopper layer from the surface of the semiconductor substrate by etching.
[0012]
According to the present invention, when manufacturing a semiconductor device in which a high voltage drive circuit and a low voltage drive circuit are mixedly mounted on the same chip, the underlying element isolation insulating film is not excessively etched by using the etching stopper film. Therefore, there is no generation of defects and deterioration of element isolation performance, and the semiconductor device can be easily manufactured with a good yield. Also, after removing the sidewall spacer once and performing high-temperature heat treatment such as CVD process, LDD implantation is performed in a self-aligned manner with the gate electrode of the low-voltage transistor. LDD implantation and heat treatment can be performed. In particular, in a low-voltage transistor, a transistor having a fine gate length in which the short channel effect is suppressed can be manufactured without being affected by the gate side wall or the heat treatment.
[0013]
In the present invention, the semiconductor substrate is not particularly limited as long as it is a semiconductor substrate on which a semiconductor device is usually manufactured. For example, a semiconductor substrate such as silicon or germanium, various compound semiconductors such as SiC, GaAs, or InGaAs are various. Can be mentioned. Of these, a silicon substrate is preferable.
The element isolation insulating film provided on the semiconductor substrate is not particularly limited as long as it is an element isolation insulating film normally provided on the semiconductor substrate. For example, there are various silicon oxide films, silicon nitride films, silicon oxynitride films, and the like. Can be mentioned.
[0014]
According to the method of manufacturing a semiconductor device of the present invention, the semiconductor device is formed in the high breakdown voltage transistor formation region in the semiconductor substrate between the steps (a) and (b) or immediately after the formation of the etching stopper layer in the step (b). A step of forming a first LDD region by introducing an impurity having a conductivity type opposite to that of the substrate;
Furthermore, after step (e)
(F) forming a second LDD region by selectively introducing an impurity having a conductivity type opposite to that of the semiconductor substrate into the low-voltage transistor formation region in the semiconductor substrate;
Forming a new sidewall film on each of the first gate electrode and the second gate electrode, and forming a second sidewall spacer having a different sidewall spacer width on each of the first gate electrode and the second gate electrode (g); When,
A step (h) of forming a source / drain in the high breakdown voltage transistor formation region and the low voltage transistor formation region can be included.
[0015]
In addition, according to the method for manufacturing a semiconductor device of the present invention, a step of forming a nonvolatile memory cell may be included between step (c) and step (f). A high-value-added semiconductor device in which a high-voltage drive circuit and a low-voltage drive circuit as a circuit are mixedly mounted on the same chip can be manufactured.
[0016]
As the method for manufacturing a semiconductor device of the present invention, the following methods (1), (2), and (3) can be selected.
(1) In step (c), a first etching stopper layer, a second etching stopper layer, and a sidewall spacer forming layer are sequentially deposited on the surface of the semiconductor substrate, and the surface of the second etching stopper layer is exposed. The sidewall spacer forming layer is anisotropically etched until a first sidewall film made of the first etching stopper layer and a second etching stopper layer are formed on each of the first gate electrode and the second gate electrode. Forming a first sidewall spacer formed by laminating a second sidewall film made of and a third sidewall film in which a part of the sidewall spacer forming layer remains,
Thereafter, in the step (d), using the photoresist having an opening in the low voltage transistor region as a mask, the third sidewall film in the low voltage transistor formation region is removed by wet etching in the first stage,
Thereafter, in step (e), the photoresist is removed, and the second etching wet layer using an etchant different from the etchant of the first wet etching is used as the second etching stopper layer in the low voltage transistor formation region. Then, the first etching stopper layer on the surface of the semiconductor substrate is removed by anisotropic etching.
In this case, for example, in the step (b), the first etching stopper layer and the first sidewall spacer forming layer are formed of a silicon oxide film, and the second etching stopper layer is formed of a silicon nitride film. ,
In the step (d), the third sidewall film is wet etched with an etchant containing hydrofluoric acid,
A specific example in which the second etching stopper layer is wet etched with an etchant containing phosphoric acid in the step (e) can be given.
However, the present invention is not limited to this, and at least adjacent layers of the first etching stopper layer, the second etching stopper layer, and the sidewall spacer forming layer that are stacked in order from the substrate are insulating films having different etching rates. I just need it. For example, the first etching stopper layer and the first sidewall spacer forming layer may be formed of a silicon nitride film, and the second etching stopper layer may be formed of a silicon oxide film.
[0017]
(2) In step (c), a first etching stopper layer, a second etching stopper layer, and a sidewall spacer forming layer are sequentially deposited on the surface of the semiconductor substrate, and the surface of the second etching stopper layer is exposed. The sidewall spacer forming layer is anisotropically etched until a first sidewall film made of the first etching stopper layer and a second etching stopper layer are formed on each of the first gate electrode and the second gate electrode. Forming a first sidewall spacer formed by laminating a second sidewall film made of and a third sidewall film in which a part of the sidewall spacer forming layer remains,
Then, before performing the step (d), a silicon oxide layer is formed on the entire surface of the semiconductor substrate,
In step (d), the silicon oxide layer and the third sidewall film on the low voltage transistor formation region side are removed by wet etching in the first stage using a photoresist having an opening in the low voltage transistor region as a mask. ,
Thereafter, in step (e), the photoresist is removed, and the second etching wet layer using an etchant different from the etchant of the first wet etching is used as the second etching stopper layer in the low voltage transistor formation region. Then, the silicon oxide layer, the second etching stopper layer, and the first etching stopper layer on the surface of the semiconductor substrate on the high breakdown voltage transistor forming region side are respectively removed by anisotropic etching.
In this case, for example, in the step (b), the first etching stopper layer and the first sidewall spacer forming layer are formed of a silicon oxide film, and the second etching stopper layer is formed of a silicon nitride film. ,
In the step (d), the silicon oxide layer and the third sidewall film are wet etched with an etchant containing hydrofluoric acid,
A specific example in which the second etching stopper layer is wet etched with an etchant containing phosphoric acid in the step (e) can be given.
However, the present invention is not limited to this, and at least adjacent layers of the first etching stopper layer, the second etching stopper layer, and the sidewall spacer forming layer that are stacked in order from the substrate are insulating films having different etching rates. I just need it. For example, the first etching stopper layer and the first sidewall spacer forming layer may be formed of a silicon nitride film, and the second etching stopper layer may be formed of a silicon oxide film. Before performing e), the silicon oxide layer formed on the entire surface of the semiconductor substrate may be replaced with a silicon nitride layer.
[0018]
(3) In step (c), an etching stopper layer and a sidewall spacer forming layer are sequentially deposited on the semiconductor substrate, and the sidewall spacer forming layer is anisotropically etched until the surface of the etching stopper layer is exposed. Each of the first gate electrode and the second gate electrode is formed by laminating a first sidewall film made of an etching stopper layer and a second sidewall film in which a part of the sidewall spacer forming layer remains. Forming a first sidewall spacer;
Then, before performing the step (d), a silicon oxide layer is formed on the entire surface of the semiconductor substrate,
In step (d), using the photoresist having an opening in the low voltage transistor region as a mask, the silicon oxide layer on the low voltage transistor formation region side is removed by first-stage wet etching with the first material, and the photoresist is formed. Then, the second sidewall film in the low voltage transistor formation region is removed by a second-stage wet etching using an etchant different from the etchant of the first-stage wet etching,
Thereafter, in step (e), the silicon oxide layer, the etching stopper layer on the high breakdown voltage transistor forming region side, and the etching stopper layer on the surface of the semiconductor substrate are respectively removed by anisotropic etching.
In this case, for example, in the step (b), the etching stopper layer is formed of a silicon oxide film, and the sidewall spacer forming layer is formed of a silicon nitride film,
In the step (d), a specific example can be given in which wet etching of the silicon oxide layer is performed with an etchant containing hydrofluoric acid and wet etching of the second sidewall film is performed with an etchant containing phosphoric acid.
Note that the present invention is not limited to this, and it is only necessary that the etching stopper layer and the sidewall spacer forming layer stacked in order from the substrate are insulating films having different etching rates. For example, the etching stopper may be formed of a silicon nitride film, and the sidewall spacer forming layer may be formed of a silicon oxide film. In this case, the etching stopper is formed on the entire surface of the semiconductor substrate before performing the step (e). The silicon oxide layer may be replaced with a silicon nitride layer.
[0019]
According to another aspect of the present invention, a plurality of high breakdown voltage transistors and a plurality of low voltage transistors each having sidewall spacers having different sidewall spacer widths are provided between the transistors on the surface of the semiconductor substrate. Element isolation insulating film,
The side wall spacer of the high breakdown voltage transistor has a total of 4 sidewall films on which the etching stopper layer remains and sidewall film on which the sidewall spacer formation layer remains on the side surface of the first gate electrode for the high breakdown voltage transistor. Layered or layered,
The side wall spacer of the low voltage transistor includes a side wall film where the etching stopper layer remains and a side wall film where another side wall spacer forming layer remains on the side surface of the second gate electrode for the low voltage transistor. A semiconductor device having a structure in which two layers are stacked together can be provided.
[0020]
In the semiconductor device of the present invention having the above structure, the high withstand voltage driving circuit and the low voltage driving circuit are mixedly mounted on the same chip, and the underlying element isolation insulating film is protected by the etching stopper film from etching during manufacturing, and the element isolation performance Is an improvement. In addition, this semiconductor device has a structure in which the width of the side wall spacer is made different for transistors with different breakdown voltage specifications, so that the breakdown voltage performance is further increased for high voltage transistors, and the parasitic resistance is reduced for low voltage transistors, thus ensuring a high drive current. In addition, the element can be miniaturized. Specifically, in a high breakdown voltage transistor, a junction breakdown voltage of 10 to 15 V is obtained, a breakdown voltage decrease of 9 V or less does not appear, and a high breakdown voltage can be stably achieved. In addition, a junction voltage of 4 to 7 V can be stably obtained even in a low voltage transistor, and a high driving current can be secured.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below in detail with reference to the drawings. The present invention is not limited to the embodiment.
[0022]
[Embodiment 1]
FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment of the present invention, and FIGS. 2 to 10 are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the first embodiment. 1 to 10, (a) shows the high breakdown voltage transistor formation region side, and (b) shows the low voltage transistor formation region side.
[0023]
The semiconductor device of the first embodiment includes a high voltage transistor shown in FIG. 1A and a low voltage transistor (high speed) shown in FIG. 1B on the surface of a P type semiconductor substrate (in this case, a P type silicon substrate). It is suitable for a mixed device in which a logic circuit) is mixed. The present invention is not limited to this, and can be applied to a nonvolatile memory embedded device such as a flash memory.
[0024]
The high breakdown voltage transistor shown in FIG. 1A has a first sidewall film 12 made of, for example, a silicon oxide film having a thickness of 5 nm from the side where the sidewall spacer of the gate electrode 10a is closer to the side surface of the gate electrode 10a, A second sidewall film 13 made of a silicon nitride film having a thickness of 15 nm, a third sidewall film 14 made of a silicon oxide film having a thickness of 100 nm, and a fourth sidewall film 21 made of a silicon oxide film having a thickness of 100 nm are formed. Stacked in order, total sidewall width (sidewall spacer width) W ₁ Is 220 nm. The first sidewall film 12 and the second sidewall film 13 are formed by remaining an etching stopper layer that protects the element isolation insulating film 2 during manufacturing.
[0025]
In the low voltage transistor shown in FIG. 1B, the side wall spacer of the gate electrode 10b is closer to the side surface of the gate electrode 10b, and the first sidewall film 12 made of, for example, a silicon oxide film having a thickness of 5 nm. , A fourth sidewall film 21 made of a silicon oxide film having a thickness of 100 nm is sequentially laminated, and a total sidewall width (sidewall spacer width) W ₂ Is 105 nm. Note that the first sidewall film 12 is a film in which an etching stopper layer for protecting the element isolation insulating film 2 remains at the time of manufacture.
[0026]
In the semiconductor device according to the first embodiment configured as described above, the high breakdown voltage transistor includes the sidewall width W of the sidewall spacer. ₁ Therefore, the distance from the high-concentration diffusion layer 22 below the sidewall spacer to the tip of the low-concentration diffusion layer 11 below the sidewall spacer has a long and gentle impurity profile, and the junction breakdown voltage is degraded. There is no structure. On the other hand, the low voltage transistor has a fine gate length and a relatively narrow sidewall spacer width W. ₂ Therefore, the area of the low-voltage transistor region can be reduced, and the low-concentration diffusion layer 20 can be shortened due to the thin fourth side wall film 21, so that parasitic resistance is suppressed and current drive capability is reduced. Nor.
[0027]
Next, a manufacturing method for manufacturing the semiconductor device shown in FIG. 1 will be described using the cross-sectional views of FIGS.
As shown in FIG. 2, the semiconductor substrate includes an element isolation insulating film 2 and an N well layer 3 and a P well layer 4 in a high breakdown voltage transistor formation region A, and an N well layer 18 and a P well layer in a low voltage transistor formation region B. A P-type semiconductor substrate (P-type silicon substrate) 1 having 19 is used. The N-well layer 3 and the P-well layer 4 on the high voltage transistor side are thinner and deeper than the N-well layer 18 and the P-well layer 19 on the low-voltage transistor side.
[0028]
Step (a): First, as shown in FIG. 2, a gate oxide film 8 is formed on the high breakdown voltage transistor formation region side and a gate oxide film 9 is formed on the low voltage transistor formation region side of the surface of the P-type semiconductor substrate 1, respectively. Thereafter, polysilicon 10 is deposited on each of the gate oxide films 8 and 9. Subsequently, as shown in FIG. 3, the polysilicon 10 and the gate oxide film 8 in a region excluding a predetermined position in the high breakdown voltage transistor formation region A are removed to form the gate electrode 10 a, and the low voltage transistor formation region B The gate electrode 10b is formed by removing the polysilicon 10 and the gate oxide film 9 in the region excluding the predetermined position. The polysilicon 10 and the gate oxide films 8 and 9 can be removed by etching using a photoresist as a mask.
[0029]
Next, as shown in FIG. 4, desired ion implantation is performed in a self-aligned manner to form a low concentration diffusion region to the gate electrode 10a in the high breakdown voltage transistor formation region. Specifically, in the NMOS transistor, for example, phosphorus (31P +) is ion-implanted in the order of 1E13 with energy of 50 to 70 KeV perpendicular to the semiconductor substrate 1, and in the PMOS transistor, for example, boron (11B +) is implanted. Ion implantation of about 1E13 order is performed perpendicularly to the semiconductor substrate 1 with energy of 20 to 30 KeV to form a first LDD region that becomes the low concentration diffusion layer 11 of the high breakdown voltage transistor.
[0030]
Step (b): Next, as shown in FIG. 5, as a first etching stopper layer (first sidewall film) 12 for protecting the element isolation insulating film 2 over the entire surface of the semiconductor substrate 1, for example, silicon oxide The film is 5 nm, the silicon nitride film is 15 nm as the second etching stopper layer (second sidewall film) 13 having a selectivity different from that of the etching stopper layer, and the silicon is formed as the sidewall spacer forming layer (third sidewall film) 14. An oxide film is sequentially deposited to 100 nm. In forming these layers 12, 13, and 14, for example, for the first etching stopper layer 12, the surface of the semiconductor substrate 1 is oxidized to form a silicon oxide film, and the second etching stopper layer 13 and the sidewall spacer are formed. As for the formation layer 14, a silicon nitride film and a silicon oxide film can be deposited by LPCVD. The ion implantation for forming the low-concentration diffusion layer 11 for the high breakdown voltage transistor is not limited to before the formation of the first etching stopper layer 12, but after the formation of the first etching stopper layer 12 (second It may be performed before the formation of the etching stopper layer 13.
[0031]
Step (c): Next, as shown in FIG. 6, only the sidewall spacer forming layer 14 made of a silicon oxide film is anisotropically etched (in this case, for example, C) until the etching stopper layer 13 is exposed. ₄ F ₈ The entire surface is etched back by dry etching using a mixed gas of Ar and Ar), and a part of the sidewall spacer forming layer 14 remains on the side surfaces of the gate electrodes 10a and 10b on the high voltage transistor side and the low voltage transistor side. To form a first sidewall spacer. That is, the first sidewall spacer is formed by sequentially laminating the first sidewall film 12, the second sidewall film 13, and the third sidewall film 14 on the side surfaces of the gate electrodes 10a and 10b. Yes. In the anisotropic etching, the element isolation insulating film 2 is protected by the second etching stopper layer 13 made of a silicon nitride film.
[0032]
Step (d): Next, as shown in FIG. 7, a photoresist 16 having an opening only on the low voltage transistor formation region side (FIG. 7 (b)) is formed on the surface of the semiconductor substrate 1, and the low voltage transistor is formed. The third sidewall film 14 made of the silicon oxide film of the first sidewall spacer formed on the side surface of the gate electrode 10b in the formation region is removed by first-stage wet etching. The third sidewall film 14 made of the silicon oxide film is removed by wet etching using, for example, an etchant containing hydrofluoric acid (HF). This wet etchant, hydrofluoric acid, has high selectivity with respect to the second etching stopper layer (second sidewall film) 13 made of a silicon nitride film, and the film of the second etching stopper layer 13 Reduction can be minimized. Therefore, there is no problem that hydrofluoric acid breaks through the second etching stopper layer 13 and pinholes are generated in the element isolation insulating film 2, so that a high manufacturing yield can be obtained.
[0033]
Step (e): Thereafter, as shown in FIG. 8, the photoresist 16 is removed with a resist removing solution, and a second etching stopper layer (second sidewall film) 13 made of a silicon nitride film is formed in the second stage. This is removed by wet etching. The removal of the second etching stopper layer 13 made of this silicon nitride film is performed by, for example, phosphoric acid (H ₃ PO ₄ Wet etching using an etchant containing This wet etchant phosphoric acid has a high selectivity with respect to the first etching stopper layer 12 made of a silicon oxide film, and suppresses the reduction of the film thickness of the first etching stopper layer 12 to a necessary minimum. be able to. That is, the first etching stopper layer 12 functions as a stopper film in the second-stage wet etching. Therefore, since phosphoric acid does not break through the stopper film and attack the semiconductor substrate 1, a high manufacturing yield can be obtained.
[0034]
Next, as shown in FIG. 9, the first etching stopper layer 12 made of the silicon oxide film remaining on the entire surface of the semiconductor substrate 1 is subjected to anisotropic etching (in this case, for example, a mixed gas of CH 2 F 2 and Ar, etc. Is removed by dry etching). The removal of the first etching stopper layer 12 made of a silicon oxide film is not limited to this time, and may be performed until the semiconductor substrate 1 and the gate electrodes 10a and 10b are salicided.
[0035]
Step (f): Next, as shown in FIG. 10, desired ion implantation is selectively performed in a self-aligned manner with respect to the gate electrode 10b in the low voltage transistor formation region, and the low concentration diffusion layer of the low voltage transistor is formed. A second LDD region to be 20 is formed. Although not shown, LDD implantation in the low voltage transistor formation region is performed after forming a photoresist having an opening in each of the NMOS / PMOS. Specifically, in an NMOS transistor, for example, arsenic (75As +) is ion-implanted to the order of 1E14 with an energy of 10 KeV to form an LDD region. In the PMOS transistor, for example, boron difluoride (49BF2 +) is ion-implanted to the order of 1E14 with an energy of 10 KeV to form an LDD. In addition, in both NMOS / PMOS, Halo implantation for suppressing the short channel effect may be performed simultaneously. At this time, the LDD implantation of the low voltage transistor is performed in a self-aligned manner with the gate electrode after performing a high temperature heat treatment such as a CVD process. Since it is not affected by spacers or heat treatment, the LDD can be easily controlled, and a transistor having a fine gate length in which the short channel effect is suppressed can be manufactured.
[0036]
Step (g): Next, a silicon oxide film having a thickness of, for example, 100 nm is deposited on the semiconductor substrate 1 in the state shown in FIG. 10, and then selective anisotropic etching is performed to thereby form the first gate electrode. A fourth sidewall film 21 is formed (remaining) on each side surface of 10a and the second gate electrode 10b, and as shown in FIG. 11, the side wall spacer width is formed on the first gate electrode 10a and the second gate electrode 10b. Second side wall spacers having different sizes are formed. The fourth sidewall film 21 is not limited to a silicon oxide film as long as it is an insulating film, and may be a silicon nitride film, a silicon nitride oxide film, or a laminated film thereof.
[0037]
Step (h): Thereafter, diffusion for ion implantation and activation is performed in a self-aligned manner using the side wall spacers of the gate electrodes 10a and 10b and the gate electrodes 10a and 10b as masks, and a high breakdown voltage transistor forming region and a low A high concentration source / drain diffusion layer 22 is formed in each voltage transistor region. As a result, the state shown in FIG. 11 is obtained.
[0038]
Thereafter, although not shown, after the surface of the semiconductor substrate 1 and the surfaces of the gate electrodes 10a and 10b are salicided, the entire surface of the semiconductor substrate 1 is covered with an insulating film by CVD or the like, and then a contact hole is opened. A semiconductor device shown in FIG. 1 can be obtained by embedding a conductive film therein and connecting desired electrodes.
[0039]
In the semiconductor device according to the first embodiment manufactured as described above, a junction breakdown voltage of 10 to 15 V is obtained in a high breakdown voltage transistor, and a breakdown voltage decrease of 9 V or less does not appear, and the breakdown voltage can be stably increased. It was. Moreover, in the low voltage transistor, a junction withstand voltage of 4 to 7 V was stably obtained, and a high driving current could be secured.
[0040]
[Embodiment 2]
The semiconductor device shown in FIG. 1 can also be manufactured by the manufacturing method of Embodiment 2 described below. Hereinafter, a method for manufacturing the semiconductor device of the second embodiment will be described mainly with reference to FIGS. 12-14, the same code | symbol is attached | subjected to the element same as Embodiment 1, and the description is abbreviate | omitted.
[0041]
In the manufacturing method of the second embodiment, first, the steps (a) to (c) described in the first embodiment with reference to FIGS. 2 to 6 are similarly performed, and the gate electrode 10a in the high breakdown voltage transistor forming region and the low A first sidewall spacer is formed on each of the gate electrodes 10b in the voltage transistor formation region.
[0042]
Next, before the step (d-2), a silicon oxide layer 15 is formed on the entire surface of the semiconductor substrate 1 in the state of FIG.
[0043]
Step (d-2): Next, as shown in FIG. 12, a photoresist 16 having an opening only on the low voltage transistor formation region side is formed, and the silicon oxide layer 15 and the gate electrode 10b on the low voltage transistor formation region side are formed. The third sidewall film 14 formed on the side surfaces of the first side is removed by wet etching in the first stage using, for example, an etchant containing hydrofluoric acid (HF). This wet etchant containing hydrofluoric acid (HF) has high selectivity with respect to the second etching stopper layer 13 made of a silicon nitride film, and it is necessary to reduce the thickness of the second etching stopper layer 13. Can be minimized. Therefore, there is no problem that the etchant breaks through the second etching stopper layer 13 and pinholes are generated in the element isolation insulating film 2, so that a high manufacturing yield can be obtained.
[0044]
Step (e-2): Thereafter, as shown in FIG. 13, the photoresist 16 is removed, and then, for example, phosphoric acid (H ₃ PO ₄ ) -Containing wet etching is performed using an etchant containing). At this time, the silicon oxide layer functions as a stopper film on the high breakdown voltage transistor formation region side, and only the second etching stopper layer 13 made of the silicon nitride film on the low voltage transistor formation region side is removed. This wet etchant has high selectivity with respect to the silicon oxide layer 15 on the high breakdown voltage transistor formation region side and the first sidewall film 12 on the low voltage transistor formation region side. The film loss of the etching stopper layer 12 can be minimized. Therefore, the etchant breaks through the silicon oxide layer 15 and the first etching stopper layer 12 as a stopper film to attack the semiconductor substrate 1, and silicon nitride on the high breakdown voltage transistor formation region side (FIG. 13A). Since there is no loss of the second etching stopper layer 13 made of a film, a high production yield can be obtained.
[0045]
Next, the silicon oxide layer 15 remaining on the high breakdown voltage transistor forming region side and the first etching stopper layer 12 on the low voltage transistor forming region side in the semiconductor substrate 1 in the state of FIG. (For example, CH ₂ F ₂ And dry etching using a mixed gas of Ar and Ar). Thereafter, anisotropic etching (for example, CH) is performed only on the high breakdown voltage transistor formation region side in the semiconductor substrate 1 using a resist mask opened only on the high breakdown voltage transistor formation region side. ₂ F ₂ The second etching stopper layer 13 made of a silicon nitride film is removed by performing dry etching using a mixed gas of Ar and Ar, and anisotropic etching (for example, CH ₂ F ₂ The first etching stopper film 12 is removed by dry etching using a mixed gas of Ar and Ar) to obtain the state shown in FIG.
Alternatively, anisotropic etching (for example, CH) is performed only on the high breakdown voltage transistor formation region side in the semiconductor substrate 1 in the state of FIG. 13 using a resist mask opened only on the high breakdown voltage transistor formation region side. ₂ F ₂ The silicon oxide layer 15 is removed by performing dry etching using a mixed gas of Ar and Ar, and then anisotropic etching (for example, CH ₂ F ₂ The second etching stopper layer 13 made of a silicon nitride film is removed by dry etching using a mixed gas of Ar and Ar). Thereafter, the resist mask is removed, and anisotropic etching (for example, CH ₂ F ₂ The remaining first etching stopper film 12 is removed by performing dry etching using a mixed gas of Ar and Ar, and the state shown in FIG. 14 is obtained.
The removal of the silicon oxide layer 15, the second etching stopper layer 13, and the first etching stopper layer 12 is not limited at this time. If the semiconductor substrate 1 and the gate electrodes 10a and 10b are salicided, the removal is not limited. Good.
[0046]
Thereafter, the same steps (f) to (h) as in the first embodiment described with reference to FIGS. 10 and 11 are performed, and the semiconductor device similar to that in FIG. 1 can be obtained.
In the semiconductor device according to the first embodiment manufactured as described above, a junction breakdown voltage of 10 to 15 V is obtained in a high breakdown voltage transistor, and a breakdown voltage decrease of 9 V or less does not appear, and the breakdown voltage can be stably increased. It was. Moreover, in the low voltage transistor, a junction withstand voltage of 4 to 7 V was stably obtained, and a high driving current could be secured.
[0047]
[Embodiment 3]
FIG. 15 is a sectional view showing a semiconductor device according to the third embodiment of the present invention. 16 to 20 are cross-sectional views illustrating the manufacturing process of the semiconductor device of the third embodiment. 15-20, the same code | symbol is attached | subjected to the element same as Embodiment 1. FIG.
[0048]
As in the first embodiment, the semiconductor device according to the third embodiment has a high breakdown voltage transistor shown in FIG. 15A on the surface of a P-type semiconductor substrate (in this case, a P-type silicon substrate), and FIG. The low voltage transistor (high-speed logic circuit) shown in FIG. The present invention is not limited to this, and can be applied to a nonvolatile memory embedded device such as a flash memory.
[0049]
The high breakdown voltage transistor shown in FIG. 15A includes a first sidewall film 12 made of a silicon oxide film having a thickness of 5 nm, for example, from the side closer to the side surface of the gate electrode 10a. A second side wall film 13a made of a silicon nitride film having a thickness of 100 nm and a third side wall film 14a made of a silicon oxide film having a thickness of 100 nm are sequentially laminated, and the total side wall width (sidewall spacer width) W ₃ Is 205 nm. Note that the first sidewall film 12 is a film in which an etching stopper layer for protecting the element isolation insulating film 2 remains at the time of manufacture.
[0050]
The low voltage transistor shown in FIG. 15B includes a first sidewall film 12 made of a silicon oxide film having a thickness of, for example, 5 nm from the side where the sidewall spacer of the gate electrode 10b is closer to the side surface of the gate electrode 10b. A third sidewall film 14 made of a silicon oxide film having a thickness of 100 nm is laminated in order, and the total sidewall width (sidewall spacer width) W ₄ Is 105 nm. Note that the first sidewall film 12 is a film in which an etching stopper layer for protecting the element isolation insulating film 2 remains at the time of manufacture.
[0051]
In the semiconductor device according to the third embodiment configured as described above, the high breakdown voltage transistor has a sidewall spacer width W as in the semiconductor device according to the first embodiment. ₃ Therefore, the distance from the high-concentration diffusion layer 22 below the sidewall spacer to the tip of the low-concentration diffusion layer 11 below the sidewall spacer has a long and gentle impurity profile, and the junction breakdown voltage is degraded. There is no structure. On the other hand, the low voltage transistor has a fine gate length and a relatively narrow sidewall spacer width W. ₂ Therefore, the area of the low-voltage transistor region can be reduced, and the low-concentration diffusion layer 20 can be shortened because of the thin sidewall film 21, so that parasitic resistance is suppressed and current drive capability is not reduced.
[0052]
Next, a manufacturing method for manufacturing the semiconductor device of the third embodiment shown in FIG. 15 will be described mainly with reference to the cross-sectional views of FIGS.
First, similarly to the step (a) of the first embodiment described above (FIGS. 1 to 4), the gate insulating films 8 and 9 and the gate electrodes 10a and 10b are formed on the semiconductor substrate 1, and then the LDD of the high breakdown voltage transistor. Make an injection.
[0053]
Step (b-3): Next, as shown in FIG. 16, a 5 nm thick silicon oxide film is formed as an etching stopper layer (first sidewall film) 12 on the entire surface of the semiconductor substrate 1, for example, as a side wall spacer formation layer. A silicon nitride film is sequentially deposited as a (second sidewall film) 13a to a thickness of 100 nm. When forming these layers 12 and 13a, for example, the etching stopper layer 12 is formed by oxidizing the surface of the semiconductor substrate 1 to form a silicon oxide film, and the sidewall spacer forming layer 13a is silicon nitrided by LPCVD. A film can be deposited. The ion implantation for forming the low-concentration diffusion layer 11 for the high breakdown voltage transistor is not limited to before the etching stopper layer 12 is formed, but after the etching stopper layer 12 is formed (before the sidewall spacer forming layer 13a is formed). ).
[0054]
Step (c-3): Next, the sidewall spacer forming layer 13a on the surface of the semiconductor substrate 1 in the state of FIG. 16 is anisotropically etched (for example, CH) until the etching stopper layer 12 is exposed. ₂ F ₂ Then, the etching stopper layer 12 is formed on the side surfaces of the gate electrodes 10a and 10b for the high voltage transistor and the low voltage transistor as shown in FIG. Thus, a first sidewall spacer in which a part of the sidewall spacer forming layer 13a remains is formed.
[0055]
Step (d-3): Next, a silicon oxide layer 15 having a thickness of 5 nm is formed on the entire surface of the semiconductor substrate 1 by, for example, LPCVD, and an opening is formed only on the low voltage transistor formation region side (FIG. 18B). The photoresist 16 is formed, and the silicon oxide layer 15 on the low voltage transistor formation region side is removed by wet etching in the first stage using, for example, an etchant containing hydrofluoric acid (HF) to obtain the state shown in FIG. To do.
[0056]
Thereafter, as shown in FIG. 19, the photoresist 16 is removed and, for example, phosphoric acid (H ₃ PO ₄ ) -Containing wet etching is performed using an etchant containing). At this time, since the silicon oxide film on the high breakdown voltage transistor forming region side functions as a stopper film, only the first sidewall spacer (second sidewall film) 13a made of the silicon nitride film in the low voltage transistor forming region is removed. The Since this wet etchant containing phosphoric acid has high selectivity with respect to the silicon oxide layer 15 and the etching stopper layer 12 which function as a stopper film, the side wall spacer only in the low voltage transistor formation region is removed. can do. Note that when the sidewall spacer forming layer 13a (silicon nitride film) is anisotropically etched to form the first sidewall spacer, the underlying etching stopper layer 12 (silicon oxide film) may be simultaneously etched away. In this case, in order to protect the surface of the semiconductor substrate 1, the surface of the substrate 1 may be oxidized again at least before wet etching with phosphoric acid.
[0057]
Step (e-3): Next, as shown in FIG. 20, the entire surface of the substrate is anisotropically etched (for example, CH ₂ F ₂ Dry etching using a mixed gas of Ar and Ar), the silicon oxide layer 15 remaining on the high breakdown voltage transistor formation region side, the etching stopper layer 12 made of a silicon oxide film, and the etching stopper on the low voltage transistor formation region side Layer 12 is removed.
Alternatively, using a resist mask that opens only on the high breakdown voltage transistor formation region side, the silicon oxide layer 15 remaining on the high breakdown voltage transistor formation region side is removed by anisotropic etching, and then the resist mask is removed and the substrate is removed. An anisotropic etching is performed on the entire surface, and the remaining etching stopper layer 12 is removed.
The removal of the silicon oxide layer 15 and the etching stopper layer 12 is not limited at this time, and may be performed before the semiconductor substrate 1 and the gate electrodes 10a and 10b are salicided.
[0058]
Thereafter, as in FIG. 10 and subsequent figures, an LDD region to be the low-concentration diffusion layer 20 is formed in the low-voltage transistor formation region, and the third sidewall 14a corresponding to the fourth sidewall film 14 of the first embodiment is formed. From the point of formation, the same steps (f) to (h) as in the first embodiment shown in FIGS. 10 and 11 are performed to obtain the semiconductor device shown in FIG.
[0059]
In the semiconductor device according to the third embodiment manufactured as described above, a junction breakdown voltage of 10 to 15 V is obtained in a high breakdown voltage transistor, and a breakdown voltage of 9 V or less does not appear, and a high breakdown voltage can be stably achieved. It was. Moreover, in the low voltage transistor, a junction withstand voltage of 4 to 7 V was stably obtained, and a high driving current could be secured. Needless to say, the second sidewall film 13 and the third sidewall film 14 in the high breakdown voltage transistor region are both silicon nitride films, or the first sidewall film 12 and the third sidewall film 12 in the low voltage transistor region. Even when the side wall films 14 are both silicon oxide films and the interface cannot be discriminated, the same effect can be obtained.
[0060]
[Other embodiments]
In the first to third embodiments, a semiconductor device in which a nonvolatile memory such as a flash memory is embedded may be manufactured. In this case, the process of forming the memory cell is performed between the process (c) and the process (f) from the formation of the sidewall spacer of the high breakdown voltage transistor to the formation of the LDD of the low voltage transistor (for example, the state of FIG. 6). If it is appropriately inserted between the states shown in FIG. In this case, although not shown, a fourth sidewall film (in the first and second embodiments) for forming the sidewall spacer (on the third embodiment) is formed on the side surfaces of the control gate and the floating gate of the nonvolatile memory cell. Since only one third sidewall film is laminated, the cell size can be reduced. Note that the sidewall spacer of the nonvolatile memory cell is not limited to this, and an insulating film such as a silicon oxide film may be formed inside the fourth sidewall film or the third sidewall film. The effect of can be obtained.
[0061]
【The invention's effect】
According to the method for manufacturing a semiconductor device of the present invention, when manufacturing a semiconductor device in which a high-voltage drive circuit and a low-voltage drive circuit are mixedly mounted on the same chip, the underlying element isolation insulating film is excessively removed by using an etching stopper film. Therefore, the semiconductor device can be easily manufactured with a good yield without the occurrence of defects and the deterioration of element isolation performance. Also, after removing the sidewall spacer once and performing high-temperature heat treatment such as CVD process, LDD implantation is performed in a self-aligned manner with the gate electrode of the low-voltage transistor. LDD implantation and heat treatment can be performed. In particular, in a low-voltage transistor, a transistor having a fine gate length in which the short channel effect is suppressed can be manufactured without being affected by the gate side wall or the heat treatment.
Further, according to the semiconductor device of the present invention, the high withstand voltage driving circuit and the low voltage driving circuit are mixedly mounted on the same chip, and the underlying element isolation insulating film is protected by the etching stopper film from etching during manufacturing, thereby isolating the element. Performance is improved. In addition, this semiconductor device has a structure in which the width of the side wall spacer is made different for transistors with different breakdown voltage specifications, so that the breakdown voltage performance is further increased for high voltage transistors, and the parasitic resistance is reduced for low voltage transistors, thus ensuring a high drive current. In addition, the element can be miniaturized. Specifically, in a high breakdown voltage transistor, a junction breakdown voltage of 10 to 15 V is obtained, a breakdown voltage decrease of 9 V or less does not appear, and a high breakdown voltage can be stably achieved. In addition, a junction voltage of 4 to 7 V can be stably obtained even in a low voltage transistor, and a high driving current can be secured.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of the first embodiment and represents a step of forming a gate electrode;
FIG. 3 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of the first embodiment, and shows a state in which a gate electrode is formed.
4 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of Embodiment 1, showing a state in which a first LDD region is formed; FIG.
5 is a cross-sectional view for explaining the manufacturing process of the semiconductor device of the embodiment 1, and shows a state in which the first and second etching stopper layers and the first sidewall spacer forming layer are stacked. FIG.
6 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of First Embodiment, in which the first sidewall spacer is formed by anisotropically etching the first sidewall spacer forming layer; FIG. To express.
7 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of First Embodiment, showing a state where the first sidewall spacer in the low-voltage transistor formation region is removed by the first-stage wet etching; FIG. .
8 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of First Embodiment, and shows a state in which the second etching stopper layer is removed by second-stage wet etching; FIG.
FIG. 9 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of the first embodiment, and shows a state where the first etching stopper layer is removed by anisotropic etching.
10 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of the first embodiment, and shows a state in which a second LDD region is formed. FIG.
11 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of First Embodiment, and shows a state in which high-concentration source / drain diffusion layers are formed in the high-breakdown-voltage transistor formation region and the low-voltage transistor region, respectively.
12 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of Embodiment 2, in which the silicon oxide layer and the first sidewall spacer on the low voltage transistor formation region side are removed by the first-stage wet etching; FIG. Represents a state.
13 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of the second embodiment, and shows a state where the second etching stopper layer is removed by the second-stage wet etching; FIG.
14 is a cross-sectional view for explaining a manufacturing process of the semiconductor device of the second embodiment, in which the silicon oxide layer, the second and first etching stopper layers, and the low voltage remaining on the high breakdown voltage transistor forming region side; This represents a state in which the first etching stopper layer remaining on the transistor formation region side is removed by anisotropic etching.
FIG. 15 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.
16 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of Embodiment 3, showing a state in which a first etching stopper layer and a first sidewall spacer forming layer are stacked. FIG.
FIG. 17 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of Embodiment 3, in which the first sidewall spacer is formed by anisotropically etching the first sidewall spacer forming layer; To express.
18 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of Third Embodiment, and shows a state in which the silicon oxide layer on the low voltage transistor formation region side is removed by the first-stage wet etching; FIG.
19 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of Third Embodiment, in a state where the first sidewall spacer on the low voltage transistor formation region side is removed by the second-stage wet etching; FIG. To express.
20 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of Third Embodiment, in which the silicon oxide layer, the first etching stopper layer, and the low-voltage transistor formation region remaining on the high breakdown voltage transistor formation region side; This represents a state where the first etching stopper layer remaining on the side is removed by anisotropic etching.
FIG. 21 is a cross-sectional view illustrating a manufacturing process of a conventional semiconductor device, and shows a state in which gate electrodes are formed in a high breakdown voltage transistor formation region and a low voltage transistor region, respectively.
FIG. 22 is a cross-sectional view illustrating the manufacturing process of the conventional semiconductor device, and shows a state in which the first LDD region and the second LDD region are formed in the high breakdown voltage transistor formation region and the low voltage transistor region.
FIG. 23 is a cross-sectional view for explaining the manufacturing process of the conventional semiconductor device, and shows a state in which the side wall spacer formed on the gate electrode in the low voltage transistor region is removed by wet etching.
FIG. 24 is a cross-sectional view for explaining the manufacturing process of the conventional semiconductor device, showing a state in which high concentration source / drain diffusion layers are formed in the high breakdown voltage transistor formation region and the low voltage transistor region, respectively.
[Explanation of symbols]
1 Semiconductor substrate
2 Element isolation insulating film
3, 18 N well layer
4, 19 P well layer
8 First gate insulating film
9 Second gate insulating film
10a First gate electrode
10b Second gate electrode
11 First LDD region (low concentration diffusion layer)
12 First etching stopper layer (first sidewall film)
13, 13a Second etching stopper layer (sidewall spacer formation layer, second sidewall film)
14, 14a Sidewall spacer formation layer (third sidewall film)
15 Silicon oxide layer
16 photoresist
20 Second LDD region (low concentration diffusion layer)
21 Fourth sidewall film
22 High concentration diffusion layer
A High breakdown voltage transistor formation region
B Low voltage transistor formation region
W ₁ , W ₂ Side wall spacer width

Claims (16)

In a manufacturing method of manufacturing a semiconductor device including a high voltage transistor and a low voltage transistor having different sidewall spacer widths between element isolation insulating films on the surface of a semiconductor substrate,
A first gate insulating film and a first gate electrode for a high breakdown voltage transistor are formed in a high breakdown voltage transistor formation region on the surface of the semiconductor substrate, and a low voltage transistor first region is formed in the low voltage transistor formation region on the surface of the semiconductor substrate. After the step (a) of forming the two-gate insulating film and the second gate electrode,
A step (b) of sequentially stacking an etching stopper layer and a sidewall spacer forming layer for protecting the element isolation insulating film on the surface of the semiconductor substrate;
Etching the sidewall spacer forming layer to form first sidewall spacers each having a part of the sidewall spacer forming layer remaining on each side surface of the first gate electrode and the second gate electrode. (C),
Removing the first sidewall spacer on the second gate electrode side by etching (d);
And (e) removing the etching stopper layer from the surface of the semiconductor substrate by etching. In step (c), a first etching stopper layer, a second etching stopper layer, and a sidewall spacer formation layer are sequentially deposited on the surface of the semiconductor substrate, and the side surface is exposed until the surface of the second etching stopper layer is exposed. By anisotropically etching the wall spacer formation layer, a first sidewall film made of the first etching stopper layer and a second etching stopper layer made of the first etching stopper layer are formed on each of the first gate electrode and the second gate electrode. Forming a first sidewall spacer formed by laminating a second sidewall film and a third sidewall film in which a part of the sidewall spacer forming layer remains,
Thereafter, in the step (d), using the photoresist having an opening in the low voltage transistor region as a mask, the third sidewall film in the low voltage transistor formation region is removed by wet etching in the first stage,
Thereafter, in step (e), the photoresist is removed, and the second etching wet layer using an etchant different from the etchant of the first wet etching is used as the second etching stopper layer in the low voltage transistor formation region. The method for manufacturing a semiconductor device according to claim 1, wherein the first etching stopper layer on the surface of the semiconductor substrate is removed by anisotropic etching after removing by etching. In step (c), a first etching stopper layer, a second etching stopper layer, and a sidewall spacer formation layer are sequentially deposited on the surface of the semiconductor substrate, and the side surface is exposed until the surface of the second etching stopper layer is exposed. By anisotropically etching the wall spacer formation layer, a first sidewall film made of the first etching stopper layer and a second etching stopper layer made of the first etching stopper layer are formed on each of the first gate electrode and the second gate electrode. Forming a first sidewall spacer formed by laminating a second sidewall film and a third sidewall film in which a part of the sidewall spacer forming layer remains,
Then, before performing the step (d), a silicon oxide layer is formed on the entire surface of the semiconductor substrate,
In step (d), the silicon oxide layer and the third sidewall film on the low voltage transistor formation region side are removed by wet etching in the first stage using a photoresist having an opening in the low voltage transistor region as a mask. ,
Thereafter, in step (e), the photoresist is removed, and the second etching wet layer using an etchant different from the etchant of the first wet etching is used as the second etching stopper layer in the low voltage transistor formation region. The silicon oxide layer, the second etching stopper layer, and the first etching stopper layer on the surface of the semiconductor substrate on the high breakdown voltage transistor forming region side are removed by anisotropic etching, respectively. 2. A method for manufacturing a semiconductor device according to 1. In the step (c), an etching stopper layer and a sidewall spacer forming layer are sequentially deposited on the semiconductor substrate, and the sidewall spacer forming layer is anisotropically etched until the surface of the etching stopper layer is exposed. A first side wall film made of an etching stopper layer and a second side wall film in which a part of the sidewall spacer forming layer remains are laminated on each of the gate electrode and the second gate electrode. Form side wall spacers,
Then, before performing the step (d), a silicon oxide layer is formed on the entire surface of the semiconductor substrate,
In step (d), using the photoresist having an opening in the low voltage transistor region as a mask, the silicon oxide layer on the low voltage transistor formation region side is removed by first-stage wet etching with the first material, and the photoresist is formed. Then, the second sidewall film in the low voltage transistor formation region is removed by a second-stage wet etching using an etchant different from the etchant of the first-stage wet etching,
2. The semiconductor according to claim 1, wherein in step (e), the silicon oxide layer, the etching stopper layer, and the etching stopper layer on the surface of the semiconductor substrate on the high breakdown voltage transistor forming region side are respectively removed by anisotropic etching. Device manufacturing method. In the step (b), the first etching stopper layer and the first sidewall spacer forming layer are formed of a silicon oxide film, and the second etching stopper layer is formed of a silicon nitride film,
In the step (d), the third sidewall film is wet etched with an etchant containing hydrofluoric acid,
3. The method of manufacturing a semiconductor device according to claim 2, wherein in the step (e), wet etching of the second etching stopper layer is performed with an etchant containing phosphoric acid. In the step (b), the first etching stopper layer and the first sidewall spacer forming layer are formed of a silicon oxide film, and the second etching stopper layer is formed of a silicon nitride film,
In the step (d), the silicon oxide layer and the third sidewall film are wet etched with an etchant containing hydrofluoric acid,
4. The method of manufacturing a semiconductor device according to claim 3, wherein in the step (e), wet etching of the second etching stopper layer is performed with an etchant containing phosphoric acid. In step (b), an etching stopper layer is formed of a silicon oxide film, and a sidewall spacer forming layer is formed of a silicon nitride film,
5. The semiconductor device according to claim 4, wherein in the step (d), wet etching of the silicon oxide layer is performed with an etchant containing hydrofluoric acid, and wet etching of the second sidewall film is performed with an etchant containing phosphoric acid. Production method. An impurity having a conductivity type opposite to that of the semiconductor substrate is introduced into the high breakdown voltage transistor formation region in the semiconductor substrate between the steps (a) and (b) or immediately after the formation of one layer of the etching stopper layer in the step (b). The method for manufacturing a semiconductor device according to claim 1, further comprising: forming a first LDD region. After step (e)
(F) forming a second LDD region by selectively introducing an impurity having a conductivity type opposite to that of the semiconductor substrate into the low-voltage transistor formation region in the semiconductor substrate;
Forming a new sidewall film on each of the first gate electrode and the second gate electrode, and forming a second sidewall spacer having a different sidewall spacer width on each of the first gate electrode and the second gate electrode (g); When,
The method for manufacturing a semiconductor device according to claim 1, further comprising a step (h) of forming a source / drain in each of the high breakdown voltage transistor formation region and the low voltage transistor formation region. The method for manufacturing a semiconductor device according to claim 9, comprising a step of forming a nonvolatile memory cell between step (c) and step (f). Provided on the surface of the semiconductor substrate are a plurality of high-voltage transistors and a plurality of low-voltage transistors each having sidewall spacers having different sidewall spacer widths, and an element isolation insulating film provided between the transistors,
The side wall spacer of the high breakdown voltage transistor has a total of 4 sidewall films on which the etching stopper layer remains and sidewall film on which the sidewall spacer formation layer remains on the side surface of the first gate electrode for the high breakdown voltage transistor. Layered or layered,
The sidewall spacer of the low voltage transistor includes a sidewall film in which the etching stopper layer remains and a sidewall film in which another sidewall spacer forming layer remains on the side surface of the second gate electrode for the low voltage transistor. A semiconductor device characterized in that two layers are laminated together. The sidewall spacer of the high breakdown voltage transistor is formed by sequentially laminating a first sidewall film, a second sidewall film, a third sidewall film, and a fourth sidewall film on the side surface of the first gate electrode.
The semiconductor device according to claim 11, wherein the sidewall spacer of the low voltage transistor is formed by sequentially stacking the first sidewall film and the fourth sidewall film on a side surface of the second gate electrode. The sidewall spacer of the high breakdown voltage transistor is formed by sequentially laminating a first sidewall film, a second sidewall film, and a third sidewall film on the side surface of the first gate electrode.
The semiconductor device according to claim 11, wherein the sidewall spacer of the low voltage transistor is formed by sequentially stacking the first sidewall film and the third sidewall film on a side surface of the second gate electrode. A nonvolatile memory cell having a sidewall spacer on the side surface of the gate is further provided on the surface of the semiconductor substrate,
The semiconductor device according to claim 12, wherein the sidewall spacer of the nonvolatile memory cell is formed of a fourth sidewall film or a third sidewall film. 15. The semiconductor according to claim 12, wherein the first sidewall film, the third sidewall film, and the fourth sidewall film are each made of a silicon oxide film, and the second sidewall film is made of a silicon nitride film. apparatus. The semiconductor device according to claim 11, wherein the high breakdown voltage transistor has a junction breakdown voltage of 10 to 15 V, and the low voltage transistor has a junction breakdown voltage of 4 to 7 V.

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