TWI631705B - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device includes a substrate, an epitaxial layer, a third dielectric layer, a shielding layer, a fourth dielectric layer, a gate, a plurality of doped regions, and a fifth dielectric layer. The epitaxial layer is on the substrate. The third dielectric layer is disposed in the first trench of the epitaxial layer and forms a second trench in the first trench. The shielding layer has an upper half and a lower half, wherein the lower half is disposed in the second trench, and the upper half protrudes from the third dielectric layer. The gate is disposed in the epitaxial layer and the third dielectric layer, wherein the fourth dielectric layer is disposed between the shielding layer and the gate. The doped region is disposed in an epitaxial layer located around the gate. The fifth dielectric layer is disposed between the doped region and the gate.

Description

Semiconductor component and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same.

Power semiconductors remain the main components of many power electronics systems. In today's power semiconductor applications, the high on-load capability of low on-voltage and reverse voltage is a very important capability indicator.

In order to further improve the various characteristics of power semiconductors, the related fields have not been exhausted. How to provide a semiconductor with better characteristics is one of the current important research and development topics, and it has become an urgent target for improvement in related fields.

One aspect of the present invention provides a semiconductor device and a method of fabricating the same that allows a semiconductor device to have a lower turn-on voltage and can carry a higher reverse voltage by a suitable structural design. In addition, the use of special process design will effectively reduce manufacturing costs.

According to an embodiment of the present invention, a method of fabricating a semiconductor device includes the following steps. First, an epitaxial layer is formed on the substrate. Then, form The first trench is in the epitaxial layer. Thereafter, a first dielectric layer, a second dielectric layer, and a third dielectric layer are sequentially formed on the epitaxial layer, wherein the third dielectric layer forms a second trench, and the second trench is located in the first trench. Then, a shielding layer is formed in the second trench. Then, the upper half of the third dielectric layer is removed such that the upper half of the shield protrudes from the third dielectric layer. Thereafter, a fourth dielectric layer is formed on the upper half of the shield layer. Then, the second dielectric layer and the first dielectric layer not covered by the third dielectric layer are removed to expose the epitaxial layer. Then, a fifth dielectric layer is formed. Thereafter, a gate is formed on the third dielectric layer, and the fifth dielectric layer is interposed between the gate and the epitaxial layer. Finally, a plurality of doped regions are formed in the epitaxial layer around the gate.

According to another embodiment of the present invention, a semiconductor device includes a substrate, an epitaxial layer, a third dielectric layer, a shielding layer, a fourth dielectric layer, a gate, a plurality of doped regions, and a fifth dielectric layer. The epitaxial layer is on the substrate. The third dielectric layer is disposed in the first trench of the epitaxial layer and forms a second trench in the first trench. The shielding layer has an upper half and a lower half, wherein the lower half is disposed in the second trench, and the upper half protrudes from the third dielectric layer. The fourth dielectric layer is disposed on the upper half. The gate is disposed in the epitaxial layer and the third dielectric layer, wherein the fourth dielectric layer is disposed between the shielding layer and the gate. The doped region is disposed in an epitaxial layer located around the gate. The fifth dielectric layer is disposed between the doped region and the gate.

In a semiconductor device, a semiconductor device can produce a low on-voltage similar to a Schottky diode because of the short channel effect that the gate can produce. As a result, the conduction efficiency loss of the semiconductor element can be reduced, and at the same time, it can have excellent reliability performance at a high temperature. Further, since the thickness of the dielectric layer located beside the gate is thin, the on-voltage of the semiconductor element can be further lowered.

The manufacturing method can be compatible with the related processes of the conventional power semiconductor device, so that the semiconductor device can be manufactured only by fine-tuning the original process. In addition, the thickness of the dielectric layer under the gate is sufficiently thick, so that the semiconductor element can carry a high reverse voltage while having a low on-voltage.

Further, by thermally oxidizing the shielding layer, it is only necessary to use one process to form a dielectric layer disposed between the gate and the shielding layer. Thus, the process required to fabricate semiconductor components can be substantially reduced compared to conventional processes, thereby effectively reducing manufacturing costs.

100‧‧‧Semiconductor components

110‧‧‧Substrate

120‧‧‧ epitaxial layer

120t, 140t‧‧‧ top

121, 134, 138‧‧‧ Ditch

122‧‧‧First doped area

123‧‧‧Second doped area

124‧‧‧ Third doped area

129‧‧‧ Groove

131‧‧‧First dielectric layer

132‧‧‧Second dielectric layer

133‧‧‧ Third dielectric layer

135‧‧‧fourth dielectric layer

137‧‧‧ fifth dielectric layer

140‧‧‧Shield

140d‧‧‧ lower half

Upper part of 140u‧‧‧

150‧‧‧ gate

171‧‧‧metal layer

172‧‧‧metal layer

1A to 1G are cross-sectional views showing respective steps of a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

2 is a cross-sectional view showing steps of a method of fabricating a semiconductor device in accordance with another embodiment of the present invention.

3 is a cross-sectional view showing the steps of a method of fabricating a semiconductor device in accordance with still another embodiment of the present invention.

4A to 4C are cross-sectional views showing respective steps of a method of fabricating a semiconductor device in accordance with still another embodiment of the present invention.

Fig. 5 is a cross-sectional view showing the steps of a method of fabricating a semiconductor device in accordance with still another embodiment of the present invention.

Figure 6 is a cross-sectional view showing the steps of a method of fabricating a semiconductor device in accordance with still another embodiment of the present invention.

The embodiments of the present invention are disclosed in the following drawings, and the details of However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not necessary. In addition, some of the conventional structures and elements are shown in the drawings in a simplified schematic manner in order to simplify the drawings.

1A to 1G are cross-sectional views showing respective steps of a method of manufacturing the semiconductor device 100 according to an embodiment of the present invention.

As shown in FIG. 1A, first, an epitaxial layer 120 is formed on the substrate 110. Specifically, the material of the substrate 110 may be a single crystal germanium. The material of the epitaxial layer 120 may be a single crystal germanium.

Next, a first trench 121 is formed in the epitaxial layer 120. Specifically, the method of forming the trench 121 is, for example, etching.

Then, the first dielectric layer 131, the second dielectric layer 132, and the third dielectric layer 133 are sequentially formed on the epitaxial layer 120, wherein the third dielectric layer 133 forms a second trench 134, and the second trench 134 is located In the first trench 121. Specifically, the material of the first dielectric layer 131 may be cerium oxide. The material of the second dielectric layer 132 may be tantalum nitride. The material of the third dielectric layer 133 may be Tetraethoxysilane (TEOS). The first dielectric layer 131 can be formed by thermally oxidizing the epitaxial layer 120. The second dielectric layer 132 and the third dielectric layer 133 may be formed by physical vapor deposition, chemical vapor deposition, or a combination thereof, respectively.

As shown in FIG. 1B, a shielding layer 140 is formed in the second trench 134. Specifically, the shielding layer 140 is first formed on the third dielectric layer 133 (ie, in the trench 134 and the top surface of the dielectric layer 133). Then remove some of the shield 140, leaving only the shielding layer 140 located in the second trench 134. The material of the shielding layer 140 may be polysilicon. The shielding layer 140 can be formed by physical vapor deposition, chemical vapor deposition, or a combination thereof. The method of removing the shielding layer 140 may be etching. In addition, the height of the top surface of the shielding layer 140 is lower than the height of the top surface of the epitaxial layer 120.

As shown in FIG. 1C, the upper half of the third dielectric layer 133 is removed leaving the third dielectric layer 133 in the first trench 121 such that the upper half 140u of the shield layer 140 protrudes. The third dielectric layer 133. Specifically, the method of removing the third dielectric layer 133 may be wet etching.

As shown in FIG. 1D, a fourth dielectric layer 135 is formed on the upper half 140u of the shield layer 140, thereby allowing the fourth dielectric layer 135 to cover the upper half 140u of the shield layer 140. Specifically, the material of the fourth dielectric layer 135 may be cerium oxide. The fourth dielectric layer 135 is formed by thermally oxidizing the shielding layer 140. It should be noted here that the second dielectric layer 132 can protect other structures underneath (eg, the first dielectric layer 131) from being affected when thermally oxidizing the shielding layer 140.

As shown in FIG. 1D and FIG. 1E , the upper half of the second dielectric layer 132 not covered by the third dielectric layer 133 is removed (ie, the height of the top surface of the third dielectric layer 133 is greater than the height of the top surface of the third dielectric layer 133 . Partly) such that the top surface height of the second dielectric layer 132 is substantially the same as the top surface height of the third dielectric layer 133. Specifically, the method of removing the second dielectric layer 132 may be wet etching.

Then, the upper half of the first dielectric layer 131 not covered by the third dielectric layer 133 (ie, a portion having a height greater than the set height of the top surface of the third dielectric layer 133) is removed to make the first dielectric layer The top surface height of the electrical layer 131 and the third dielectric The top surface of layer 133 is substantially the same height and the upper half of epitaxial layer 120 is exposed. Specifically, the method of removing the first dielectric layer 131 may be wet etching.

Then, a fifth dielectric layer 137 is formed on the exposed epitaxial layer 120. Specifically, the material of the fifth dielectric layer 137 may be cerium oxide. The fifth dielectric layer 137 can be formed by thermally oxidizing the epitaxial layer 120.

Thereafter, a gate 150 is formed in the trench 138 and the third dielectric layer 133, and the fifth dielectric layer 137 is interposed between the gate 150 and the epitaxial layer 120. Specifically, the gate 150 is first formed on the top surface of the trench 138 and the third dielectric layer 133. Then, the upper half of the gate 150 is removed leaving only the gate 150 located in the trench 138. Thus, the gate 150 is disposed on the first dielectric layer 131, the second dielectric layer 132, and the third dielectric layer 133 and directly contacts the fifth dielectric layer 137. The material of the gate 150 may be polysilicon. The gate 150 can be formed by physical vapor deposition, chemical vapor deposition, or a combination thereof. The method of removing the gate 150 may be etching.

As shown in FIG. 1F, the first doping region 122 is formed in the epitaxial layer 120 located around the gate 150 (ditch 138) to serve as a body region. The first doping region 122 is formed by ion implantation (Ion Implantation) and drive infiltration (Drive In).

Then, a second doping region 123 is formed in the upper portion of the first doping region 122 (the epitaxial layer 120) located around the gate 150 (ditch 138) as a source region. Specifically, the second doping region 123 is formed by ion implantation and drive-in diffusion.

As shown in FIG. 1F and FIG. 1G, the recess 129 is formed in the second doping region 123. Specifically, the method of forming the recess 129 may be etching.

Then, according to the position of the groove 129, ion implantation and drive-in diffusion are performed to form a third doping region 124 in the first doping region 122 (the epitaxial layer 120) located around the gate 150 (ditch 138). .

Then, the dielectric layer 137 on the top surface of the second doping region 123 is removed, and the metal deuteration layer 171 is formed on the second doping region 123, the third doping region 124, and the gate 150. Specifically, after removing the dielectric layer 137 (which can be removed by etching), a metal layer is first formed on the second doping region 123, the third doping region 124, and the gate 150. In some embodiments, the material of the metal layer can be titanium. The metal layer may be formed by physical vapor deposition, chemical vapor deposition, or a combination thereof. Then, the temperature is raised to the appropriate temperature. Thus, the metal layer will combine with the second doped region 123, the third doped region 124, and the gate 150 underneath to form the metal germanide layer 171. The metal deuteration layer 171 is electrically connected to the second doping region 123, the third doping region 124, and the gate 150. In some embodiments, the material of the metal deuteration layer 171 may be titanium telluride.

Finally, a metal layer 172 is formed on the metal deuteration layer 171. Specifically, the material of the metal layer 172 may be aluminum or copper. The metal layer 172 can be formed by an electrochemical deposition process, a physical vapor deposition process, a chemical vapor deposition process, or a combination thereof.

In the present embodiment, the first doping region 122 is P-type. The second doping region 123 is of the N+ type. The third doping region 124 is of the P+ type. It should be understood that the specific embodiments of the first doping region 122, the second doping region 123, and the third doping region 124 are merely illustrative and are not intended to limit the present invention, and are generally in the technical field of the present invention. The knowledgeer should flexibly select the specific embodiments of the first doping region 122, the second doping region 123 and the third doping region 124 according to actual needs.

In the semiconductor device 100, the semiconductor device 100 will be able to generate a low on-voltage similar to a Schottky diode because of the short channel effect that the gate 150 can generate. Thus, the conduction efficiency loss of the semiconductor element 100 can be reduced, and at the same time, it can have excellent reliability performance at a high temperature. Further, since the thickness of the dielectric layer 137 located beside the gate 150 is thin, the on-voltage of the semiconductor element 100 can be further lowered.

The manufacturing method can be compatible with the related processes of the conventional power semiconductor device, and thus the semiconductor device 100 can be manufactured only by fine-tuning the original process. In addition, the thicknesses of the first dielectric layer 131, the second dielectric layer 132, and the third dielectric layer 133 under the gate 150 are sufficiently thick, so that the semiconductor device 100 can carry a high voltage while having a low on-voltage. Reverse voltage.

Further, by thermally oxidizing the shielding layer 140, only the fourth dielectric layer 135 disposed between the gate 150 and the shielding layer 140 can be formed by using one process. Thus, the process required to fabricate the semiconductor device 100 can be greatly reduced compared to the conventional process, thereby effectively reducing the manufacturing cost.

2 is a cross-sectional view showing steps of a method of fabricating a semiconductor device 100 in accordance with another embodiment of the present invention. As shown in FIG. 2, the manufacturing method of the present embodiment is substantially the same as the manufacturing method of the above-described embodiment, and the main difference is that after the second doping region 123 is formed, the groove 129 is not formed as in the first G-figure. In the second doping region 123, a third doping region 124 is directly formed in the first doping region 122 and the second doping region 123, wherein the bottom doping depth of the third doping region 124 is greater than the second doping region The bottom depth of zone 123.

3 is a cross-sectional view showing the steps of a method of fabricating the semiconductor device 100 in accordance with still another embodiment of the present invention. As shown in Figure 3, this implementation The manufacturing method of the method is substantially the same as the manufacturing method of the first G diagram, and mainly differs in that the groove 129 and the third doping region 124 are not formed in the present embodiment. In addition, the first doping region 122 is P-type. The second doping region 123 is of the P+ type. It should be understood that the specific embodiments of the first doping region 122 and the second doping region 123 are merely illustrative and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains should be considered as needed. A specific embodiment of the first doping region 122 and the second doping region 123 is elastically selected.

4A to 4B are cross-sectional views showing respective steps of a method of fabricating the semiconductor device 100 according to still another embodiment of the present invention. The manufacturing method of the present embodiment is substantially the same as the manufacturing method of the above-described embodiment, and the differences will be mainly described below.

As shown in FIG. 4A, when the partial shield layer 140 is removed, the top surface 140t of the remaining shield layer 140 is disposed at a height approximately equal to the set height of the top surface 120t of the epitaxial layer 120.

As shown in FIG. 4B, when the gate 150 is formed, since the height of the top surface of the fourth dielectric layer 135 is greater than or equal to the set height of the top surface 120t of the epitaxial layer 120, the gate 150 will not It will be placed above the upper half 140u of the shield layer 140. In other words, the gate 150 is not disposed on the top surface of the fourth dielectric layer 135.

As shown in FIG. 4C, the semiconductor device 100 formed in the present embodiment is basically the same as the semiconductor device 100 formed in FIG. 1G. The main difference is that in the present embodiment, the top surface 140t of the shield layer 140 is disposed. The height is approximately equal to the set height of the top surface 120t of the epitaxial layer 120 (the first doped region 122, the second doped region 123, and the third doped region 124 are formed in the epitaxial layer 120), so The gate 150 is not disposed above the upper half 140u of the shield layer 140. Further, in the foregoing process, since the top surface of the fourth dielectric layer 135 is disposed at a height greater than or equal to the set height of the top surface 120t of the epitaxial layer 120, a portion of the fourth dielectric layer 135 will protrude. Epitaxial layer 120. Prior to forming the metal deuteration layer 171, the dielectric layer 135 protruding from the epitaxial layer 120 is removed, thereby exposing the shield layer 140. Thus, the metal deuteration layer 171 is also electrically connected to the shielding layer 140. Specifically, the method of removing the fourth dielectric layer 135 protruding from the epitaxial layer 120 may be a Chemical Mechanical Planarization (CMP).

FIG. 5 is a cross-sectional view showing steps of a method of fabricating a semiconductor device 100 according to still another embodiment of the present invention. As shown in FIG. 5, the manufacturing method of the present embodiment is substantially the same as the manufacturing method of the fourth embodiment to the fourth embodiment, and the main difference is that after the second doping region 123 is formed, no groove is formed. 129 directly forms the third doping region 124 in the first doping region 122 and the second doping region 123 , wherein the bottom doping depth of the third doping region 124 is greater than the bottom doping depth of the second doping region 123 .

FIG. 6 is a cross-sectional view showing steps of a method of fabricating a semiconductor device 100 according to still another embodiment of the present invention. As shown in FIG. 6, the manufacturing method of the present embodiment is substantially the same as the manufacturing method of FIGS. 4A to 4C, and mainly differs in that, in the present embodiment, the recess 129 and the third doping region are not formed. 124. In addition, the first doping region 122 is P-type. The second doping region 123 is of the P+ type. It should be understood that the specific embodiments of the first doping region 122 and the second doping region 123 are merely illustrative and are not intended to limit the present invention. A person having ordinary knowledge in the field of art should flexibly select a specific embodiment of the first doping region 122 and the second doping region 123 as needed.

In a semiconductor device, a semiconductor device can produce a low on-voltage similar to a Schottky diode because of the short channel effect that the gate can produce. As a result, the conduction efficiency loss of the semiconductor element can be reduced, and at the same time, it can have excellent reliability performance at a high temperature. Further, since the thickness of the dielectric layer located beside the gate is thin, the on-voltage of the semiconductor element can be further lowered.

The manufacturing method can be compatible with the related processes of the conventional power semiconductor device, so that the semiconductor device can be manufactured only by fine-tuning the original process. In addition, the thickness of the dielectric layer under the gate is sufficiently thick, so that the semiconductor element can carry a high reverse voltage while having a low on-voltage.

Further, by thermally oxidizing the shielding layer, it is only necessary to use one process to form a dielectric layer disposed between the gate and the shielding layer. Thus, the process required to fabricate semiconductor components can be substantially reduced compared to conventional processes, thereby effectively reducing manufacturing costs.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

Claims (15)

A method for fabricating a semiconductor device, comprising: forming an epitaxial layer on a substrate; forming a first trench in the epitaxial layer; sequentially forming a first dielectric layer, a second dielectric layer, and a first a third dielectric layer on the epitaxial layer, wherein the third dielectric layer forms a second trench, the second trench is located in the first trench; a shielding layer is formed in the second trench; An upper half of the three dielectric layers such that an upper portion of the shielding layer protrudes from the third dielectric layer; a fourth dielectric layer is formed on the upper portion of the shielding layer; The second dielectric layer and the first dielectric layer are covered by the third dielectric layer to expose the epitaxial layer; a fifth dielectric layer is formed on the first dielectric layer, and a portion is exposed The first dielectric layer; forming a gate on the third dielectric layer and interposing the fifth dielectric layer between the gate and the epitaxial layer; and forming a plurality of doped regions In the epitaxial layer around the gate. The method of fabricating a semiconductor device according to claim 1, wherein the fourth dielectric layer is formed by thermally oxidizing the shielding layer. The method of fabricating a semiconductor device according to claim 1, wherein a top surface height of the shielding layer is lower than a top surface height of the epitaxial layer. The method of fabricating a semiconductor device according to claim 1, wherein the forming the plurality of doped regions comprises: forming a first doped region in the epitaxial layer located around the gate as a substrate And forming a second doped region in the upper portion of the first doped region around the gate as a source region. The method of fabricating a semiconductor device according to claim 4, wherein after forming the second doped region, further comprising: forming a recess in the second doped region; and forming a third according to the recess position A doped region is in the first doped region. The method of manufacturing the semiconductor device of claim 4, wherein after the forming the second doped region, further comprising: forming a third doped region in the first doped region, wherein the third doped region The bottom depth is greater than the bottom depth of the second doped region. The method of fabricating a semiconductor device according to claim 1, wherein a top surface height of the fourth dielectric layer is greater than or equal to a top surface height of the epitaxial layer. A semiconductor component comprising: a substrate; an epitaxial layer on the substrate; a third dielectric layer disposed in a first trench of the epitaxial layer and forming a second trench in the first trench; a shielding layer having an upper half and a lower half, wherein the lower layer a half portion is disposed in the second trench, the upper portion protrudes from the third dielectric layer; a fourth dielectric layer; a gate disposed in the epitaxial layer and the third dielectric layer The fourth dielectric layer is disposed between the shielding layer and the gate; a plurality of doped regions are disposed in the epitaxial layer around the gate; and a fifth dielectric layer is disposed Between the doped region and the gate, wherein the fifth dielectric layer has a thickness smaller than a thickness of the first dielectric layer at a junction of the fifth dielectric layer and the first dielectric layer. The semiconductor device of claim 8, wherein a top surface height of the shielding layer is lower than a top surface height of the epitaxial layer, at least a portion of the gate is located above the upper half of the shielding layer. The semiconductor device of claim 8, wherein a top surface height of the fourth dielectric layer is greater than or equal to a top surface height of the epitaxial layer. The semiconductor device of claim 8, wherein the fourth dielectric layer is formed by thermally oxidizing the shielding layer. The semiconductor device of claim 8, further comprising: the third dielectric layer is made of tetraethoxy decane; a first dielectric layer is disposed between the epitaxial layer and the first dielectric layer, wherein the first dielectric layer is made of germanium dioxide; and a second dielectric layer is disposed on the first Between the dielectric layer and the third dielectric layer, wherein the second dielectric layer is made of tantalum nitride. The semiconductor device of claim 8, wherein the doped regions comprise: a first doped region in the epitaxial layer around the gate as a base region; and a second doping A miscellaneous region is located in the upper portion of the first doped region around the gate as a source region. The semiconductor device of claim 13, further comprising: a third doped region located in the first doped region, wherein the second doped region has a recess, and the position of the third doped region corresponds to At the location of the groove. The semiconductor device of claim 13, further comprising: a third doped region located in the first doped region, wherein a bottom depth of the third doped region is greater than a bottom depth of the second doped region.