JP2008251757A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a structure for realizing both fast switching and breakdown voltage using a simple process. <P>SOLUTION: A main electrode layer 55a of a Schottky junction region portion S and a sub-electrode layer 55b of a guard ring region portion G are separately formed on the principal plane of one side of a semiconductor substrate. The main electrode layer 55a and the sub-electrode layer 55b are isolated from each other by an interlayer insulating film 54. The main electrode layer 55a forms a Schottky junction, with a lightly-doped semiconductor layer 52 on the Schottky junction region portion S. The sub-electrode layer 55b forms the Schottky junction with the lightly-doped semiconductor layer 52 and forms a junction with a guard ring layer 53 on the guard ring region portion G. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique related to improvement of high breakdown voltage and high-speed switching in a Schottky diode (SBD).

Conventionally, an example of this type of semiconductor device is shown in FIG. In this Schottky barrier diode, a semiconductor substrate is formed by laminating an N ⁻ type semiconductor layer (epitaxial layer) 2 on an N ⁺ type semiconductor substrate 1, and a metal layer that forms a Schottky junction on the surface of the N ⁻ type semiconductor layer 2. An (anode electrode) 3 is provided, and a region where the metal layer 3 and the N ⁻ type semiconductor layer 2 are joined becomes a Schottky junction region. A guard ring 4 in which P ⁺ -type impurities are diffused is provided on the outermost periphery of this Schottky junction region, and an interlayer insulating film 5 is provided to cover the outer peripheral surface of the N ⁻ -type semiconductor layer 2 and the outer peripheral surface of the guard ring 4, A cathode electrode 6 is provided on the back surface of the semiconductor substrate.

In this Schottky barrier diode, the depletion layer 7 extends from the Schottky junction region to the N ⁻ type semiconductor layer 2 when a reverse bias is applied. At this time, due to the presence of the p + type guard ring 4 at the outermost periphery of the Schottky junction region, the depletion layer expands in the horizontal (horizontal) direction, and its curvature is relaxed to provide a withstand voltage.

The depletion layer 7 becomes a capacitive component, and the Schottky barrier diode does not have a low capacitance. In addition, the guard ring 4 and the N ⁻ type semiconductor layer 2 form a pN junction and operate as a pN junction diode when a predetermined voltage is exceeded when a forward voltage is applied, and when a reverse voltage is applied to switch to an off state, Since the depletion layer 7 spreads after the outflow or recombination of carriers accumulated in the N ⁻ type semiconductor 2 is performed, a reverse recovery time (Trr) occurs. For this reason, the presence of a guard ring for securing a breakdown voltage hinders a reduction in capacity and a high-speed operation.

Another semiconductor device is shown in FIG. In this Schottky barrier diode, a semiconductor substrate is formed by laminating an N ⁻ type semiconductor layer (epitaxial layer) 2 on an N ⁺ type semiconductor substrate 1, and a metal layer that forms a Schottky junction on the surface of the N ⁻ type semiconductor layer 2. An (anode electrode) 3 is provided, and a region where the metal layer 3 and the N ⁻ type semiconductor layer 2 are joined becomes a Schottky junction region. An interlayer insulating film 5 is provided to cover the outer peripheral surface of the N ⁻ -type semiconductor layer 2 and the outer peripheral surface of the trench 8, and a cathode electrode 6 is provided on the back surface of the semiconductor substrate. A trench 8 provided surrounding the Schottky junction region passes through the N ⁻ type semiconductor layer 2 and reaches the N ⁺ type semiconductor substrate 1, and an insulating film 9 is provided in the trench 8.

  With this configuration, when the reverse voltage is applied, the horizontal extension of the depletion layer 7 terminates in the trench 8 (insulating film 9), and the depletion layer 7 does not have a curvature at the end, but only in the depth direction of the semiconductor substrate. spread. For this reason, the depletion layer does not occur around the guard ring, and the capacity component is reduced accordingly.

Another semiconductor device is shown in FIG. In this Schottky barrier diode, a semiconductor substrate is formed by laminating an N ⁻ type semiconductor layer (epitaxial layer) 2 on an N ⁺ type semiconductor substrate 1, and a metal layer that forms a Schottky junction on the surface of the N ⁻ type semiconductor layer 2. An (anode electrode) 3 is provided, and a region where the metal layer 3 and the N ⁻ type semiconductor layer 2 are joined becomes a Schottky junction region.

A guard ring 4 in which P ⁺ -type impurities are diffused is provided at a position separated from the Schottky junction region. An interlayer insulating film 5 provided so as to cover the outer peripheral surface of the N ⁻ type semiconductor layer 2 corresponding to the outermost periphery of the Schottky junction region includes a central window portion corresponding to the Schottky junction region and an annular window portion corresponding to the guard ring 4. The metal layer 3 that is Schottky-bonded to the N ⁻ type semiconductor layer 2 is separated from the central window portion, and the annular metal layer 3a that is bonded to the guard ring 4 is separated from the annular window portion, and the cathode is formed on the back surface of the semiconductor substrate. An electrode 6 is provided.

According to this configuration, when the forward bias is applied, the annular metal layer 3a is separated from the metal layer 3 so that holes are not injected into the guard ring 4. When the reverse bias is applied, the Schottky junction region and the guard ring 4 are not injected. Is rapidly depleted, and the electric field is dispersed at the edge of the metal layer 3 before the electric field reaches a high value.
JP 2005-243717 A JP-A-10-178186

  Incidentally, as described above, in the configuration shown in FIG. 3, since the Schottky diode is a majority carrier device, it has a low forward voltage and can perform high-speed switching. Further, by providing the guard ring in the peripheral annular region, the depletion layer formed around the guard ring in the reverse bias state extends in the lateral direction (the direction along the main surface of the substrate) to ensure the breakdown voltage. In order to ensure this breakdown voltage, it is necessary to set the width, depth, cross-sectional area, and impurity concentration of the guard ring to predetermined values.

  However, as described above, if such a guard ring is provided for the purpose of securing a breakdown voltage, there is a concern that the switching characteristics of the device may be affected. That is, when the device is turned off from the forward direction to the reverse direction, it takes time for the minority carriers injected from the guard ring to disappear, so there is a concern that the reverse recovery time will increase and the switching characteristics will deteriorate. is there.

  There were two approaches to avoid such problems. That is, the configuration shown in FIG. 4 is a technique of ensuring a breakdown voltage and ensuring switching by forming a trench in the guard ring.

FIG. 6 shows a method for manufacturing the Schottky barrier diode according to the configuration of FIG.
1) Growth of mask oxide film As shown in FIG. 6A, the semiconductor substrate is formed by laminating an N ⁻ type semiconductor layer (epitaxial layer) 2 on an N ⁺ type semiconductor substrate 1, and on the main surface of the N ⁻ type semiconductor layer 2. A mask oxide film (interlayer insulating film) 21 is formed.
2) TR mask alignment As shown in FIG. 6B, a TR mask (resist) 22 having a window at a portion where a trench is to be formed on the mask oxide film 21 is aligned.
3) SiO2 etching (TR hard mask)
As shown in FIG. 6C, the mask oxide film 21 is etched in the window of the TR mask 22 to form a TR hard mask.
4) TR dry etching As shown in FIG. 6D, after removing the resist of the TR mask 22, the N ⁻ type semiconductor layer 2 is dry etched to form a trench 8. At this time, it is theoretically difficult to dig deep trenches 8 by etching, and there is a problem that trenches 8 spread laterally, and expensive equipment is required.
5) TEOS growth As shown in FIG. 6E, a TEOS (tetraethoxysilane) insulating film 9 is formed on the surface of the mask oxide film 21 and the trench 8 by high-density plasma chemical vapor deposition (HDP-CVD). At this time, if there is a defect in the shape of the trench 8, a gap is generated in the insulating film 9, which greatly affects the reliability.
6) CW Window Formation As shown in FIG. 6 (f), a CW mask (resist) 23 having a window for forming the metal layer 3 is aligned on the insulating film 9.
7) CW etching As shown in FIG. 6G, the insulating film 9 is etched in the window of the CW mask 23 to expose the N ⁻ type semiconductor layer 2.
8) Preparation of metal electrode film As shown in FIG. 6 (h), after removing the resist of the CW mask 23, a metal layer 3 as a metal electrode film is formed on the N ⁻ type semiconductor layer 2 and the insulating film 9.
9) MW mask alignment As shown in FIG. 6 (i), an MW mask (resist) 24 having a window for removing the outer peripheral portion of the metal layer 3 is aligned on the metal layer 3.
10) MW Etching As shown in FIG. 6 (j), the metal layer 3 is etched in the window of the MW mask 24 to expose the insulating film 9.
11) Metallization annealing As shown in FIG. 6K, after removing the resist of the MW mask 24, metallization annealing is performed.

  As described above, the trench process has a higher technical and equipment difficulty than the planar process, and specifically, it is difficult to achieve uniform trench etching and a good trench shape.

  Next, in the configuration shown in FIG. 5, the Schottky junction region and the guard ring region are electrically separated, and the width of the interlayer insulating film 5 is set to an appropriate value so that the Schottky junction region can be separated from the Schottky junction region at the time of reverse bias. A structure in which the extending depletion layer 7a and the depletion layer 7b extending from the guard ring 4 are easily connected can be realized.

FIG. 7 shows a method for manufacturing the Schottky barrier diode according to the configuration shown in FIG.
1) Growth of mask oxide film As shown in FIG. 7A, the semiconductor substrate is formed by laminating an N ⁻ type semiconductor layer (epitaxial layer) 2 on an N ⁺ type semiconductor substrate 1, and on the main surface of the N ⁻ type semiconductor layer 2. A mask oxide film (interlayer insulating film 5) 31 is formed.
2) GR mask alignment As shown in FIG. 7B, a GR mask (resist) 32 having a window at the portion where the guard ring 4 is formed is aligned on the mask oxide film 31.
3) GR etching As shown in FIG. 7C, the mask oxide film 31 is etched in the window of the GR mask 32 to form a window.
4) GR injection (B ⁺ )
As shown in FIG. 7D, boron is implanted into the N ⁻ type semiconductor layer 2 through the window of the GR mask 32 and the window of the mask oxide film 31.
5) Boron diffusion As shown in FIG. 7E, after removing the resist of the GR mask 32, boron in the N ⁻ type semiconductor layer 2 is diffused to form the guard ring 4.
6) CW Window Formation As shown in FIG. 7 (f), a CW mask (resist) 33 having a window for forming the metal layer 3 is aligned on the mask oxide film 31 and the guard ring 4.
7) CW etching As shown in FIG. 7G, the mask oxide film 31 is etched in the window of the CW mask 33 to expose the N ⁻ type semiconductor layer 2 in the portion corresponding to the Schottky junction region, and the interlayer insulation The film 5 is formed.
8) Preparation of metal electrode film As shown in FIG. 7 (h), after removing the resist of the CW mask 33, a metal layer 3 as a metal electrode film is formed on the N ⁻ type semiconductor layer 2 and the interlayer insulating film 5. .
9) MW mask alignment As shown in FIG. 7 (i), on the metal layer 3, a window for removing the outer peripheral portion of the metal layer 3 and a separation portion separating the Schottky junction region and the guard ring region are formed. The MW mask (resist) 34 having a window for the alignment is aligned.
10) MW Etching As shown in FIG. 7J, the metal layer 3 is etched in the window of the MW mask 34 to expose the interlayer insulating film 5.
11) Metallization annealing As shown in FIG. 7 (k), metallization annealing is performed after the resist of the MW mask 34 is removed.

  As described above, since the guard ring 4 needs a predetermined width, depth, cross-sectional area, and impurity concentration in order to ensure the intended breakdown voltage, the capacitance still changes. Absent.

  In view of the above problems, the present invention has a structure in which the guard ring has a small cross-sectional area and a predetermined breakdown voltage can be secured by a simple process in order to form a Schottky barrier diode that achieves both high-speed switching and breakdown voltage. It is an object to provide a semiconductor device having the following.

  In order to solve the above problems, in a semiconductor device of the present invention, a low-concentration semiconductor layer having the same conductivity type is formed on a semiconductor substrate, and a guard ring layer having a conductivity type different from the low-concentration semiconductor layer is the low-concentration semiconductor layer. An insulating protective film is formed on the main surface on one side of the semiconductor substrate except for the Schottky junction region and the guard ring region. Metal is separately formed on the main surface on one side of the semiconductor substrate into the main electrode layer of the Schottky junction region and the sub electrode layer of the guard ring region, and the main electrode layer and the sub electrode layer The main electrode layer is in Schottky junction with the low concentration semiconductor layer in the Schottky junction region, and the sub electrode layer is in contact with the low concentration semiconductor layer in the guard ring region. Shi Characterized by joining the guard ring layer while Ttoki junction.

  In the method for manufacturing a semiconductor device according to the present invention, a low concentration semiconductor layer having the same conductivity type is formed on a semiconductor substrate by epitaxial growth, and an insulating protective film forming step is formed on the low concentration semiconductor layer. And selectively etching the insulating protective film to open a predetermined portion to expose the surface of the low-concentration semiconductor layer, and to have a conductivity type different from that of the low-concentration semiconductor layer using the insulating protective film as a mask. A guard ring layer forming step for forming a guard ring layer extending from the surface of the low-concentration semiconductor layer into the layer by injecting and diffusing the dopant, and selective etching is performed on the insulating protective film to perform a shot. The low-concentration semiconductor layer and the guard are exposed by opening a window in the key junction region and the guard ring region, and exposing the main surface on one side of the semiconductor substrate using the insulating protective film as a mask. A metal forming step of forming a Schottky metal on the ring layer and the insulating protective film, and forming a mask having a window between the Schottky junction region and the guard ring region on the Schottky metal, Etching the Schottky metal in the window of the mask to expose the insulating protective film, thereby making the Schottky metal a main electrode layer in the Schottky junction region portion and a sub electrode layer in the guard ring region portion. And a metal dividing step of separating and dividing.

  As described above, according to the present invention, the guard ring separated by the insulating protective film (interlayer insulating film) around the Schottky junction region where the Schottky metal main electrode layer and the low-concentration semiconductor layer are Schottky joined. By providing a region portion, and a region in which the Schottky metal sub-electrode layer and the low-concentration semiconductor layer are in a Schottky junction and a region in which the sub-electrode layer and the guard ring layer are joined in the guard ring region portion, Even if the width of the guard ring layer in the guard ring region is narrower than that of the conventional case, the guard ring layer can realize a withstand voltage structure equivalent to that of the conventional case, and the guard ring layer has a smaller width than that of the conventional guard ring. A reduction in electric capacity can be realized. Furthermore, the semiconductor device of the present invention can be produced by a conventional simple planar technique without requiring a three-dimensional process such as a trench process.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In FIG. 1, a Schottky barrier diode (semiconductor device) is formed by stacking an N ⁻ type semiconductor layer (epitaxial layer) 52 of a low-concentration semiconductor layer having the same conductivity type as a semiconductor substrate on an N ⁺ type semiconductor substrate 51. A guard ring layer 53 is formed in an annular shape extending from the surface of the N ⁻ type semiconductor layer 52 into the layer, and the guard ring layer 53 diffuses P ⁺ type impurities into the N ⁻ type semiconductor layer 52 to form an N ^{− type.} It has a conductivity type different from that of the type semiconductor layer 52.

On the surface of the N ⁻ type semiconductor layer 52 which forms the main surface on one side of the semiconductor substrate, an interlayer insulating film 54 which forms an insulating protective film is formed except for the Schottky junction region S and the guard ring region G. .

Further, a Schottky metal layer 55 is provided on the surface of the N ⁻ type semiconductor layer 52 that forms one main surface of the semiconductor substrate, and the metal layer 55 is separated from the main electrode layer (anode) by the interlayer insulating film 54. Electrode) 55a and sub-electrode layer 55b are formed separately.

The main electrode layer 55a is in Schottky junction with the N ⁻ type semiconductor layer 2 in the whole area of the Schottky junction region S, and the sub electrode layer 55b is in Schottky junction with the N ⁻ type semiconductor layer 52 in the guard ring region portion G. At the same time, it is bonded to the guard ring layer 53.

The value of the interlayer insulating film 54 and the ratio of the region G1 and the region G2 in the guard ring region G are set to appropriate values necessary for obtaining a required breakdown voltage. The capacitance of the Schottky junction surface between the layer 55 b and the N ⁻ type semiconductor layer 2 is slightly smaller than the capacitance of the pn junction surface between the guard ring layer 53 and the N ⁻ type semiconductor layer 2. A cathode electrode 56 is provided on the back surface of the semiconductor substrate.

In the present embodiment, a region G1 in which the Schottky metal sub-electrode layer 55b and the N ⁻ type semiconductor layer 2 are in Schottky junction is provided in the inner region of the guard ring region G, and the sub-electrode layer 55b is disposed in the outer region. Although the region G2 where the guard ring layer 53 is joined is provided, the present invention is not limited to the configuration described above.

For example, a region G2 where the sub electrode layer 55b and the guard ring layer 53 are joined is provided in the inner region of the guard ring region G, and the Schottky metal sub electrode layer 55b and the N ⁻ type semiconductor layer 2 are formed in the outer region. It is possible to provide the key junction region G1, and the Schottky metal sub electrode layer 55b and the N ⁻ type semiconductor layer 2 are provided on both sides of the region G2 where the sub electrode layer 55b and the guard ring layer 53 are joined. It is also possible to provide a region G1 for Schottky junction.

  With this configuration, the sub-electrode layer 55b is separated from the main electrode layer 55a, so that holes are not injected into the guard ring layer 53 when a forward bias is applied, and a slight reverse bias is applied when a reverse bias is applied. The depletion layer 57a in the Schottky junction region S and the depletion layer 57b in the guard ring region portion G are connected to each other, and the electric field is generated between the Schottky junction region S of 55a and the guard ring region portion G of the guard ring layer 53. Before reaching a high value, the electric field in the Schottky junction region S is dispersed.

  Therefore, even if the guard ring layer 53 is formed to be narrower than the conventional one in the guard ring region G, the guard ring layer 53 realizes the same breakdown voltage structure as the conventional one, while the guard ring layer 53 has the same width as the conventional guard ring. By making it narrower, the capacitance can be reduced.

Next, a method for manufacturing a semiconductor device of the present invention will be described with reference to FIG.
1) Mask oxide film growth (insulating protective film formation process)
As shown in FIG. 2A, in the semiconductor substrate, an N ⁻ type semiconductor layer (epitaxial layer) 52 is stacked on an N ⁺ type semiconductor substrate 51, and a mask oxide film (interlayer insulation) is formed on the main surface of the N ⁻ type semiconductor layer 52. Film 54) 41 is formed.
2) GR mask alignment (guard ring layer forming process)
As shown in FIG. 2B, a GR mask (resist) 42 having a window at the portion where the guard ring layer 53 is formed on the mask oxide film 41 is aligned.
3) GR etching (guard ring layer forming process)
As shown in FIG. 2C, the mask oxide film 41 is etched in the window of the GR mask 42 to form a window.
4) GR injection (B ⁺ ) (guard ring layer forming step)
As shown in FIG. 2D, boron is implanted into the N ⁻ type semiconductor layer 52 through the window of the GR mask 42 and the window of the mask oxide film 41.
5) Boron diffusion (guard ring layer formation process)
As shown in FIG. 2E, after removing the resist of the GR mask 42, boron in the N ⁻ type semiconductor layer 52 is diffused to form a guard ring layer 53.
6) CW window formation (metal formation process)
As shown in FIG. 2F, a CW mask (resist) 43 having a window for forming a Schottky metal layer 55 is aligned on the mask oxide film 41.
7) CW etching (metal forming process)
As shown in FIG. 2G, the mask oxide film 41 is etched into the interlayer insulating film 54 in the window of the CW mask 43, and the N ⁻ type semiconductor layer 52 corresponding to the Schottky junction region S is exposed. Thus, the N ⁻ type semiconductor layer 52 and the guard ring layer 53 in the part corresponding to the guard ring region G are exposed.
8) Metal electrode film creation (metal formation process)
As shown in FIG. 2H, after removing the resist of the CW mask 43, a Schottky metal layer 55 is formed on the N ⁻ type semiconductor layer 52, the guard ring layer 53, and the interlayer insulating film 54.
9) MW mask alignment (metal division process)
As shown in FIG. 2I, on the metal layer 55, a window for removing the outer peripheral portion of the metal layer 55 and a separation portion for separating the Schottky junction region S and the guard ring region G are formed. A MW mask (resist) 44 having a window is aligned.
10) MW etching (metal division process)
As shown in FIG. 2J, the metal layer 55 is etched in the window of the MW mask 44 to expose the interlayer insulating film 54, and the metal layer 55 is separated and divided into a main electrode layer 55a and a sub electrode layer 55b.
11) Metallization annealing As shown in FIG. 2 (k), after removing the resist of the MW mask 44, metallization annealing is performed.

  As described above, the semiconductor device of the present invention can be manufactured by a conventional simple planar technique without requiring three-dimensional processing as in the trench process.

  The present invention is effective for a semiconductor device because the width of the guard ring layer can be narrowed to achieve a breakdown voltage structure and a reduction in capacitance.

Sectional drawing which shows the semiconductor device in embodiment of this invention Schematic diagram showing the manufacturing process of the semiconductor device Sectional view showing a conventional semiconductor device Sectional drawing which shows another conventional semiconductor device Sectional drawing which shows another conventional semiconductor device Schematic diagram showing the manufacturing process of a conventional semiconductor device Schematic diagram showing the manufacturing process of another conventional semiconductor device

Explanation of symbols

S Schottky junction region G Guard ring region G1, G2 region 51 N ⁺ type semiconductor substrate 52 N ⁻ type semiconductor layer 53 Guard ring layer 54 Interlayer insulating film 55 Metal layer 55a Main electrode layer (anode electrode)
55b Sub-electrode layer 56 Cathode electrode

Claims (2)

A low-concentration semiconductor layer having the same conductivity type is formed on a semiconductor substrate, and a guard ring layer having a conductivity type different from that of the low-concentration semiconductor layer extends from the surface of the low-concentration semiconductor layer into the layer to form an annular shape. An insulating protective film is formed on one main surface of the semiconductor substrate except for a Schottky junction region portion and a guard ring region portion, and a Schottky metal is formed on the one main surface of the semiconductor substrate. The main electrode layer of the junction region and the sub-electrode layer of the guard ring region are formed separately and divided, the insulating protective film separates the main electrode layer and the sub-electrode layer, the main electrode layer The Schottky junction region is in Schottky junction with the low-concentration semiconductor layer, and the sub-electrode layer is in Schottky junction with the low-concentration semiconductor layer in the guard ring region and joined with the guard ring layer. Wherein a. An insulating protective film forming step of forming a low concentration semiconductor layer having the same conductivity type by epitaxial growth on a semiconductor substrate, and forming an insulating protective film on the low concentration semiconductor layer;
The insulating protective film is selectively etched to open a predetermined portion to expose the surface of the low-concentration semiconductor layer, and a dopant having a conductivity type different from that of the low-concentration semiconductor layer is formed using the insulating protective film as a mask. A guard ring layer forming step of forming a guard ring layer extending from the surface of the low-concentration semiconductor layer into the layer by implantation and diffusion;
The low-concentration semiconductor in which the insulating protective film is selectively etched to open windows in the Schottky junction region portion and the guard ring region portion, and is exposed using the insulating protective film as a mask on one main surface of the semiconductor substrate Forming a Schottky metal on the layer, the guard ring layer and the insulating protective film; and
A mask having a window opened between the Schottky junction region and the guard ring region is formed on the Schottky metal, and the Schottky metal is etched in the mask window to expose the insulating protective film. A method of manufacturing a semiconductor device, comprising: a metal dividing step of separating and dividing the Schottky metal into a main electrode layer in the Schottky junction region and a sub electrode layer in the guard ring region.

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