CN110010508A - A method of passivation layer is solved to power device reliability effect - Google Patents

A method of passivation layer is solved to power device reliability effect Download PDF

Info

Publication number
CN110010508A
CN110010508A CN201910282761.3A CN201910282761A CN110010508A CN 110010508 A CN110010508 A CN 110010508A CN 201910282761 A CN201910282761 A CN 201910282761A CN 110010508 A CN110010508 A CN 110010508A
Authority
CN
China
Prior art keywords
region
area
termination environment
passivation layer
kai
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910282761.3A
Other languages
Chinese (zh)
Inventor
张二雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Rui Jun Semiconductor Ltd By Share Ltd
Original Assignee
Shenzhen Rui Jun Semiconductor Ltd By Share Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Rui Jun Semiconductor Ltd By Share Ltd filed Critical Shenzhen Rui Jun Semiconductor Ltd By Share Ltd
Priority to CN201910282761.3A priority Critical patent/CN110010508A/en
Publication of CN110010508A publication Critical patent/CN110010508A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3171Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

The present invention provides a kind of solution passivation layer to the method for power device reliability effect, power device surface includes cellular region and termination environment, the cellular region is divided into the region GATE and the region Source again, open region is carved in the region GATE and the region Source in cellular region, remaining cellular region and termination environment all cover passivation layer, the termination environment except the region passivation layer Gate and the region source carve open a fritter for encapsulate after in addition to lead, one or more lesser areas Ke Kai are opened in termination environment simultaneously, the each area Ke Kai 1um ~ 20um wide, the area in the area Zong Kekai is less than the half of termination environment area;The film internal stress and mobile ion for discharging termination environment passivation layer, greatly reduce influence of the passivation layer to termination environment, component failure caused by solving because of mobile ion and stress problem greatly promotes the function and reliability of device.

Description

A method of passivation layer is solved to power device reliability effect
Technical field
The invention belongs to the passivating structures of semiconductor chip fabrication process technical field, especially power device, to function The solution of the integrity problem of rate device.
Background technique
Semiconductor power device is because possessing high switching speed, high voltage, a series of advantage such as good thermal stability, when It is preceding to be widely used under the working environment of all kinds of complexity, such as Industry Control, power supply, portable electronics, consumer electronics, The fields such as automotive electronics and Aeronautics and Astronautics.But it since the environment that power device is worked is complicated, is easy by extraneous factor Interference, such as steam, machinery scratch, high temperature etc., cause the electrology characteristic of device to generate offset, make the performance of the device of device significantly It reduces or fails, surface passivation technique is the weight for protecting device inside to influence from extraneous factor that grows up in the latest 20 years Technology is wanted, is had very great significance to reliability and the stability tool for promoting device.
However passivation layer technology is in the manufacturing process of semiconductor devices, it is unavoidable can introduce some mobile ions and Stress between film layer, although reducing mobile ion and stress mainly by technique adjustment at this stage, technique adjustment is to it after all Improve it is limited, it is also unavoidable to draw so while passivation layer technology brings protection and improving stability, reliability to device The stress between mobile ion and film layer is entered, termination environment surface leakage can be caused after mobile ion and stress reach to a certain degree Lead to component failure, it is most easy to crack especially at the high step in termination environment to cause to fail, therefore some producers are because of mobile ion and stress Operation passivation layer is directly abandoned in influence to device reliability, so that its products application environment and the market competitiveness be made to drop significantly It is low.
Passivation layer mainly exempts from extraneous factor interference to the protection of device surface and causes to fail, therefore as complete as possible on being laid out Device surface is protected in face, and at present for power device passivation layout layer, there are mainly two types of:
GATE region and Source region of the layout 1. in cellular region only carve and open a zonule, for drawing when subsequent encapsulation Line, remaining region (cellular region and termination environment) all cover passivation layer;
The region Gate that layout 2. is located in cellular region, which is only carved, opens a zonule, and around the area Gate Ke Kai and finger areas covers Passivation layer, the region Source are all carved and are opened, and lead when subsequent encapsulation is used for, and termination environment all covers passivation layer.
Both the above layout is since entire termination environment is all covered by a passivation layer, and covering surface is larger, in manufacturing process therewith The mobile ion and stress of introducing are also larger, and termination environment surface leakage can be caused to cause component failure, therefore solve the problems, such as that this is carved not Rong Huan.
Summary of the invention
The technical problem to be solved by the present invention is to change the layout of passivation layer by change, solve because of mobile ion and stress Component failure caused by problem greatly promotes the function and reliability of device.
In order to solve the above technical problems, a kind of method for solving passivation layer to power device reliability effect of the present invention, function Rate device surface includes cellular region and termination environment, and the cellular region is divided into the region GATE and the region Source again, is located at cellular region Open region is carved in the interior region GATE and the region Source, and all covering passivation layer, feature exist for remaining cellular region and termination environment In, the termination environment except the region passivation layer Gate and the region source carve open a fritter for encapsulate after in addition to lead, while at end Petiolarea opens one or more lesser areas Ke Kai, each area Ke Kai 1um ~ 20um wide, preferably 10 um, the area in the area Zong Kekai Less than the half of termination environment area.In addition in termination environment, sequentially deposited oxide layer and silicon nitride form passivation layer;In the terminal Area surface grows oxide layer, and for the dielectric layer deposition in the oxide layer, the dielectric layer includes fairlead, said metal layer It is deposited on dielectric layer, forms Gate area tracks port and Source area tracks port, the passivation layer are deposited on institute It states on metal layer and dielectric layer;And the welding window of subsequent package lead is formed on the passivation layer.
The purpose for opening area this moment mainly discharges passivation layer large area bring film internal stress and mobile ion, can be significantly The influence of film internal stress and mobile ion to termination environment is reduced, to greatly promote the reliability of device.
At least one continuous area Ke Kai is arranged in design concept according to the present invention, termination environment of the present invention, in this approach 2 or multiple areas Ke Kai can be increased to.
Multiple discontinuous areas Ke Kai are arranged in design concept according to the present invention, termination environment of the present invention, and the method is at least Increase to 2 or multiple areas Ke Kai.
Design concept according to the present invention, the continuous area Ke Kai is arranged in termination environment of the present invention simultaneously and discontinuous quarter opens Area, and multiple areas Ke Kai can be increased.
The discontinuous area Ke Kai of design concept according to the present invention, termination environment of the present invention is distributed in the four of cellular region In week, the area same position Ke Kai, which moves in parallel, can make up the closed area Ke Kai.
Compared with prior art, the present invention have it is following the utility model has the advantages that release termination environment passivation layer film internal stress and can Dynamic ion, greatly reduces influence of the passivation layer to termination environment, component failure caused by solving because of mobile ion and stress problem, Greatly promote the function and reliability of device.
Detailed description of the invention
Fig. 1 is the layout structure schematic diagram of present invention layout 1;
Fig. 2 is the layout structure schematic diagram of present invention layout 2;
Fig. 3 is one of layout structure schematic diagram of the present invention;
Fig. 4 is the two of layout structure schematic diagram of the present invention;
Fig. 5 is the three of layout structure schematic diagram of the present invention;
Fig. 6 is the four of layout structure schematic diagram of the present invention;
Fig. 7 is the five of layout structure schematic diagram of the present invention;
Fig. 8 is the six of layout structure schematic diagram of the present invention;
Fig. 9 is the seven of layout structure schematic diagram of the present invention;
Figure 10 is the eight of layout structure schematic diagram of the present invention.
Specific embodiment
Firstly, it is necessary to be illustrated, the present invention is a kind of to solve passivation layer to the method for power device reliability effect, Power device surface includes cellular region and termination environment, and the cellular region is divided into the region GATE and the region Source again, is located at cellular Open region is carved in the region GATE and the region Source in area, remaining cellular region and termination environment all cover passivation layer, such as Fig. 3 institute Show, the termination environment except the region passivation layer Gate and the region source carve open a fritter for encapsulate after in addition to lead, while at end Petiolarea opens one or more lesser areas Ke Kai, each area Ke Kai 1um ~ 20um wide, preferably 10 um, the area in the area Zong Kekai Less than the half of termination environment area.In addition in termination environment, sequentially deposited oxide layer and silicon nitride form passivation layer;In the terminal Area surface grows oxide layer, and for the dielectric layer deposition in the oxide layer, the dielectric layer includes fairlead, said metal layer It is deposited on dielectric layer, forms Gate area tracks port and Source area tracks port, the passivation layer are deposited on institute It states on metal layer and dielectric layer;And the welding window of subsequent package lead is formed on the passivation layer.
The purpose for opening area this moment mainly discharges passivation layer large area bring film internal stress and mobile ion, can be significantly The influence of film internal stress and mobile ion to termination environment is reduced, to greatly promote the reliability of device.
At least one continuous area Ke Kai is arranged in design concept according to the present invention, termination environment of the present invention, in this approach 2 or multiple areas Ke Kai can be increased to.
Multiple discontinuous areas Ke Kai are arranged in design concept according to the present invention, termination environment of the present invention, and the method is at least Increase to 2 or multiple areas Ke Kai.
Design concept according to the present invention, the continuous area Ke Kai is arranged in termination environment of the present invention simultaneously and discontinuous quarter opens Area, and multiple areas Ke Kai can be increased.
The discontinuous area Ke Kai of design concept according to the present invention, termination environment of the present invention is distributed in the four of cellular region In week, the area same position Ke Kai, which moves in parallel, can make up the closed area Ke Kai.
In a word: combining in various ways, as long as the area ring region You Kekai, quantity can be 1 or multiple, can be continuous Or it is discontinuous, the area Zong Kekai area is less than the half of termination environment area, is both needed to the protection by this patent.

Claims (5)

1. a kind of solution passivation layer is to the method for power device reliability effect, power device surface includes cellular region and terminal Area, the cellular region are divided into the region GATE and the region Source again, the region GATE and the region Source in cellular region Open region is carved, remaining cellular region and termination environment all cover passivation layer, and in process of production, foreign ion enters cellular region and end Petiolarea causes the accumulation of electronics, directional profile under the action of electric field such as electronics, mobile ion in semiconductor or insulating materials And certain internal electric field is formed to change the intrinsic property of material, especially under high temperature environment, different materials level internal Between the coefficient of expansion will lead to higher device temperature work when level part stress it is excessive, which is characterized in that the termination environment except passivation The layer region Gate and the region source carve open a fritter for encapsulate after outside lead, while termination environment open one or more compared with The area little Ke Kai, each area Ke Kai 1um ~ 20um wide, the area in the area Zong Kekai are less than the half of termination environment area;In addition at end Sequentially deposited oxide layer and silicon nitride form passivation layer to petiolarea;Oxide layer is grown on the termination environment surface, the dielectric layer forms sediment Product is in the oxide layer, and the dielectric layer includes fairlead, and said metal layer is deposited on dielectric layer, forms the region Gate Lead port and Source area tracks port, the passivation layer are deposited on the metal layer and dielectric layer;And described blunt Change the welding window that subsequent package lead is formed on layer.
2. a kind of passivation layer that solves as described in claim 1 is to the method for power device reliability effect, which is characterized in that institute It states termination environment and at least one continuous area Ke Kai is set.
3. a kind of passivation layer that solves as described in claim 1 is to the method for power device reliability effect, which is characterized in that institute It states termination environment and multiple discontinuous areas Ke Kai is set.
4. a kind of passivation layer that solves as described in claim 1 is to the method for power device reliability effect, which is characterized in that institute It states termination environment while the continuous area Ke Kai and the discontinuous area Ke Kai is set.
5. a kind of passivation layer that solves as claimed in claim 3 is to the method for power device reliability effect, which is characterized in that institute The discontinuous area Ke Kai for stating termination environment is distributed in the surrounding of cellular region, and the area same position Ke Kai, which moves in parallel, can make up an envelope The area Bi Kekai.
CN201910282761.3A 2019-04-10 2019-04-10 A method of passivation layer is solved to power device reliability effect Pending CN110010508A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910282761.3A CN110010508A (en) 2019-04-10 2019-04-10 A method of passivation layer is solved to power device reliability effect

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910282761.3A CN110010508A (en) 2019-04-10 2019-04-10 A method of passivation layer is solved to power device reliability effect

Publications (1)

Publication Number Publication Date
CN110010508A true CN110010508A (en) 2019-07-12

Family

ID=67170711

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910282761.3A Pending CN110010508A (en) 2019-04-10 2019-04-10 A method of passivation layer is solved to power device reliability effect

Country Status (1)

Country Link
CN (1) CN110010508A (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1190796A (en) * 1996-10-03 1998-08-19 国际商业机器公司 Inorganic package layer for sealing organic layer and making method thereof
CN103579322A (en) * 2013-11-13 2014-02-12 国家电网公司 IGBT device capable of improving switch-on and switch-off speed and switch-on and switch-off uniformity and manufacturing method thereof
CN106098572A (en) * 2016-08-23 2016-11-09 全球能源互联网研究院 A kind of manufacturing method of passivation layer and high-voltage semi-conductor power device
CN106252244A (en) * 2016-09-22 2016-12-21 全球能源互联网研究院 A kind of terminal passivating method and semiconductor power device
CN107768260A (en) * 2016-08-22 2018-03-06 全球能源互联网研究院 A kind of plane terminal passivating method and semiconductor power device
CN208674124U (en) * 2018-08-31 2019-03-29 江苏丽隽功率半导体有限公司 A kind of passivation layer structure of field-effect tube

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1190796A (en) * 1996-10-03 1998-08-19 国际商业机器公司 Inorganic package layer for sealing organic layer and making method thereof
CN103579322A (en) * 2013-11-13 2014-02-12 国家电网公司 IGBT device capable of improving switch-on and switch-off speed and switch-on and switch-off uniformity and manufacturing method thereof
CN107768260A (en) * 2016-08-22 2018-03-06 全球能源互联网研究院 A kind of plane terminal passivating method and semiconductor power device
CN106098572A (en) * 2016-08-23 2016-11-09 全球能源互联网研究院 A kind of manufacturing method of passivation layer and high-voltage semi-conductor power device
CN106252244A (en) * 2016-09-22 2016-12-21 全球能源互联网研究院 A kind of terminal passivating method and semiconductor power device
CN208674124U (en) * 2018-08-31 2019-03-29 江苏丽隽功率半导体有限公司 A kind of passivation layer structure of field-effect tube

Similar Documents

Publication Publication Date Title
EP2068373B1 (en) Solar cell module
CN103594365A (en) A method for forming a PMOS transistor
CN105118775A (en) A shield grid transistor formation method
CN110010508A (en) A method of passivation layer is solved to power device reliability effect
CN102184868A (en) Method for improving reliability of apex gate oxide of trench gate
CN1832148A (en) Method of manufacturing a flash memory device
CN102487050B (en) Power semiconductor and manufacture method thereof
WO2011116762A3 (en) Method for producing a semiconductor solar cell
CN107946306A (en) Three-dimensional storage organization production method, storage organization, memory and electronic equipment
CN208674124U (en) A kind of passivation layer structure of field-effect tube
CN113054037B (en) Fast recovery diode chip and manufacturing method thereof
CN101819935A (en) Composite plane terminal passivating method for controllable silicon device
CN205219470U (en) Slicer improvement guide pulley
CN105789063A (en) Semiconductor device and fabrication method thereof
CN203895468U (en) PID effect resistance solar energy cell
CN103137544A (en) Semi-conductor chip structure and manufacture method of metal fuse in chip
CN105047549A (en) Method for reducing high-k metal gate device threshold voltage fluctuations by using redundant silicon technology
CN204029776U (en) For the processing unit (plant) of semiconductor chip
CN104183609A (en) Semiconductor device and manufacturing method thereof
CN102623326B (en) Method for fabricating dielectric layer
CN206340537U (en) A kind of aluminium oxide passivation structure
CN205248281U (en) Ditch cell type FRD chip
CN104485329A (en) ESD protection device of IGBT structure and with high maintaining voltage
CN110690160A (en) Chip protection structure and manufacturing method thereof
CN106653951B (en) Packaging method of braided structure thin cable for space solar cell array

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20190712

RJ01 Rejection of invention patent application after publication