CN106098572A - A kind of manufacturing method of passivation layer and high-voltage semi-conductor power device - Google Patents
A kind of manufacturing method of passivation layer and high-voltage semi-conductor power device Download PDFInfo
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- CN106098572A CN106098572A CN201610704091.6A CN201610704091A CN106098572A CN 106098572 A CN106098572 A CN 106098572A CN 201610704091 A CN201610704091 A CN 201610704091A CN 106098572 A CN106098572 A CN 106098572A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
Abstract
The invention provides a kind of manufacturing method of passivation layer and high-voltage semi-conductor power device, described method includes by being screen printed onto coating polyimide glue on high-voltage semi-conductor power device；Polyimides glue is carried out front baking and solidify to form polyimide covercoat；High-voltage semi-conductor power device uses said method manufacture.Compared with prior art, a kind of manufacturing method of passivation layer of present invention offer and high-voltage semi-conductor power device, not only increase the work efficiency of semiconductor power device passivation layer manufacture and reduce job costs, also improving the job stability of high-voltage semi-conductor power device.
Description
Technical field
The present invention relates to high-voltage semi-conductor power device fabricating technology field, be specifically related to a kind of passivation layer manufacturer
Method and high-voltage semi-conductor power device.
Background technology
In order to avoid semiconductor power device is polluted or anti-with some composition generation chemistry in surrounding by foreign ion
Answer and cause its surface electric property to change, need in semiconductor power device, arrange passivation layer, with shielding from outward
The impact on boundary, it is ensured that it can be stablized and work reliably.But these foreign ions especially sodium ion moves in the passivation layer
Dynamic meeting causes electron accumulation, affects electric field and the distribution on semiconductor power device surface, and then causes semiconductor power device work
When making, leakage current increases and breakdown characteristics is degenerated.
When high-voltage semi-conductor power device is operated under high temperature and high pressure environment, the foreign ion in its passivation layer can become more
Add active, carry out redistributing so that the surface field of high-voltage semi-conductor power device changes by electric field action, breakdown potential
Pressure instability occurs that creep, leakage current continue to increase and ultimately results in component failure.Therefore, blunt to high-voltage semi-conductor power device
Change layer to need to carry out more perfect Passivation Treatment so that it is possess stronger anti-introduced contaminants ionic soil ability and at high temperature height
Stable breakdown voltage and leakage current is kept under pressure ring border.
At present, the passivation layer technique of high-voltage semi-conductor power device mainly uses following step:
1, silicon dioxide layer is grown in surface of silicon, and at its surface deposition dielectric layer；
2, at dielectric layer surface deposit silicon nitride layer；
3, on silicon nitride layer, polyimides is processed.
Wherein, the processing technique of polyimides is similar with photoresist process, including gluing, front baking, photoetching, develops and solidifies
Etc. operation, complex steps and there is bigger uncontrollable factor probability.Meanwhile, the polyimides of above-mentioned technique manufacture is used also to have
There is following shortcoming: easily fall off, affect the electrical property of metal electrode quality and device；The course of processing is only capable of realizing monolithic every time
The processing operation of wafer, production efficiency is low, and cost is high；Conventional lithographic machine performance is relatively low to be less than the thickness after polyimides processing
15um, it is impossible to meet high-voltage semi-conductor power device applications performance requirement when high temperature and high pressure environment.
Summary of the invention
In order to overcome the defect of prior art, the invention provides a kind of manufacturing method of passivation layer and high-voltage semi-conductor power
Device.
First aspect, in the present invention, the technical scheme of a kind of manufacturing method of passivation layer is:
Described method includes:
By being screen printed onto coating polyimide glue on high-voltage semi-conductor power device；
Described polyimides glue is carried out front baking and solidify to form polyimide covercoat.
The optimal technical scheme that the present invention further provides is: described coating polyamides Asia on high-voltage semi-conductor power device
Amine glue includes:
By being screen printed onto the metal electrode of described high-voltage semi-conductor power device and coating polyamides in the plane
Imines glue, and welding window is formed on the surface of described metal electrode.
The optimal technical scheme that the present invention further provides is: described coating polyamides Asia on high-voltage semi-conductor power device
Amine glue includes:
At metal electrode and institute's deposition silicon nitride film layer in the plane thereof of described high-voltage semi-conductor power device and right
Described silicon nitride film layer carries out photoetching and etching forms welding window；
By being screen printed onto coating polyimide glue on described silicon nitride film layer.
The optimal technical scheme that the present invention further provides is: described coating polyamides Asia on high-voltage semi-conductor power device
Include before amine glue:
Growing silicon oxide thin layer on the silicon substrate of described high-voltage semi-conductor power device, and to described silicon oxide film
Layer carries out photoetching and etching is formed with source region window；
Dielectric layer deposited on the surface of described silicon oxide film layer, and described dielectric layer is carried out photoetching and etching formation
Contact hole；
Deposited metal on described dielectric layer, described metal level insert downwards described contact hole and with described silicon substrate
Active region contact；Described metal level is carried out photoetching and etching forms described metal electrode.
The optimal technical scheme that the present invention further provides is: described included by screen-printing deposition polyimides glue:
Silk screen arranges multiple alignment mark, described alignment mark and wafer one_to_one corresponding to be processed；
Described silk screen is arranged according to alignment mark the top of described wafer to be processed；
Coating polyimide glue on described silk screen, described polyimides glue is deposited on metal electrode and institute thereof through silk screen
In the plane or on silicon nitride film layer.
The optimal technical scheme that the present invention further provides is: described according to alignment mark, silk screen is arranged in crystalline substance to be processed
Include before the top of circle:
Adjust the spacing of described silk screen and wafer to be processed；
Described spacing range is 5～100um.
The optimal technical scheme that the present invention further provides is:
The temperature of described front baking is 70～130 DEG C, and the time of described front baking is 1～5min.
The optimal technical scheme that the present invention further provides is:
The temperature of described solidification is 250～450 DEG C, and the time of described solidification is 30～100min.
Second aspect, in the present invention, the technical scheme of a kind of high-voltage semi-conductor power device is:
Silicon substrate；
Silicon oxide film layer, described silicon oxide film layer is deposited on described silicon substrate；
Dielectric layer, described dielectric layer deposition is on described silicon oxide film layer, and described dielectric layer includes contact hole；
Metal level, described metal level is deposited on described dielectric layer, and inserts downwards described contact hole and serve as a contrast with described silicon
The active region contact at the end；
Polyimide covercoat, described polyimide covercoat is deposited on described metal level and at it by silk screen printing
Surface forms welding window.
The third aspect, in the present invention, the technical scheme of another kind of high-voltage semi-conductor power device is:
Described high-voltage semi-conductor power device includes:
Silicon substrate；
Silicon oxide film layer, described silicon oxide film layer is deposited on described silicon substrate；
Dielectric layer, described dielectric layer deposition is on described silicon oxide film layer, and described dielectric layer includes contact hole；
Metal level, described metal level is deposited on described dielectric layer, and inserts downwards described contact hole and serve as a contrast with described silicon
The active region contact at the end；
Silicon nitride film layer, described silicon nitride film layer be deposited on described metal level and institute in the plane, described nitridation
Silicon membrane layer includes welding window；
Polyimide covercoat, described polyimide covercoat is deposited on described silicon nitride film layer by silk screen printing
On.
Compared with immediate prior art, the invention has the beneficial effects as follows:
1, a kind of manufacturing method of passivation layer that the present invention provides, uses method for printing screen deposit polyimide covercoat,
And then it is carried out front baking and solidify to form polyimide covercoat, work flow is less and is prevented from polyimide covercoat
Come off and improve the functional reliability of semiconductor power device；Meanwhile, polyimides can be adjusted by method for printing screen to protect
The thickness of layer so that it is meet performance requirement when semiconductor power device is applied to high-pressure high-temperature environment；By silk screen printing side
Method can also carry out polyimide covercoat processing to many wafers simultaneously, improves the work that semiconductor power device passivation layer manufactures
Make efficiency and reduce job costs；
2, a kind of high-voltage semi-conductor power device that the present invention provides, can comprise by silicon oxide film layer, dielectric layer and
Polyimide covercoat composition composite construction or by silicon oxide film layer, dielectric layer, silicon nitride film layer and polyimides
The composite construction of protective layer composition, wherein polyimide covercoat is as the protective film of high-voltage semi-conductor power device passivation layer
Layer, improves the reliability of high-voltage semi-conductor power device so that it is can also keep stable when being applied to high temperature and high pressure environment
Breakdown voltage and leakage current.
Accompanying drawing explanation
Fig. 1: a kind of manufacturing method of passivation layer implementing procedure schematic diagram in the embodiment of the present invention；
Fig. 2: silicon substrate active area schematic diagram in the embodiment of the present invention；
Fig. 3: embodiment of the present invention dielectric layer schematic diagram；
Fig. 4: contact hole schematic diagram in the embodiment of the present invention；
Fig. 5: metal electrode schematic diagram in the embodiment of the present invention；
Fig. 6: silicon nitride film layer schematic diagram in the embodiment of the present invention；
Fig. 7: a kind of polyimide covercoat schematic diagram in the embodiment of the present invention；
Fig. 8: another kind of polyimide covercoat schematic diagram in the embodiment of the present invention；
Fig. 9: silicon nitride film layer schematic top plan view in individual devices in the embodiment of the present invention；
Figure 10: silk screen top view schematic diagram corresponding with individual devices in the embodiment of the present invention；
Figure 11: silicon nitride film layer schematic top plan view in partial wafer in the embodiment of the present invention；
Figure 12: silk screen top view schematic diagram corresponding with partial wafer in the embodiment of the present invention；
Wherein, 11: silicon substrate N-layer；12: silicon substrate N+ layer；13:P+ district；21: silicon oxide film layer；22: dielectric layer；
23: metal level；24: silicon nitride film layer；25: polyimide covercoat；31: baffle plate；32: silk screen.
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely illustrated, it is clear that described embodiment is
The a part of embodiment of the present invention rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under not making creative work premise, broadly falls into the scope of protection of the invention.
Below in conjunction with the accompanying drawings, a kind of manufacturing method of passivation layer provided the embodiment of the present invention illustrates.
Fig. 1 is a kind of manufacturing method of passivation layer implementing procedure schematic diagram in the embodiment of the present invention, as it can be seen, the present embodiment
Middle manufacturing method of passivation layer comprises the steps:
Step S101: by being screen printed onto coating polyimide glue on high-voltage semi-conductor power device.
The present embodiment can use following two kinds of embodiments to high-voltage semi-conductor power device coating polyimide glue,
Specifically:
First embodiment
By being screen printed onto metal electrode and institute's coating polyimide in the plane thereof of high-voltage semi-conductor power device
Glue, and welding window is formed on the surface of metal electrode.
Second embodiment
At metal electrode and institute's deposition silicon nitride film layer in the plane thereof, and silicon nitride film layer is carried out photoetching and quarter
Erosion forms welding window.
Fig. 6 is silicon nitride film layer schematic diagram in the embodiment of the present invention, as it can be seen, metal electrode 23 forms sediment in the present embodiment
Amass on dielectric layer 22 and insert downwards contact hole and active region contact.At metal electrode 23 and place plane i.e. metal electrode thereof
23 and dielectric layer 22 on deposition silicon nitride film layer 24, silicon nitride film layer 24 is carried out photoetching and etching formed welding window,
A part for metal electrode 24 is come out by welding window.
Step S102: and polyimides glue is carried out front baking and solidify to form polyimide covercoat.
Fig. 7 is a kind of polyimide covercoat schematic diagram in the embodiment of the present invention, as it can be seen, polyamides is sub-in the present embodiment
Amine protective layer 25 is deposited on silicon nitride film layer 24.
Fig. 8 is another kind of polyimide covercoat schematic diagram in the embodiment of the present invention, as it can be seen, polyamides in the present embodiment
Imines protective layer 25 is deposited on metal electrode 23.
The present embodiment uses method for printing screen coating polyimide protective layer, and then it is carried out front baking and solidification shape
Becoming polyimide covercoat, work flow is less and is prevented from polyimide covercoat and comes off and improve semiconductor power device
Functional reliability.Meanwhile, the thickness of polyimide covercoat can also be adjusted by method for printing screen so that it is meet quasiconductor
Power device applications performance requirement when high-pressure high-temperature environment；Multiple wafers can also be entered by method for printing screen simultaneously
Row polyimide covercoat is processed, and improves the work efficiency of semiconductor power device passivation layer manufacture and reduces work
This.
Further, the present embodiment also includes before coating polyimide glue on high-voltage semi-conductor power device following
Implement step, specifically:
1, growing silicon oxide thin layer on a silicon substrate, and silicon oxide film layer is carried out photoetching and etching is formed with source region
Window.
Fig. 2 is silicon substrate active area schematic diagram in the embodiment of the present invention, as it can be seen, silicon substrate includes silicon in the present embodiment
Substrate N-floor 11, silicon substrate N+ floor 12 and P+ district 13.Silicon oxide film layer 21 deposits on a silicon substrate, and active area window is silicon lining
The window of the active area at the end, it is simple to metal electrode deposits on the active area.
2, dielectric layer deposited on the surface of silicon oxide film layer, and dielectric layer is carried out photoetching with etching formed contact
Hole.
Fig. 3 is embodiment of the present invention dielectric layer schematic diagram, as it can be seen, the present embodiment dielectric layer 22 is deposited on oxidation
On the surface of the combinative structure of silicon membrane layer 21 and active area composition.
Fig. 4 is contact hole schematic diagram in the embodiment of the present invention, as it can be seen, dielectric layer 22 is carried out photoetching in the present embodiment
Forming one or more contact holes with etching, active area is by this contact holes exposing out, it is simple to electrode metal deposits.
3, deposited metal on dielectric layer, metal level inserts downwards contact hole and the active region contact with silicon substrate；Right
Metal level carries out photoetching and etching forms metal electrode.
Fig. 5 is metal electrode schematic diagram in the embodiment of the present invention, as it can be seen, metal level is deposited on medium in the present embodiment
On layer 22, a portion metal level is inserted downwards in contact hole and active region contact.Finally metal level is carried out photoetching and
Etching forms metal electrode 23.
In the present embodiment, silicon oxide film layer is as semiconductor power device passivation layer, be possible to prevent silicon substrate by impurity from
Son pollute or with some composition generation chemical reaction in surrounding and cause its surface electric property to change.
Further, the present embodiment can use following enforcement step by screen-printing deposition polyimides glue:
1, multiple alignment mark is set on silk screen, alignment mark and wafer one_to_one corresponding to be processed.In the present embodiment
Alignment mark is set on silk screen and can ensure that when processing the passivation layer of single or multiple semiconductor power devices, exactly often
Deposit polyimide layer on individual wafer to be processed, improve accuracy and the reliability of passivation layer processing.
Fig. 9 is silicon nitride film layer schematic top plan view in individual devices in the embodiment of the present invention, and Figure 10 is that the present invention implements
Silk screen top view schematic diagram corresponding with individual devices in example, as it can be seen, baffle plate 31 is corresponding with metal electrode 23, in silk screen 32
The part do not covered by baffle plate 31 is corresponding with silicon nitride film layer 24.Meanwhile, the metal electricity that baffle plate 31 and welding window expose
Pole 23 is corresponding, metal electrode that the part do not covered by baffle plate 31 in silk screen 32 and welding window do not expose and planar section thereof
Corresponding.
Figure 11 is silicon nitride film layer schematic top plan view in partial wafer in the embodiment of the present invention, and Figure 12 is that the present invention implements
Silk screen top view schematic diagram corresponding with partial wafer in example, as it can be seen, baffle plate 31 and metal electrode 23 one_to_one corresponding, silk screen
The part do not covered by baffle plate 31 in 32 and silicon nitride film layer 24 one_to_one corresponding.Meanwhile, baffle plate 31 exposes with welding window
Metal electrode 23 one_to_one corresponding, the metal electrode that the part do not covered by baffle plate 31 in silk screen 32 and welding window do not expose
And planar section one_to_one corresponding.
2, silk screen is arranged according to alignment mark the top of wafer to be processed.In the present embodiment, silk screen is according to alignment mark
After being arranged in the top of wafer to be processed, each wafer to be processed and the spacing of silk screen should keep identical, so that polyamides
Imine layer is deposited on all of wafer to be processed exactly.
3, coating polyimide glue on silk screen, polyimides glue is deposited on silicon nitride film layer through silk screen.
The present embodiment also needed to before implementing step 2 require to adjust silk according to the actual performance of semiconductor power device
Net and the spacing of wafer to be processed, this spacing range can be 5～100um.
Polyimides glue can be carried out after implementing step 3 front baking by the present embodiment and solidify to form polyimides protection
Layer, wherein the temperature of front baking can be 70～130 DEG C, and the time of front baking can be 1～5min；The temperature of solidification can be 250
～450 DEG C, the time of solidification can be 30～100min.The present embodiment use front baking and two operations of solidification can be formed poly-
Acid imide protective layer, eliminates gluing in traditional handicraft, front baking, photoetching, develops and the operation such as solidification, reduce processing risk.
The invention provides a kind of high-voltage semi-conductor power device and provide specific embodiment.
The present embodiment mesohigh semiconductor power device includes silicon substrate, silicon oxide film layer, dielectric layer, metal level and gathers
Acid imide protective layer.Wherein,
Silicon substrate can be P type substrate, and silicon oxide film layer deposits on a silicon substrate.
Dielectric layer deposition is on silicon oxide film layer, and dielectric layer includes contact hole.
Metal level is deposited on dielectric layer, and inserts downwards contact hole and the active region contact with silicon substrate.
Polyimide covercoat is deposited on the metal layer by silk screen printing and forms welding window, this enforcement on its surface
In example, silk screen printing uses scheme disclosed in above-mentioned manufacturing method of passivation layer to implement.
Silicon oxide film layer, dielectric layer and the composite construction of polyimide covercoat composition, wherein polyamides in the present embodiment
Imines protective layer, as the protecting film layer of high-voltage semi-conductor power device passivation layer, improves high-voltage semi-conductor power device
Reliability so that it is stable breakdown voltage and leakage current can also be kept when being applied to high temperature and high pressure environment.
Present invention also offers a kind of high-voltage semi-conductor power device and provide specific embodiment.
The present embodiment mesohigh semiconductor power device includes silicon substrate, silicon oxide film layer, dielectric layer, metal level, nitrogen
SiClx thin layer and polyimide covercoat.Wherein,
Silicon substrate can be P type substrate, and silicon oxide film layer deposits on a silicon substrate.
Dielectric layer deposition is on silicon oxide film layer, and dielectric layer includes contact hole.
Metal level is deposited on dielectric layer, and inserts downwards contact hole and the active region contact with silicon substrate.
Silicon nitride film layer be deposited on metal level and institute in the plane, silicon nitride film layer includes welding window.
Polyimide covercoat is deposited on silicon nitride film layer by silk screen printing, and in the present embodiment, silk screen printing uses
Scheme disclosed in above-mentioned manufacturing method of passivation layer is implemented.
In the present embodiment, silicon oxide film layer, dielectric layer, silicon nitride film layer and polyimide covercoat composition is compound
Structure, wherein polyimide covercoat is as the protecting film layer of high-voltage semi-conductor power device passivation layer, improves high pressure half
The reliability of conductor power device so that it is stable breakdown voltage and electric leakage can also be kept when being applied to high temperature and high pressure environment
Stream.
Obviously, those skilled in the art can carry out various change and the modification essence without deviating from the present invention to the present invention
God and scope.So, if these amendments of the present invention and modification belong to the scope of the claims in the present invention and equivalent technologies thereof
Within, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. a manufacturing method of passivation layer, it is characterised in that described method includes:
By being screen printed onto coating polyimide glue on high-voltage semi-conductor power device；
Described polyimides glue is carried out front baking and solidify to form polyimide covercoat.
2. a kind of manufacturing method of passivation layer as claimed in claim 1, it is characterised in that described at high-voltage semi-conductor power device
Upper coating polyimide glue includes:
By being screen printed onto metal electrode and institute's coating polyimide in the plane thereof of described high-voltage semi-conductor power device
Glue, and welding window is formed on the surface of described metal electrode.
3. a kind of manufacturing method of passivation layer as claimed in claim 1, it is characterised in that described at high-voltage semi-conductor power device
Upper coating polyimide glue includes:
At metal electrode and institute's deposition silicon nitride film layer in the plane thereof of described high-voltage semi-conductor power device, and to described
Silicon nitride film layer carries out photoetching and etching forms welding window；
By being screen printed onto coating polyimide glue on described silicon nitride film layer.
4. a kind of manufacturing method of passivation layer as claimed in claim 1, it is characterised in that described at high-voltage semi-conductor power device
Include before upper coating polyimide glue:
Growing silicon oxide thin layer on the silicon substrate of described high-voltage semi-conductor power device, and described silicon oxide film layer is entered
Row photoetching and etching are formed with source region window；
Dielectric layer deposited on the surface of described silicon oxide film layer, and described dielectric layer is carried out photoetching with etching formed contact
Hole；
Deposited metal on described dielectric layer, described metal level inserts downwards described contact hole and active with described silicon substrate
District contacts；Described metal level is carried out photoetching and etching forms described metal electrode.
5. a kind of manufacturing method of passivation layer as described in any one of claim 1-3, it is characterised in that described in pass through silk screen printing
Coating polyimide glue includes:
Silk screen arranges multiple alignment mark, described alignment mark and wafer one_to_one corresponding to be processed；
Described silk screen is arranged according to alignment mark the top of described wafer to be processed；
Coating polyimide glue on described silk screen, described polyimides glue is deposited on metal electrode through silk screen and place is put down
On face or on silicon nitride film layer.
6. manufacturing method of passivation layer as claimed in claim 5 a kind of, it is characterised in that described by silk screen according to alignment mark cloth
Include before putting above wafer to be processed:
Adjust the spacing of described silk screen and wafer to be processed；
Described spacing range is 5～100um.
7. a kind of manufacturing method of passivation layer as claimed in claim 1, it is characterised in that
The temperature of described front baking is 70～130 DEG C, and the time of described front baking is 1～5min.
8. a kind of manufacturing method of passivation layer as claimed in claim 1, it is characterised in that
The temperature of described solidification is 250～450 DEG C, and the time of described solidification is 30～100min.
9. a high-voltage semi-conductor power device, it is characterised in that described high-voltage semi-conductor power device includes:
Silicon substrate；
Silicon oxide film layer, described silicon oxide film layer is deposited on described silicon substrate；
Dielectric layer, described dielectric layer deposition is on described silicon oxide film layer, and described dielectric layer includes contact hole；
Metal level, described metal level is deposited on described dielectric layer, and insert downwards described contact hole and with described silicon substrate
Active region contact；
Polyimide covercoat, described polyimide covercoat is deposited on described metal level and on its surface by silk screen printing
Form welding window.
10. a high-voltage semi-conductor power device, it is characterised in that described high-voltage semi-conductor power device includes:
Silicon substrate；
Silicon oxide film layer, described silicon oxide film layer is deposited on described silicon substrate；
Dielectric layer, described dielectric layer deposition is on described silicon oxide film layer, and described dielectric layer includes contact hole；
Metal level, described metal level is deposited on described dielectric layer, and insert downwards described contact hole and with described silicon substrate
Active region contact；
Silicon nitride film layer, described silicon nitride film layer be deposited on described metal level and institute in the plane, described silicon nitride is thin
Film layer includes welding window；
Polyimide covercoat, described polyimide covercoat is deposited on described silicon nitride film layer by silk screen printing.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610704091.6A CN106098572A (en) | 2016-08-23 | 2016-08-23 | A kind of manufacturing method of passivation layer and high-voltage semi-conductor power device |
| PCT/CN2017/093002 WO2018014792A1 (en) | 2016-07-20 | 2017-07-14 | Passivation layer manufacturing method, high-voltage semiconductor power device and front electrode |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610704091.6A CN106098572A (en) | 2016-08-23 | 2016-08-23 | A kind of manufacturing method of passivation layer and high-voltage semi-conductor power device |
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| CN106098572A true CN106098572A (en) | 2016-11-09 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018014792A1 (en) * | 2016-07-20 | 2018-01-25 | 全球能源互联网研究院 | Passivation layer manufacturing method, high-voltage semiconductor power device and front electrode |
| CN108622852A (en) * | 2018-05-21 | 2018-10-09 | 赛莱克斯微系统科技（北京）有限公司 | A method of manufacturing metal pins pad in MEMS structure |
| CN110010508A (en) * | 2019-04-10 | 2019-07-12 | 深圳市锐骏半导体股份有限公司 | A method of passivation layer is solved to power device reliability effect |
| CN107910253B (en) * | 2017-11-15 | 2020-11-20 | 上海华虹宏力半导体制造有限公司 | Polyimide and passivation layer mask combination method |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4906314A (en) * | 1988-12-30 | 1990-03-06 | Micron Technology, Inc. | Process for simultaneously applying precut swatches of precured polyimide film to each semiconductor die on a wafer |
| US6341418B1 (en) * | 1999-04-29 | 2002-01-29 | International Business Machines Corporation | Method for direct chip attach by solder bumps and an underfill layer |
| JP2003273141A (en) * | 2002-03-12 | 2003-09-26 | Fujikura Ltd | Manufacturing method of semiconductor device |
| US20070026631A1 (en) * | 2005-07-29 | 2007-02-01 | Mou-Shiung Lin | Metal pad or metal bump over pad exposed by passivation layer |
| EP1837908A1 (en) * | 2006-03-22 | 2007-09-26 | SEMIKRON Elektronik GmbH & Co. KG | High performance semiconductor component with secondary passivation layer and associated method of manufacture |
| US20130233381A1 (en) * | 2010-09-21 | 2013-09-12 | Pi R&D Co., Ltd. | Polyimide resin composition for use in forming insulation film in photovoltaic cell and method of forming insulation film in photovoltaic cell used therewith |
| CN104201252A (en) * | 2014-09-22 | 2014-12-10 | 苏州阿特斯阳光电力科技有限公司 | PERC (passivated emitter and locally diffused rear contact) solar cell preparation method |
| CN104332403A (en) * | 2013-07-22 | 2015-02-04 | 无锡华润上华半导体有限公司 | Semiconductor power device and manufacturing method thereof |
-
2016
- 2016-08-23 CN CN201610704091.6A patent/CN106098572A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4906314A (en) * | 1988-12-30 | 1990-03-06 | Micron Technology, Inc. | Process for simultaneously applying precut swatches of precured polyimide film to each semiconductor die on a wafer |
| US6341418B1 (en) * | 1999-04-29 | 2002-01-29 | International Business Machines Corporation | Method for direct chip attach by solder bumps and an underfill layer |
| JP2003273141A (en) * | 2002-03-12 | 2003-09-26 | Fujikura Ltd | Manufacturing method of semiconductor device |
| US20070026631A1 (en) * | 2005-07-29 | 2007-02-01 | Mou-Shiung Lin | Metal pad or metal bump over pad exposed by passivation layer |
| EP1837908A1 (en) * | 2006-03-22 | 2007-09-26 | SEMIKRON Elektronik GmbH & Co. KG | High performance semiconductor component with secondary passivation layer and associated method of manufacture |
| US20130233381A1 (en) * | 2010-09-21 | 2013-09-12 | Pi R&D Co., Ltd. | Polyimide resin composition for use in forming insulation film in photovoltaic cell and method of forming insulation film in photovoltaic cell used therewith |
| CN104332403A (en) * | 2013-07-22 | 2015-02-04 | 无锡华润上华半导体有限公司 | Semiconductor power device and manufacturing method thereof |
| CN104201252A (en) * | 2014-09-22 | 2014-12-10 | 苏州阿特斯阳光电力科技有限公司 | PERC (passivated emitter and locally diffused rear contact) solar cell preparation method |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018014792A1 (en) * | 2016-07-20 | 2018-01-25 | 全球能源互联网研究院 | Passivation layer manufacturing method, high-voltage semiconductor power device and front electrode |
| CN107910253B (en) * | 2017-11-15 | 2020-11-20 | 上海华虹宏力半导体制造有限公司 | Polyimide and passivation layer mask combination method |
| CN108622852A (en) * | 2018-05-21 | 2018-10-09 | 赛莱克斯微系统科技（北京）有限公司 | A method of manufacturing metal pins pad in MEMS structure |
| CN108622852B (en) * | 2018-05-21 | 2020-05-12 | 赛莱克斯微系统科技（北京）有限公司 | Method for manufacturing metal pin pad in MEMS structure |
| CN110010508A (en) * | 2019-04-10 | 2019-07-12 | 深圳市锐骏半导体股份有限公司 | A method of passivation layer is solved to power device reliability effect |
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