JP2004014658A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for reducing interferences between a plurality of PIN diode arranged in parallel. <P>SOLUTION: An epitaxial layer (I layer) 2 showing n-type conductivity is formed on a semiconductor substrate 1, and semiconductor regions (P layers) 3 showing p-type conductivity are formed on an upper face side of the I layer 2 and semiconductor regions (N layers) 4 showing n-type conductivity are formed at a periphery by leaving a prescribed distance. First electrodes (anode electrodes) 5 are formed close to the P layers 3 and second electrodes (cathode electrodes) 6 close to the N layers 4. The PIN diodes D1 and D2, which are composed of the P layers 3, the I layer 2 and the N layers 4, are constituted between the first electrodes 5 and the second electrodes 6. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a semiconductor device having a PIN (Positive Intrinsic Negative) diode.
[0002]
[Prior art]
For example, FIG. 6.1, "Basics of Semiconductor Devices", published by McGraw-Hill Book Co., Ltd., issued on Mar. 25, 1986, describes a planar n ⁺ p junction diode made of silicon.
[0003]
The n ⁺ p junction diode is first formed on a relatively heavily doped (eg, 10 ¹⁹ cm ⁻³ ) doped p-type conductive substrate on a relatively lightly doped (eg, 10 ¹⁶ cm ⁻³ ) substrate. Is grown. Next, after forming a silicon oxide film on the surface of the epitaxial film by thermal oxidation treatment, a part of the silicon oxide film is removed to form a window, and then an impurity exhibiting n-type conductivity is formed through the window. By diffusion to form an n ⁺ p junction diode. A plurality of such bondings are simultaneously formed on the substrate.
[0004]
[Problems to be solved by the invention]
The present inventors have studied a PIN diode for an antenna switch or a phase shift. FIG. 8 is a sectional view of a principal part of a semiconductor substrate showing an example of a PIN diode studied by the present inventors.
[0005]
An epitaxial layer (I layer) 52 is formed on the surface of a semiconductor substrate (N layer) 51 having n-type conductivity, and the epitaxial layer 52 has an isolation made of a semiconductor region having n-type conductivity. A semiconductor region (P layer) 54 having p-type conductivity and surrounded by the layer 53 is formed. A p-type conductivity is provided between a first electrode 55 provided in contact with the semiconductor region 54 exhibiting p-type conductivity and a second electrode 56 provided in contact with the back surface of the semiconductor substrate 51. A PIN diode including a semiconductor region (P layer) 54, an epitaxial layer (I layer) 52, and a semiconductor substrate (N layer) 51 is configured.
[0006]
However, the present inventor has found that the following problem occurs when a plurality of PIN diodes having different signal frequencies are arranged in parallel.
[0007]
That is, when the first PIN diode E1 and the second PIN diode E2 having different frequencies of the input signal are simultaneously turned on, the carriers injected into the epitaxial layer 52 spread over the entire epitaxial layer 52. The high-frequency signal S1 of the PIN diode E1 and the high-frequency signal S2 of the second PIN diode E2 may interfere with each other (modulate), causing distortion in the output signal.
[0008]
By increasing the depth of the isolation layer 53, it is possible to prevent interference (modulation) between the high-frequency signal S1 of the first PIN diode E1 and the high-frequency signal S2 of the second PIN diode E2. However, since the isolation layer 53 is formed by introducing impurities into the epitaxial layer 52 by an ion implantation method and then performing a heat treatment, the depth is limited, and when the epitaxial layer 52 is relatively thick, It is considered that it is difficult to prevent the interference (modulation) in the isolation layer 53.
[0009]
An object of the present invention is to provide a technique capable of reducing interference between a plurality of PIN diodes arranged in parallel.
[0010]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0011]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0012]
According to the present invention, an epitaxial layer in which an impurity having n-type conductivity is introduced at a relatively low concentration is formed on a substrate, and an impurity having p-type conductivity has a relatively high concentration on an upper surface side of the epitaxial layer. And a second semiconductor region into which impurities having n-type conductivity are introduced at a relatively high concentration at a predetermined distance from the periphery of the first semiconductor region. The first semiconductor region, the epitaxial layer, and the second semiconductor region constitute a diode.
[0013]
The present invention includes a step of forming an epitaxial layer in which an impurity exhibiting n-type conductivity is introduced at a relatively low concentration on a substrate; a step of forming a first insulating film on the epitaxial layer; Forming a relatively high-concentration first semiconductor region by introducing a p-type conductive impurity into the epitaxial layer through the region from which the first insulating film is removed after removing a part of the insulating film; Forming a second insulating film on the first insulating film; and forming a first and second portions around the first semiconductor region with a predetermined width at a predetermined distance from the first semiconductor region. After removing the insulating film, an impurity exhibiting n-type conductivity is introduced into the epitaxial layer through the region from which the first and second insulating films have been removed to form a second semiconductor region having a relatively high concentration. And a process.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.
[0015]
FIG. 1 is a plan view of a principal part of a semiconductor substrate showing a PIN diode according to an embodiment of the present invention, and FIG. 2 is a sectional view of a principal part of the semiconductor substrate showing a PIN diode along line AA 'in FIG. is there. Although two PIN diodes arranged in parallel are shown in the figure, three or more PIN diodes may be arranged on the substrate. In FIG. 1, a hatched region indicates an N layer that constitutes a part of the PIN diode.
[0016]
An epitaxial layer (hereinafter, referred to as an I layer) 2 having a thickness of about 10 μm and exhibiting n-type conductivity is formed on an upper layer of a semiconductor substrate 1 made of silicon single crystal. In the I layer 2, a semiconductor region (hereinafter, referred to as a P layer) 3 having a rectangular shape having a side of about 50 to 150 μm and exhibiting p-type conductivity is formed. A semiconductor region (hereinafter, referred to as an N layer) 4 having a width of about 50 to 150 μm and exhibiting n-type conductivity is formed. Adjacent P layers 3 are separated at intervals of about 200 to 400 μm, and the depth of P layers 3 is about 5 μm. The depth of the N layer 4 is about 5 to 10 μm, and the N layer 4 may be in contact with the semiconductor substrate 1.
[0017]
Further, both anode and cathode electrodes are formed on the upper surface side of the I layer 2, and a first electrode (anode electrode) 5 contacts the P layer 3 and a second electrode (cathode electrode) 6 contacts the N layer 4. ing. Therefore, PIN diodes D1 and D2 composed of the P layer 3, the I layer 2 and the N layer 4 are formed between the first electrode 5 and the second electrode 6 provided on the upper surface side of the I layer 2. . The impurity concentration of the P layer 3, I layer 2 and the N layer 4, respectively ¹⁰ 20 ^{cm -3,} it can be a 10 13 ^{cm -3} and ¹⁰ 20 ^{cm -3} or so. Note that an insulating film 7 having a thickness of about 2 μm is formed on the I layer 2 so that the first electrode 5 and the I layer 2 or the second electrode 6 and the I layer 2 do not come into contact with each other.
[0018]
As described above, according to the present embodiment, P layer 3 and N layer 4 constituting PIN diodes D1 and D2 are arranged on the upper surface side of I layer 2, and N layer 4 and P layer 3 are closed circuit. By applying a potential, for example, 0.7 V, to the N layer 4, the N layer 4 can be used as a carrier (electron) injection source. Therefore, carriers can be collected in the vicinity of the surface of the I layer 2, and when the N layer 4 reaches the semiconductor substrate 1, the carriers can be stored in the I layer 2 on which the PIN diodes D1 and D2 are formed. . As a result, even if the PIN diodes D1 and D2 are turned on at the same time, it is possible to prevent the carrier from spreading to the entire I layer 2, so that the high-frequency signal S1 of the PIN diode D1 and the high-frequency signal S2 of the PIN diode D2 are mutually connected. Interference can be prevented. As a result, it is possible to improve problems such as distortion of output signals, inter-channel interference, and cross modulation of the semiconductor device having the PIN diodes D1 and D2.
[0019]
Further, since the diode characteristics are controlled by the distance between the P layer 3 and the N layer 4, the influence of the thickness of the I layer 2 on the diode characteristics is reduced. Thereby, the thickness of the I layer 2 can be made relatively thin, and the N layer 4 can be easily formed in contact with the semiconductor substrate 1.
[0020]
Next, a method for manufacturing a PIN diode according to an embodiment of the present invention will be described in the order of steps with reference to the cross-sectional views of main parts of a semiconductor substrate shown in FIGS.
[0021]
First, as shown in FIG. 3, a semiconductor substrate (semiconductor wafer processed into a thin circular plate) 1 made of, for example, an n-type silicon single crystal is prepared. Next, an n-type silicon single crystal film is grown on the surface of the semiconductor substrate 1 by an epitaxial method to form an I layer 2 having an impurity concentration of about 10 ¹³ cm ⁻³ and a thickness of about 10 μm. Next, a silicon oxide film 7a having a thickness of about 1 μm is formed on the surface of the I layer 2 by performing a thermal oxidation treatment.
[0022]
Next, as shown in FIG. 4, after a rectangular hole is opened in a part of the silicon oxide film 7a at an interval of about 200 to 400 μm by dry etching using a resist pattern as a mask, for example, a p-type impurity is formed. Is ion-implanted into the I layer 2 and then heat-treated to form a P layer 3 having an impurity concentration of about 10 ²⁰ cm ⁻³ and a depth of about 5 μm. One side of the P layer 3 can be a rectangle of about 50 to 150 μm.
[0023]
Next, as shown in FIG. 5, a silicon oxide film 7b having a thickness of about 1 μm is deposited on the silicon oxide film 7a by, for example, a CVD (Chemical Vapor Deposition) method.
[0024]
Next, as shown in FIG. 6, the silicon oxide films 7a and 7b around the P layer 3 are separated by a predetermined distance from the P layer 3 by dry etching using a resist pattern as a mask and having a width of about 50 to 150 μm. Is removed. Subsequently, an n-type impurity is ion-implanted into the I layer 2 and then heat treatment is performed to form an N layer 4 having an impurity concentration of about 10 ²⁰ cm ⁻³ and a depth of about 5 to 10 μm.
[0025]
Next, as shown in FIG. 7, after removing the silicon oxide film 7b above the P layer 3, a metal film, for example, an aluminum alloy film is deposited on the silicon oxide film 7b. Thereafter, the metal film is processed by dry etching using the resist pattern as a mask to form a first electrode 5 connected to the P layer 3 and a second electrode 6 connected to the N layer 4. Thereby, the PIN diode is substantially completed.
[0026]
As described above, the invention made by the inventor has been specifically described based on the embodiment of the invention. However, the invention is not limited to the embodiment, and can be variously modified without departing from the gist of the invention. Needless to say, there is.
[0027]
For example, in the above embodiment, the case where the present invention is applied to a PIN diode has been described. A similar effect can be obtained.
[0028]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0029]
By arranging the P layer and the N layer constituting the PIN diode on the upper surface side of the I layer and applying a potential to the N layer to use the N layer as a cathode, carriers can be collected near the surface of the I layer. Accordingly, even if a plurality of PIN diodes are turned on at the same time, the spread of carriers to the entire I layer can be prevented, so that high-frequency signals can be prevented from interfering with each other between the plurality of PIN diodes.
[Brief description of the drawings]
FIG. 1 is a plan view of a principal part of a semiconductor substrate showing a PIN diode according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of a principal part of the semiconductor substrate showing a PIN diode taken along the line AA ′ of FIG. 1;
FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the PIN diode according to one embodiment of the present invention;
FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the PIN diode according to one embodiment of the present invention;
FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the PIN diode according to one embodiment of the present invention;
FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the PIN diode according to one embodiment of the present invention;
FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the PIN diode according to one embodiment of the present invention;
FIG. 8 is a sectional view of a principal part of a semiconductor substrate showing a PIN diode studied by the present invention.
[Explanation of symbols]
Reference Signs List 1 semiconductor substrate 2 epitaxial layer (I layer)
3 Semiconductor region showing p-type conductivity (P layer)
4 Semiconductor region showing n-type conductivity (N layer)
5 First electrode 6 Second electrode 7 Insulating film 7a Silicon oxide film 7b Silicon oxide film 51 Semiconductor substrate (N layer)
52 Epitaxial layer (I layer)
53 Isolation layer 54 Semiconductor region showing p-type conductivity (P layer)
55 first electrode 56 second electrode D1 PIN diode D2 PIN diode S1 high frequency signal S2 high frequency signal E1 first PIN diode E2 second PIN diode

Claims (5)

An epitaxial layer in which an impurity having a first conductivity type is introduced at a relatively low concentration is formed on a substrate, and an impurity having a second conductivity type different from the first conductivity type is formed on an upper surface of the epitaxial layer. The first conductivity type is introduced at a relatively high concentration, and the impurity having the first conductivity type is introduced at a relatively high concentration at a predetermined distance around the first semiconductor region and the periphery of the first semiconductor region. A second semiconductor region is formed,
A semiconductor device comprising: a diode including the first semiconductor region, the epitaxial layer, and the second semiconductor region. An epitaxial layer in which an impurity having a first conductivity type is introduced at a relatively low concentration is formed on a substrate, and an impurity having a second conductivity type different from the first conductivity type is formed on an upper surface of the epitaxial layer. The first conductivity type is introduced at a relatively high concentration, and the impurity having the first conductivity type is introduced at a relatively high concentration at a predetermined distance around the first semiconductor region and the periphery of the first semiconductor region. A second semiconductor region is formed,
A semiconductor device comprising a diode comprising the first semiconductor region, the epitaxial layer, and the second semiconductor region, wherein the second semiconductor region reaches the substrate. A first semiconductor region into which an impurity having a first conductivity type is introduced on an upper surface side of a substrate; and an impurity having a second conductivity type different from the first conductivity type around the first semiconductor region. And a second semiconductor region into which is introduced.
A semiconductor device comprising a diode including the first semiconductor region and the second semiconductor region. (A) forming, on a substrate, an epitaxial layer into which impurities having a first conductivity type are introduced at a relatively low concentration;
(B) forming a first insulating film on the epitaxial layer;
(C) After removing a part of the first insulating film, an impurity of a second conductivity type different from the first conductivity type is introduced into the epitaxial layer through a region where the first insulating film is removed. Forming a relatively high concentration first semiconductor region;
(D) forming a second insulating film on the first insulating film;
(E) at a predetermined distance from the first semiconductor region, removing the first and second insulating films around the first semiconductor region with a predetermined width, and then removing the first and second insulating films. Introducing the impurity of the first conductivity type into the epitaxial layer through a region from which an insulating film has been removed to form a second semiconductor region having a relatively high concentration. Method. (A) forming, on a substrate, an epitaxial layer into which impurities having a first conductivity type are introduced at a relatively low concentration;
(B) forming a first insulating film on the epitaxial layer;
(C) After removing a part of the first insulating film, an impurity of a second conductivity type different from the first conductivity type is introduced into the epitaxial layer through a region where the first insulating film is removed. Forming a relatively high concentration first semiconductor region;
(D) forming a second insulating film on the first insulating film;
(E) at a predetermined distance from the first semiconductor region, removing the first and second insulating films around the first semiconductor region with a predetermined width, and then removing the first and second insulating films. Introducing the impurity of the first conductivity type into the epitaxial layer through the region from which the insulating film has been removed to form a second semiconductor region having a relatively high concentration,
The method of manufacturing a semiconductor device, wherein the second semiconductor region reaches the substrate.

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