CN103137544A - Semi-conductor chip structure and manufacture method of metal fuse in chip - Google Patents
Semi-conductor chip structure and manufacture method of metal fuse in chip Download PDFInfo
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- CN103137544A CN103137544A CN2011103743074A CN201110374307A CN103137544A CN 103137544 A CN103137544 A CN 103137544A CN 2011103743074 A CN2011103743074 A CN 2011103743074A CN 201110374307 A CN201110374307 A CN 201110374307A CN 103137544 A CN103137544 A CN 103137544A
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Abstract
An embodiment of the invention provides a semi-conductor chip structure and a manufacture method of a metal fuse in a chip. The method includes that a first metal layer on the upper surface of a silicon substrate is etched, the thickness of the first metal layer is d1, at least two metal blocks which are d1 in the thickness and w1 in the width are formed on the upper surface of the silicon substrate, and a first opening is formed between every two metal blocks; a passivation layer which is d2 in the thickness is formed on the upper surface of the first metal layer; the passivation layer is etched, and a second opening which is d2 in the thickness and w2 in the width is formed on the upper surface of each metal block of the at least two metal blocks; a second metal layer which is d3 in the thickness is formed on the upper surface of the passivation layer, the first metal layer and the second metal layer are processed in alloying mode so as to enable the second metal layer at the second opening position to be closely combined with the first metal layer; and the second metal layer is etched, the metal fuse is formed between every two second openings in the at least two second openings.
Description
Technical field
The application relates to the semiconductor chip fabrication process technical field, relates in particular to fuse manufacture craft field.
Background technology
Along with developing rapidly of industry, semiconductor chip has obtained using more and more widely, and the fuse of using in semiconductor circuit chip, can be by powering up, it is fused to reach the effect of adjusting the structure of circuit in chip, also obtain people and more and more pay close attention to.
The fuse of using in semiconductor circuit chip, has plenty of polycrystalline fuse, has plenty of metal fuse, and that the method for making in the prior art metal fuse has is a variety of, but in prior art, no matter for which kind of fuse, in manufacturing process, generally all need to etch the metal fuse cabling by the metal level below passivation layer, then leave the corresponding window of metal fuse (as shown in Figure 2) at passivation layer, be convenient to the volatilization of follow-up burning timing product or flow.Product for the wide metal fuse technique of fine rule, if carry out the copper cash encapsulation, the aluminum layer thickness of press welding block needs thickening, but present conventional process for upsetting flow process, can damage metal fuse in manufacturing process, in prior art, the first manufacture method is specific as follows at present:
As shown in Figure 1, the first metal layer is carried out etching, etch the metal fuse cabling;
As shown in Figure 2, passivation layer is carried out etching, etch metal fuse window and press welding block window;
As shown in Figure 3, add one deck the second metal level at the passivation layer upper surface;
As shown in Figure 4, the second metal level is carried out etching, obtain metal fuse.
The metal fuse that obtains by the first manufacture method is because before carrying out the metal level thickening, the window of passivation layer fuse is etched open (as shown in Figure 2), the metal level of follow-up thickening is when carrying out wet etching, the fuse window of meeting by opening on passivation layer erodes metal fuse (as shown in Figure 3, Figure 4).
In prior art, also have the second manufacture method to make metal fuse, although the method is not damaged metal fuse, the technique more complicated, cost is also higher, so usually seldom adopt this way.Specific practice is as follows:
As shown in Figure 5, the first metal layer is carried out etching, etch the metal fuse cabling;
As shown in Figure 6, generate a passivation layer at the first metal layer upper surface;
As shown in Figure 7, generate the second metal level at the passivation layer upper surface;
As shown in Figure 8, the second metal level is carried out etching, etch the press welding block zone;
As shown in Figure 9, at the second metal level upper surface regeneration one regeneration passivation layer;
As shown in figure 10, the regeneration passivation layer is carried out etching, etching obtains metal fuse.
So, although the second manufacture method can the corroding metal fuse, complex manufacturing process, work difficulty is relatively large, and cost is higher.
In sum, the inventor finds to exist in prior art following at least two problems in the invention process:
1, in manufacturing process, due to the order and the position that make, meeting damage metal fuse more or less;
If 2 adopt the manufacture method of not damaging metal fuse, complex manufacturing process, and cost of manufacture is higher, and practicality also decreases.
Summary of the invention
The embodiment of the present application provides the manufacture method of metal fuse in a kind of semiconductor chip structure and chip, has solved prior art and has made the technical problem that can damage metal fuse in the metal fuse process.
In order to solve the problems of the technologies described above, the embodiment of the present application provides the manufacture method of metal fuse in a kind of semiconductor chip, specifically comprises:
The first metal layer that is d1 to the thickness that is positioned at the silicon substrate upper surface carries out etching, forms at the upper surface of described silicon substrate to comprise that at least two thickness are d1, and width is the metal derby of w1, wherein, forms one first opening between every two metal derbies;
Upper surface formation thickness at described the first metal layer is the passivation layer of d2, and fills up described the first opening;
Described passivation layer is carried out etching, it is d2 that each metal derby upper surface in described at least two metal derbies forms a thickness, and width is the second opening of w2, and described d2 is more than or equal to described d1, and less than or equal to described d1 and described d2 sum, described w2 is less than described w1;
Forming thickness at described passivation layer upper surface is the second metal level of d3, and fill up described the second opening, described the first metal layer and described the second metal level are carried out Alloying Treatment, the second metal level and the described the first metal layer of corresponding described the second opening part are combined closely;
Described the second metal level is carried out etching, to form a metal fuse at least between every two the second openings in described two the second openings.
The embodiment of the present application provides a kind of semiconductor chip structure, specifically comprises:
One silicon substrate;
Be positioned at the first metal layer of a described silicon substrate upper surface, described the first metal layer includes at least two metal derbies, forms one first opening between each metal derby;
Be positioned at the passivation layer of described the first metal layer upper surface, and include at least two the second openings, described the second opening is positioned at the upper surface of each metal derby of described at least two metal derbies;
Be positioned at the metal fuse of described passivation layer upper surface, described metal fuse connects every two the second openings in described at least two the second openings.
Further, said structure also comprises:
Be positioned at the press welding block of the described second metal level thickening of use of described passivation layer upper surface; Described press welding block and described metal fuse be not at same position.
Wherein, the cross section of described metal derby is shaped as rectangle, square, rhombus, trapezoidal, triangle or circle.
The application can reach one of following advantage or useful technique effect by an embodiment or a plurality of embodiment:
1, add in the etching process of thick metal layers at press welding block owing to utilizing, simultaneously formed metal fuse in passivation layer surface, the making of metal fuse is on passivation layer, be not traditional being positioned at below passivation layer, so in making the metal fuse process, when not damaging metal fuse, satisfied again fuse and burnt the demand of transferring;
2, be to complete in the metal level etching of press welding block thickening due to the making utilization of metal fuse, so making flow process for the press welding block thickening, the making of metal fuse does not increase any step operation, making step and manufacture difficulty have been simplified to greatest extent, not only reduce cost, also realized the integrated of metal fuse making and press welding block process for upsetting.
Description of drawings
Fig. 1 is the first manufacture method first step of metal fuse in prior art, and the first metal layer is carried out etching, etches metal fuse cabling profile;
Fig. 2 is the first manufacture method second step of metal fuse in prior art, and passivation layer is carried out etching, etches metal fuse window profile;
Fig. 3 is the 3rd step of the first manufacture method of metal fuse in prior art, generates the second metal level profile at the passivation layer upper surface;
Fig. 4 is the 4th step of the first manufacture method of metal fuse in prior art, and the second metal level is carried out etching, etches the metal fuse profile;
Fig. 5 is the second manufacture method first step of metal fuse in prior art, and the first metal layer is carried out etching, etches metal fuse cabling profile;
Fig. 6 is the second manufacture method second step of metal fuse in prior art, generates a passivation layer profile at the first metal layer upper surface;
Fig. 7 is the 3rd step of the second manufacture method of metal fuse in prior art, generates the second metal level profile at the passivation layer upper surface;
Fig. 8 is the 4th step of the second manufacture method of metal fuse in prior art, and the second metal level is carried out Etching profile figure;
Fig. 9 is the 5th step of the second manufacture method of metal fuse in prior art, generates regeneration passivation layer profile at the second metal level upper surface;
Figure 10 is the 5th step of the second manufacture method of metal fuse in prior art, and the regeneration passivation layer is carried out etching, etches the metal fuse profile;
Figure 11 carries out profile after etching to the first metal layer in the embodiment of the present application one;
Figure 12 is the profile after the upper surface of the first metal layer forms passivation layer in the embodiment of the present application one;
Figure 13 carries out profile after etching to passivation layer in the embodiment of the present application one;
Figure 14 is the profile after the second metal level that the passivation layer upper surface forms in the embodiment of the present application one;
Figure 15 be in the embodiment of the present application one to the second metal level etching, form the profile after metal fuse;
Figure 16 is the sectional structure chart of the first embodiment of semiconductor chip in the embodiment of the present application two;
Figure 17 is the sectional structure chart of the second embodiment of two kinds of semiconductor chips of the embodiment of the present application.
Embodiment
The embodiment of the present application provides the manufacture method of metal fuse in a kind of semiconductor chip structure and chip, has solved prior art and has made meeting damage metal fuse or complex manufacturing process and the high technical problem of cost in the metal fuse process.
Please refer to Figure 11 to Figure 15, the embodiment of the present application provides the manufacture method of metal fuse in a kind of chip, specifically comprises:
As shown in figure 11, the first metal layer that is d1 to the thickness that is positioned at the silicon substrate upper surface carries out etching, forms at the upper surface of this silicon substrate to comprise that at least two thickness are d1, and width is the metal derby of w1, wherein, forms one first opening between every two metal derbies;
As shown in figure 12, the upper surface formation thickness at the first metal layer is the passivation layer of d2;
As shown in figure 13, this passivation layer is carried out etching, it is d2 that each the metal derby upper surface at least two metal derbies forms a thickness, and width is the second opening of w2, and wherein, d2 is more than or equal to d1, and less than or equal to d1 and d2 sum, w2 is less than w1;
As shown in figure 14, forming thickness at this passivation layer upper surface is the second metal level of d3;
As shown in figure 15, this second metal level is carried out etching, to form a metal fuse between every two the second openings at least two the second openings.
Wherein, the material of described the first metal layer and described the second metal level can adopt aluminium, copper, albronze or Al-Si-Cu alloy, certainly, in implementation procedure, can consider the actual conditions needs, also can select other metal material according to the embodiment of the present application, so can consider cost in practical application and select suitable concrete material in conjunction with the characteristic of various metal materials.
The material that described passivation layer adopts can be the silicides such as silicon dioxide, plays a protective effect; Can be also other material, can be according to actual needs in actual application, the different material that selection can play a protective role.
In actual application, for manufacture of semiconductor, described etching is divided into wet etching and dry etching usually, and the embodiment of the present application adopts wet etching.Certainly, two kinds of methods respectively have characteristics, can come according to the actual conditions needs method of selective etching.Mainly the impact according to ambient temperature, humidity, and the operating pressure of selecting and these factors of power method of coming selective etching.
Optionally, after this passivation layer upper surface formation thickness is the second metal level of d3, the first metal layer and the second metal level are carried out Alloying Treatment, the second metal level and the first metal layer of corresponding the second opening part are combined closely.
In concrete implementation process, described alloying refers to by improving temperature, chip be carried out the high temperature fusion treatment, is that the second metal level and the first metal layer that corresponding the second opening goes out combined closely.
As shown in figure 16, the embodiment of the present application provides a kind of semiconductor chip structure, specifically comprises:
One silicon substrate;
Be positioned at the first metal layer of this silicon substrate upper surface, the first metal layer includes at least two metal derbies, forms one first opening between each metal derby;
Be positioned at the passivation layer of this first metal layer upper surface, this passivation layer includes at least two the second openings, and this second opening is positioned at the upper surface of each metal derby of at least two metal derbies;
Be positioned at the metal fuse of this passivation layer upper surface, this metal fuse connects every two the second openings at least two the second openings;
Wherein, the material of described the first metal layer and described the second metal level can adopt aluminium, copper, albronze or Al-Si-Cu alloy, certainly, in implementation procedure, can consider the actual conditions needs, also can select other metal material according to the embodiment of the present application, so can consider cost in practical application and select suitable concrete material in conjunction with the characteristic of various metal materials.
The material that described passivation layer adopts can be the silicides such as silicon dioxide, plays a protective effect; Can be also other material, can be according to actual needs in actual application, the different material that selection can play a protective role.
As shown in figure 17, said structure also comprises:
Be positioned at the press welding block of the use second metal level thickening of this passivation layer upper surface; This press welding block and this metal fuse be not at same position.
Wherein, the cross section of described metal derby is shaped as rectangle, square, rhombus, trapezoidal, triangle or circle.
The application can reach one of following advantage or useful technique effect by an embodiment or a plurality of embodiment:
1, add in the etching process of thick metal layers at press welding block owing to utilizing, simultaneously formed metal fuse in passivation layer surface, the making of metal fuse is on passivation layer, be not traditional being positioned at below passivation layer, so in making the metal fuse process, when not damaging metal fuse, satisfied again fuse and burnt the demand of transferring;
2, be to complete in the metal level etching of press welding block thickening due to the making utilization of metal fuse, so making flow process for the press welding block thickening, the making of metal fuse does not increase any step operation, making step and manufacture difficulty have been simplified to greatest extent, not only reduce cost, also realized the perfect integrated of metal fuse making and press welding block process for upsetting.
The method that the present invention is designed can be used any computer language to realize, and there is no specific (special) requirements for software and hardware.Although described the application's preferred embodiment, in a single day those skilled in the art get the basic creative concept of cicada, can make other change and modification to these embodiment.So claims are intended to all changes and the modification that are interpreted as comprising preferred embodiment and fall into the application's scope.
Obviously, those skilled in the art can carry out various changes and modification and not break away from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of claim of the present invention and equivalent technologies thereof, the present invention also is intended to comprise these changes and modification interior.
Claims (5)
1. the manufacture method of metal fuse in a semiconductor chip, is characterized in that, specifically comprises:
The first metal layer that is d1 to the thickness that is positioned at the silicon substrate upper surface carries out etching, forms at the upper surface of described silicon substrate to comprise that at least two thickness are d1, and width is the metal derby of w1, wherein, forms one first opening between every two metal derbies;
Upper surface formation thickness at described the first metal layer is the passivation layer of d2;
Described passivation layer is carried out etching, it is d2 that each metal derby upper surface in described at least two metal derbies forms a thickness, and width is the second opening of w2, and described d2 is more than or equal to described d1, and less than or equal to described d1 and described d2 sum, described w2 is less than described w1;
Forming thickness at described passivation layer upper surface is the second metal level of d3;
Described the second metal level is carried out etching, to form a metal fuse at least between every two the second openings in described two the second openings.
2. the method for claim 1, is characterized in that, also comprises:
Described the first metal layer and described the second metal level are carried out Alloying Treatment, the second metal level and the described the first metal layer of corresponding described the second opening part are combined closely.
3. a semiconductor chip structure, is characterized in that, comprising:
One silicon substrate;
Be positioned at the first metal layer of a described silicon substrate upper surface, described the first metal layer includes at least two metal derbies, forms one first opening between each metal derby;
Be positioned at the passivation layer of described the first metal layer upper surface, described passivation layer includes at least two the second openings, and described the second opening is positioned at the upper surface of each metal derby of described at least two metal derbies;
Be positioned at the metal fuse of described passivation layer upper surface, described metal fuse connects every two the second openings in described at least two the second openings.
4. structure as claimed in claim 3, is characterized in that, also comprises:
Be positioned at the press welding block of the described second metal level thickening of use of described passivation layer upper surface; Described press welding block and described metal fuse be not at same position.
5. structure as described in claim 3 or 4, is characterized in that, the cross section of described metal derby be shaped as rectangle, square, rhombus, trapezoidal, triangle or circle.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110374307.4A CN103137544B (en) | 2011-11-22 | 2011-11-22 | The manufacture method of metal fuse in a kind of semiconductor chip structure and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110374307.4A CN103137544B (en) | 2011-11-22 | 2011-11-22 | The manufacture method of metal fuse in a kind of semiconductor chip structure and chip |
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| CN103137544A true CN103137544A (en) | 2013-06-05 |
| CN103137544B CN103137544B (en) | 2015-11-11 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104022103A (en) * | 2014-06-12 | 2014-09-03 | 上海先进半导体制造股份有限公司 | Chip and manufacturing method thereof |
| CN108598064A (en) * | 2018-05-09 | 2018-09-28 | 北京智芯微电子科技有限公司 | Connect the metal wire of conventional die and test special chip in wafer |
| WO2021180122A1 (en) * | 2020-03-13 | 2021-09-16 | 长鑫存储技术有限公司 | Semiconductor structure and formation method therefor, and fusing method for laser fuse |
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|---|---|---|---|---|
| KR20010005114A (en) * | 1999-06-30 | 2001-01-15 | 김영환 | Fabricating method for fuse of semiconductor device |
| US20040171263A1 (en) * | 2003-02-28 | 2004-09-02 | Ja-Young Choi | Method for forming fuse integrated with dual damascene process |
| US20050040491A1 (en) * | 2002-06-05 | 2005-02-24 | Chiu-Te Lee | Fuse stucture |
| CN102157491A (en) * | 2011-03-10 | 2011-08-17 | 上海宏力半导体制造有限公司 | Semiconductor structure and manufacturing method thereof |
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2011
- 2011-11-22 CN CN201110374307.4A patent/CN103137544B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010005114A (en) * | 1999-06-30 | 2001-01-15 | 김영환 | Fabricating method for fuse of semiconductor device |
| US20050040491A1 (en) * | 2002-06-05 | 2005-02-24 | Chiu-Te Lee | Fuse stucture |
| US20040171263A1 (en) * | 2003-02-28 | 2004-09-02 | Ja-Young Choi | Method for forming fuse integrated with dual damascene process |
| CN102157491A (en) * | 2011-03-10 | 2011-08-17 | 上海宏力半导体制造有限公司 | Semiconductor structure and manufacturing method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104022103A (en) * | 2014-06-12 | 2014-09-03 | 上海先进半导体制造股份有限公司 | Chip and manufacturing method thereof |
| CN108598064A (en) * | 2018-05-09 | 2018-09-28 | 北京智芯微电子科技有限公司 | Connect the metal wire of conventional die and test special chip in wafer |
| WO2021180122A1 (en) * | 2020-03-13 | 2021-09-16 | 长鑫存储技术有限公司 | Semiconductor structure and formation method therefor, and fusing method for laser fuse |
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| CN103137544B (en) | 2015-11-11 |
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Effective date of registration: 20220726 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District Cheng Fu Road 298, founder building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |