KR20010005114A - Fabricating method for fuse of semiconductor device - Google Patents

Fabricating method for fuse of semiconductor device Download PDF

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Publication number
KR20010005114A
KR20010005114A KR1019990025911A KR19990025911A KR20010005114A KR 20010005114 A KR20010005114 A KR 20010005114A KR 1019990025911 A KR1019990025911 A KR 1019990025911A KR 19990025911 A KR19990025911 A KR 19990025911A KR 20010005114 A KR20010005114 A KR 20010005114A
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KR
South Korea
Prior art keywords
fuse
metal
mask
layer
polycrystal silicon
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KR1019990025911A
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Korean (ko)
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최병진
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김영환
현대전자산업 주식회사
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Priority to KR1019990025911A priority Critical patent/KR20010005114A/en
Publication of KR20010005114A publication Critical patent/KR20010005114A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62—Protection against overvoltage, e.g. fuses, shunts

Abstract

PURPOSE: A method for forming a fuse of a semiconductor device is provided to prevent that a heat is transmitted to an adjacent element in case of a fuse blowing up, by making a lower part of a fuse as a polycrystal silicon and interconnecting the polycrystal silicon layers by using a metal. CONSTITUTION: The first interfacial insulating layer(23) is formed on a semiconductor substrate(21). A polycrystal silicon layer pattern(25) connected to a fuse is formed on the first interfacial insulating layer. A center part of the polycrystal silicon layer pattern is separated from another center part of another polycrystal silicon layer pattern. A contact hole exposing a fuse connection part is provided on the polycrystal silicon layer pattern, and exposes the both sides of the polycrystal silicon layer pattern. The second interfacial insulating layer(27) includes the contact hole therein. A metal layer for a fuse is formed on the total structure, and the metal layer interconnects the polycrystal silicon layer patterns separated from each other. The metal layer for fuse is etched by using a fuse mask as an etching mask, thereby forming a metal fuse. The fuse mask protects a part functioning as a fuse. The third interfacial insulating layer(33) is formed on the total structure. By using a fuse box mask as an etching mask, the third interfacial insulating layer is etched. At this time, the etching process is performed to leave the third interfacial insulating layer of a predetermined thickness on an upper part of the metal fuse. The fuse box mask exposes a part determined as a fuse box area.

Description

반도체소자의 퓨즈 제조방법{Fabricating method for fuse of semiconductor device}Fabrication method for fuse of semiconductor device

본 발명은 반도체소자의 퓨즈 제조방법에 관한 것으로서, 특히 금속퓨즈를 하부에서 다결정실리콘층을 사용하여 연결함으로써 퓨즈블로잉업(fuse blowing up)시 인접하는 소자에 열이 전달되는 것을 방지하는 반도체소자의 퓨즈 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a fuse of a semiconductor device, and more particularly, to a method of manufacturing a fuse of a semiconductor device which prevents heat from being transferred to an adjacent device during fuse blowing up by connecting a metal fuse using a polysilicon layer below. It relates to a fuse manufacturing method.

일반적으로 수많은 미세 셀(cell) 중 한 개라도 결함이 있다면 DRAM 및 SRAM의 반도체 메모리 소자는 제구실을 하지 못하게 되어 불량품으로 처리된다. 하지만 반도체 메모리 소자의 집적도가 증가함에 따라 확률적으로 소량의 셀에만 발생할 확률이 높은데도 불구하고, 이를 불량품으로 폐기한다는 것은 수율을 낮추는 비효율적인 처리 방식이다.In general, if any one of the many fine cells is defective, the semiconductor memory devices of the DRAM and the SRAM will not be able to serve as a defective part and will be treated as defective. However, although the probability of occurrence of only a small number of cells is increased as the degree of integration of semiconductor memory devices increases, discarding it as a defective product is an inefficient treatment method that lowers the yield.

따라서, DRAM 및 SRAM 등의 반도체 메모리 소자내에 미리 예비 메모리 셀을 설치해 두고서 그 예비 메모리 셀을 이용하여 불량셀을 대체시킴으로써 수율을 높이는 리던던시 방식을 채용하게 되었다.Accordingly, a redundancy scheme is adopted in which a yield memory is increased by preliminarily providing spare memory cells in semiconductor memory devices such as DRAM and SRAM, and replacing defective cells using the spare memory cells.

이와 같이 리던던시 방식이 채용된 종래의 반도체 메모리 소자는 제조공정을 거쳐 패키지(pakage)화되는데, 몰딩(molding)된 패키지에 불량이 발생하면 정확한 원인을 조사하기 위한 분석을 위해 이것이 잉여의 셀로 대체한 칩인지의 여부를 알아야 한다. 또한 칩의 신뢰성이 점차적으로 중요해짐에 따라 어떤 칩이 잉여의 셀로 대체된 칩인지의 여부를 알 필요가 있다.The conventional semiconductor memory device employing such a redundancy method is packaged through a manufacturing process. If a defect occurs in a molded package, it is replaced by a surplus cell for analysis to investigate the exact cause. You need to know if it's a chip. In addition, as chip reliability becomes increasingly important, it is necessary to know whether a chip is replaced by a surplus cell.

이를 광학적인 방법으로 알고자 할 경우에는 몰딩된 패키지를 파괴해야 되는데, 이 경우에는 칩의 특성이 달라질 수가 있고, 또한 패키지의 파괴 과정에서 심한 파괴로 인해 칩을 분석할 수 없을 정도로 만들게 되는 경우가 발생된다.In order to know this by optical method, it is necessary to destroy the molded package. In this case, the characteristics of the chip may be changed, and in the case of the package destruction, the chip may be impossible to analyze due to severe destruction. Is generated.

그에 따라 몰딩된 패키지의 외부에서 잉여의 셀로 대체했는지를 알아 보는 테스트 방식이 채용되는데, 그 테스트 방식은 통상적으로 특정한 핀과 파워 핀 사이에 퓨즈와 다이오드를 직렬로 연결하고 사이에 흐르는 전류가 다르게 되므로, 이를 이용하여 잉여의 셀로 대체하였는지의 여부를 외부에서도 알 수 있도록 하는 방식이다.As a result, a test method is used to determine whether the cell is replaced by a surplus of cells outside the molded package, which is typically connected in series with a fuse and a diode between a specific pin and a power pin, and the current flowing between them is different. By using this method, it is possible to know from the outside whether it is replaced by a surplus cell.

메모리 소자의 불량 셀을 행(row)과 열(column)으로 대체하는 경우, 반도체 집적회로의 옵션(option)처리를 하는 경우 또는 집적회로 내의 단위 소자를 미세 조정하는 경우에 퓨즈를 이용할 수 있다.A fuse may be used to replace defective cells of a memory device with rows and columns, to perform option processing of a semiconductor integrated circuit, or to finely adjust a unit device in an integrated circuit.

일반적으로 사용되는 퓨즈의 방식으로는 금속 퓨즈를 만들어 큰 전류를 흘려 퓨즈를 끊는 방법과 금속 또는 다결정실리콘 퓨즈를 만들어 레이져를 이용하여 퓨즈를 끊는 방식, 그리고 절연막을 통한 터널링 전자(tunneling electron)로 플로우팅 게이트를 차지(charge)시키는 플로우팅 게이트 방식이 있다.Commonly used fuses are made of metal fuses to blow large currents and blown metals or polycrystalline silicon fuses to blow fuses, and tunneling electrons through the insulating film. There is a floating gate method that charges a putting gate.

레이저를 이용하여 퓨즈를 끊는 방식에서 다결정실리콘층으로 형성된 퓨즈가 주로 사용되는데, 이는 금속퓨즈를 사용할 경우 금속의 열전도도가 매우 크기 때문에 퓨즈의 블로잉업이 힘들어서 상대적으로 열전도도가 작은 다결정실리콘층을 사용하면 퓨즈의 블로잉업을 용이하게 실시할 수 있다.A fuse formed of a polysilicon layer is mainly used in a method of breaking a fuse using a laser. Since a metal fuse has a large thermal conductivity, a blow up of the fuse is difficult and thus a polysilicon layer having a relatively low thermal conductivity is used. If used, the blow-up of the fuse can be easily performed.

그러나, 반도체 집적회로의 집적도가 높아짐에 따라 다층 금속을 사용하게 되고, 다결정실리콘층으로 형성된 퓨즈를 사용하는 경우 퓨즈 상부에 적층되는 절연막의 두께가 높아져서 상기 절연막을 식각하는데 많은 시간을 필요로 하여 처리량(throughput)이 떨어지고, 상기 절연막을 증착할 때와 상기 절연막을 식각할 때 균일성(uniformity)문제로 퓨즈상의 절연막 두께를 균일하게 유지하기가 어렵기 때문에 퓨즈 블로잉업이 어려워지는 문제점이 있다.However, as the degree of integration of semiconductor integrated circuits increases, multilayer metals are used, and when a fuse formed of a polysilicon layer is used, the thickness of the insulating film stacked on the fuse becomes high, which requires a large amount of time to etch the insulating film. (Throughput) is lowered, and it is difficult to blow the fuse because it is difficult to uniformly maintain the thickness of the insulating film on the fuse due to uniformity problems when the insulating film is deposited and when the insulating film is etched.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 금속퓨즈와 연결될 다결정실리콘층 패턴을 먼저 형성하고 금속배선 형성공정시 형성되는 금속층을 이용하여 상기 다결정실리콘층 패턴을 형성하여 퓨즈를 형성함으로써 퓨즈 상부에 형성되는 절연막의 두께를 얇게 형성할 수 있고, 퓨즈블로잉업공정시 퓨즈의 열이 주변으로 전달되는 것을 방지하여 리페어 공정을 용이하게 실시하고, 반도체소자의 고집적화를 유리하게 하는 반도체소자의 퓨즈 제조방법을 제공하는데 그 목적이 있다.The present invention is to solve the above problems of the prior art, by forming a polysilicon layer pattern to be connected to the metal fuse first and by using the metal layer formed during the metal wiring formation process to form the polysilicon layer pattern to form a fuse The thickness of the insulating film formed on the upper part can be formed thinly, and the fuse process of the semiconductor device facilitates the repair process by preventing the heat of the fuse from being transferred to the periphery during the fuse blow-up process, and facilitates high integration of the semiconductor device. The purpose is to provide a manufacturing method.

도 1 은 종래기술에 따라 다결정실리콘층을 사용한 반도체소자의 퓨즈 제조방법을 도시한 단면도.1 is a cross-sectional view showing a fuse manufacturing method of a semiconductor device using a polysilicon layer according to the prior art.

도 2a 내지 도 2f 는 본 발명에 따라 금속을 사용한 반도체소자의 퓨즈 제조방법을 도시한 단면도.2A to 2F are sectional views showing a fuse manufacturing method of a semiconductor device using a metal according to the present invention;

〈도면의 주요부분에 대한 부호 설명〉<Explanation of symbols on main parts of the drawing>

11, 21 : 반도체기판 13, 23 : 제1층간절연막11, 21: semiconductor substrate 13, 23: first interlayer insulating film

15, 25 : 다결정실리콘층 패턴 17, 27 : 제2층간절연막15, 25: polysilicon layer pattern 17, 27: second interlayer insulating film

29 : 퓨즈 콘택홀 31 : 퓨즈용 금속층29: fuse contact hole 31: metal layer for the fuse

32 : 금속퓨즈 33 : 제3층간절연막32: metal fuse 33: third interlayer insulating film

이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 퓨즈 제조방법은,In order to achieve the above object, the fuse manufacturing method of the semiconductor device according to the present invention,

반도체기판 상부에 제1층간절연막을 형성하는 공정과,Forming a first interlayer insulating film on the semiconductor substrate;

상기 제1층간절연막 상부에 퓨즈와 연결하기 위한 다결정실리콘층 패턴을 형성하되, 중간부분이 서로 이격되어 분리되도록 형성하는 공정과,Forming a polysilicon layer pattern for connecting to the fuse on the first interlayer insulating layer, wherein the middle portions are spaced apart from each other;

상기 구조 상부에 다결정실리콘층 패턴에서 퓨즈가 접속될 부분을 노출시키는 콘택홀이 구비되되, 서로 이격되어 있는 다결정실리콘층 패턴 양쪽을 노출시키는 콘택홀이 구비된 제2층간절연막을 형성하는 공정과,Forming a second interlayer insulating film having a contact hole exposing a portion to which a fuse is to be connected in the polysilicon layer pattern on the structure, the contact hole exposing both sides of the polysilicon layer pattern spaced apart from each other;

전체표면 상부에 상기 콘택홀을 통하여 상기 이격되어 있는 다결정실리콘층 패턴을 서로 연결하는 퓨즈용 금속층을 형성하는 공정과,Forming a fuse metal layer on the entire surface of the fuse to connect the spaced polysilicon layer patterns to each other through the contact hole;

퓨즈로 예정되는 부분을 보호하는 퓨즈 마스크를 식각마스크로 상기 퓨즈용 금속층을 식각하여 금속퓨즈를 형성하는 공정과,Forming a metal fuse by etching the fuse metal layer by using a fuse mask that protects a predetermined portion of the fuse as an etch mask;

상기 구조 상부에 제3층간절연막을 형성하는 공정과,Forming a third interlayer insulating film on the structure;

퓨즈박스영역으로 예정되는 부분을 노출시키는 퓨즈박스 마스크를 식각마스크로 사용하여 상기 제3층간절연막을 식각하되, 상기 금속퓨즈 상부에 소정 두께의 제3층간절연막이 남아있도록 식각하는 공정을 포함하는 것을 특징으로 한다.Etching the third interlayer insulating film using a fuse box mask that exposes a predetermined portion of the fuse box region as an etching mask, and etching the third interlayer insulating film to have a predetermined thickness remaining on the metal fuse. It features.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2f 는 본 발명에 따라 금속을 사용한 반도체소자의 퓨즈 제조방법을도시한 단면도이다.2A to 2F are cross-sectional views illustrating a fuse manufacturing method of a semiconductor device using a metal according to the present invention.

먼저, 반도체기판(21) 상부에 제1층간절연막(23)을 형성하고, 상기 제1층간절연막(23) 상부에 다결정실리콘층을 형성한다.First, a first interlayer insulating film 23 is formed on the semiconductor substrate 21, and a polysilicon layer is formed on the first interlayer insulating film 23.

다음, 상기 반도체기판(21)의 퓨즈박스영역에서 다결정실리콘층 상부에 퓨즈가 연결될 부분으로 예정되는 부분을 보호하는 감광막 패턴(도시안됨)을 형성하고, 상기 감광막 패턴을 식각마스크로 상기 다결정실리콘층을 식각하여 다결정실리콘층 패턴(25)을 형성한다. 이때, 상기 다결정실리콘층 패턴(25)은 중심부분이 서로 이격되어 형성되고, 상기 다결정실리콘층 대신 폴리사이드구조(polycide)로 형성할 수도 있다.Next, a photoresist pattern (not shown) is formed on the polycrystalline silicon layer in the fuse box region of the semiconductor substrate 21 to protect a portion scheduled to be connected to the fuse, and the polysilicon layer is formed by using the photoresist pattern as an etch mask. Is etched to form a polysilicon layer pattern 25. In this case, the polysilicon layer pattern 25 may be formed with a central portion spaced apart from each other, and may be formed of a polycide structure instead of the polysilicon layer.

상기 다결정실리콘층 패턴(25)은 워드라인, 비트라인 또는 캐패시터공정중 어느 한 공정에서 형성될 수 있다. (도 2a참조)The polysilicon layer pattern 25 may be formed in any one of a word line, a bit line, and a capacitor process. (See Figure 2A)

그 다음, 후속공정을 실시하는 동안에 퓨즈박스영역에 제2층간절연막(27)이 형성된다. (도 2b참조)Then, a second interlayer insulating film 27 is formed in the fuse box region during the subsequent process. (See Figure 2b)

다음, 금속배선 콘택형성공정시 셀영역의 금속배선 콘택으로 예정되는 부분에서 상기 제2층간절연막(27)은 퓨즈가 상기 다결정실리콘층 패턴(25)과 접속될 부분을 노출시키는 콘택마스크를 식각마스크로 사용하여 식각하여 퓨즈 콘택홀(29)을 형성한다. (도 2c참조)Next, during the metallization contact forming process, the second interlayer insulating layer 27 may etch a contact mask that exposes a portion where the fuse is to be connected to the polysilicon layer pattern 25 at a portion that is intended as a metallization contact of the cell region. Etching is used to form a fuse contact hole (29). (See FIG. 2C)

그 다음, 상기 제2층간절연막(27) 상부에 상기 다결정실리콘층 패턴(25)에 접속되도록 퓨즈용 금속층(31)을 형성한다. 이때, 상기 퓨즈용 금속층(31)은 Al층 또는 W층 또는 Cu층으로 사용할 수 있다. (도 2d참조)Next, a fuse metal layer 31 is formed on the second interlayer insulating layer 27 so as to be connected to the polysilicon layer pattern 25. In this case, the fuse metal layer 31 may be used as an Al layer, a W layer, or a Cu layer. (See FIG. 2D)

다음, 상기 퓨즈용 금속층(31)은 퓨즈로 예정되는 부분을 보호하는 퓨즈마스크를 식각마스크로 식각하여 금속퓨즈(32)를 형성한다. (도 2e참조)Next, the fuse metal layer 31 forms a metal fuse 32 by etching a fuse mask that protects a portion of the fuse to be an etch mask. (See Figure 2E)

그 후, 상기 구조 상부에 제3층간절연막(33)을 형성하되, 상기 금속퓨즈(32) 상부에서 균일한 두께를 갖도록 형성한다. (도 2f참조)Thereafter, a third interlayer insulating film 33 is formed on the structure, and formed to have a uniform thickness on the metal fuse 32. (See Figure 2f)

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 퓨즈 제조방법은, 고집적 반도체소자의 금속퓨즈를 형성하는데 있어서 퓨즈의 하부를 다결정실리콘층으로 형성하고 상기 다결정실리콘층을 금속을 사용하여 서로 연결함으로써 퓨즈 상부에 적층되는 절연막의 두께가 줄어들고, 그에 따라 상기 절연막을 식각하는 시간이 감소하기 때문에 처리량(throughput) 및 리페어 수율(repair yield)이 증가하며, 퓨즈블로잉업시 금속퓨즈의 열이 주변으로 전달되는 것을 방지하여 반도체소자의 고집적화를 유리하게 하고, 그에 따른 소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the method of manufacturing a fuse of a semiconductor device according to the present invention, in forming a metal fuse of a highly integrated semiconductor device, a fuse is formed by forming a lower portion of the fuse as a polysilicon layer and connecting the polycrystalline silicon layers to each other using a metal fuse. Since the thickness of the insulating layer stacked on the upper side is reduced, and thus the time for etching the insulating layer is reduced, throughput and repair yield are increased, and heat of the metal fuse is transferred to the surroundings during fuse blow-up. It is advantageous to prevent the high integration of the semiconductor device, thereby improving the characteristics and reliability of the device.

Claims (3)

반도체기판 상부에 제1층간절연막을 형성하는 공정과,Forming a first interlayer insulating film on the semiconductor substrate; 상기 제1층간절연막 상부에 퓨즈와 연결하기 위한 다결정실리콘층 패턴을 형성하되, 중간부분이 서로 이격되어 분리되도록 형성하는 공정과,Forming a polysilicon layer pattern for connecting to the fuse on the first interlayer insulating layer, wherein the middle portions are spaced apart from each other; 상기 구조 상부에 다결정실리콘층 패턴에서 퓨즈가 접속될 부분을 노출시키는 콘택홀이 구비되되, 서로 이격되어 있는 다결정실리콘층 패턴 양쪽을 노출시키는 콘택홀이 구비된 제2층간절연막을 형성하는 공정과,Forming a second interlayer insulating film having a contact hole exposing a portion to which a fuse is to be connected in the polysilicon layer pattern on the structure, the contact hole exposing both sides of the polysilicon layer pattern spaced apart from each other; 전체표면 상부에 상기 콘택홀을 통하여 상기 이격되어 있는 다결정실리콘층 패턴을 서로 연결하는 퓨즈용 금속층을 형성하는 공정과,Forming a fuse metal layer on the entire surface of the fuse to connect the spaced polysilicon layer patterns to each other through the contact hole; 퓨즈로 예정되는 부분을 보호하는 퓨즈 마스크를 식각마스크로 상기 퓨즈용 금속층을 식각하여 금속퓨즈를 형성하는 공정과,Forming a metal fuse by etching the fuse metal layer by using a fuse mask that protects a predetermined portion of the fuse as an etch mask; 상기 구조 상부에 제3층간절연막을 형성하는 공정과,Forming a third interlayer insulating film on the structure; 퓨즈박스영역으로 예정되는 부분을 노출시키는 퓨즈박스 마스크를 식각마스크로 사용하여 상기 제3층간절연막을 식각하되, 상기 금속퓨즈 상부에 소정 두께의 제3층간절연막이 남아있도록 식각하는 공정을 포함하는 반도체소자의 퓨즈 제조방법.Etching the third interlayer insulating film by using a fuse box mask that exposes a predetermined portion of the fuse box region as an etching mask, and etching the third interlayer insulating film to a predetermined thickness on the metal fuse. Method for manufacturing fuses of devices. 제 1 항에 있어서,The method of claim 1, 상기 다결정실리콘층 패턴은 실리사이드구조로 형성하는 것을 특징으로 하는 반도체소자의 퓨즈 제조방법.The polysilicon layer pattern is a fuse manufacturing method of the semiconductor device, characterized in that formed in a silicide structure. 제 1 항에 있어서,The method of claim 1, 상기 퓨즈용 금속층은 Al층 또는 W층 또는 Cu층으로 형성하는 것을 특징으로 하는 반도체소자의 퓨즈 제조방법.The fuse metal layer may be formed of an Al layer, a W layer, or a Cu layer.
KR1019990025911A 1999-06-30 1999-06-30 Fabricating method for fuse of semiconductor device KR20010005114A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030054791A (en) * 2001-12-26 2003-07-02 동부전자 주식회사 Method of forming fuse for semiconductor device
KR100904478B1 (en) * 2002-12-30 2009-06-24 주식회사 하이닉스반도체 Semiconductor device and method for fabricating the same
CN103137544A (en) * 2011-11-22 2013-06-05 北大方正集团有限公司 Semi-conductor chip structure and manufacture method of metal fuse in chip

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JPH05136271A (en) * 1991-11-15 1993-06-01 Hitachi Ltd Semiconductor integrated circuit device and its manufacture
JPH0778872A (en) * 1993-09-08 1995-03-20 Fujitsu Ltd Semiconductor integrated circuit
KR970003863A (en) * 1995-06-23 1997-01-29 김주용 Metal fuse structure of redundancy cell of semiconductor device and manufacturing method thereof
KR19980065935A (en) * 1997-01-16 1998-10-15 김광호 Fuse Manufacturing Method for Semiconductor Memory Device
JPH1131748A (en) * 1997-07-11 1999-02-02 Sony Corp Semiconductor device and manufacture of the same

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Publication number Priority date Publication date Assignee Title
JPH05136271A (en) * 1991-11-15 1993-06-01 Hitachi Ltd Semiconductor integrated circuit device and its manufacture
JPH0778872A (en) * 1993-09-08 1995-03-20 Fujitsu Ltd Semiconductor integrated circuit
KR970003863A (en) * 1995-06-23 1997-01-29 김주용 Metal fuse structure of redundancy cell of semiconductor device and manufacturing method thereof
KR19980065935A (en) * 1997-01-16 1998-10-15 김광호 Fuse Manufacturing Method for Semiconductor Memory Device
JPH1131748A (en) * 1997-07-11 1999-02-02 Sony Corp Semiconductor device and manufacture of the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030054791A (en) * 2001-12-26 2003-07-02 동부전자 주식회사 Method of forming fuse for semiconductor device
KR100904478B1 (en) * 2002-12-30 2009-06-24 주식회사 하이닉스반도체 Semiconductor device and method for fabricating the same
CN103137544A (en) * 2011-11-22 2013-06-05 北大方正集团有限公司 Semi-conductor chip structure and manufacture method of metal fuse in chip

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