CN108133922B - Method for manufacturing pressure welding assembly of semiconductor chip - Google Patents
Method for manufacturing pressure welding assembly of semiconductor chip Download PDFInfo
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- CN108133922B CN108133922B CN201711345315.XA CN201711345315A CN108133922B CN 108133922 B CN108133922 B CN 108133922B CN 201711345315 A CN201711345315 A CN 201711345315A CN 108133922 B CN108133922 B CN 108133922B
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000003466 welding Methods 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000002161 passivation Methods 0.000 claims abstract description 70
- 229910052751 metal Inorganic materials 0.000 claims abstract description 48
- 239000002184 metal Substances 0.000 claims abstract description 48
- 239000000463 material Substances 0.000 claims abstract description 38
- 238000005530 etching Methods 0.000 claims abstract description 35
- 230000008719 thickening Effects 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000002131 composite material Substances 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 36
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 27
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 27
- 229920002120 photoresistant polymer Polymers 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 235000012239 silicon dioxide Nutrition 0.000 claims description 18
- 239000000377 silicon dioxide Substances 0.000 claims description 18
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 230000007797 corrosion Effects 0.000 description 5
- 238000005260 corrosion Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000005275 alloying Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49534—Multi-layer
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Pressure Sensors (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
Abstract
The invention provides a method for manufacturing a pressure welding assembly of a semiconductor chip, which comprises the following steps: forming a pressure welding block on the surface of the semiconductor substrate; forming a passivation layer on the surface of the semiconductor substrate, wherein the passivation layer covers the pressure welding block and is a composite film layer comprising a plurality of passivation material film layers; sequentially etching the plurality of passivation material film layers of the passivation layer to enable the passivation layer to form an inverted trapezoidal opening at the position where the pressure welding block is located; and forming a metal thickening layer on the surface of the pressure welding block through the inverted trapezoidal opening. The scheme provided by the invention can solve the problem of thickening of the pressure welding block, improve the feasibility of the process and reduce the process cost.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of semiconductor chip manufacturing, in particular to a manufacturing method of a pressure welding assembly of a semiconductor chip.
[ background of the invention ]
In recent years, gold wire packaging has been increasing, and packaging factories have started to move to copper wire packaging. The copper wire package has a series of advantages of low price, low resistivity, high thermal conductivity and the like. But the copper wire has higher hardness, the routing strength is much larger than that of a gold wire and an aluminum wire, and the requirement on the thickness of the metal layer of the pressure welding block is correspondingly increased. Due to the limitations of photolithography alignment and control of etched line width, it is difficult for chip manufacturers to simply increase the thickness of the metal layer to meet the requirement of copper wiring for customers.
To solve this problem, there are two types of solutions:
the method comprises the following steps: the method of adding one more layer of pressure welding block reverse plate can make the aluminum layer on the pressure welding block locally thickened, and can meet the requirement of copper wire punching. The method specifically comprises the following steps: after the passivation layer is etched, a metal layer is sputtered (usually aluminum is selected), the photoresist is exposed (pad reverse) and developed, then the aluminum outside the pad area can be etched away, the photoresist is removed, and finally alloying is carried out (the purpose of alloying is to make the newly sputtered aluminum and the lower aluminum combine better). Thus, the thickness of the metal layer at the position of the pressure welding block can be locally thickened.
Although this method can thicken the metal layer at the bonding pad, it has some obvious defects: after the metal layer grows on the surface of the passivation layer, the metal layer needs to be subjected to photoetching and etching, so that the cost and the process complexity are increased. This is contrary to the original intention of adding a metal layer at the pad.
A second method: the metal layer is thickened at the pressure welding block by adopting a photoresist stripping process, and then the photoresist is stripped, so that the unnecessary metal layer is removed. This approach also has some drawbacks:
(1) the photoresist is organic matter, and will flow under the temperature of 200 degrees or so, and the metal growth temperature of conventional board all can exceed this temperature, so it is difficult to grow metal on the photoresist surface. Unless special machines for room temperature metal growth are used. Therefore, a certain threshold is brought to the popularization and application of the process;
(2) the photoresist appearance of the stripping process is an inverted trapezoid, but the inclination angle of the inverted trapezoid is not very large, which may cause that the photoresist sidewall cannot be broken when a thickened metal layer is grown subsequently.
(3) After the thick metal layer is grown, the photoresist needs to be stripped, and the stripping liquid needs to gradually and transversely dissolve the photoresist from the side wall of the photoresist, so that the metal layer on the surface of the photoresist is removed. At the moment, most area of the chip is covered by the thickened metal layer, at least the part of the pressure welding block is exposed on the side wall of the photoresist, and the photoresist can be transversely dissolved only through the position by the stripping liquid. Therefore, the efficiency of peeling is greatly affected, and peeling is basically not smooth.
In view of the above, it is desirable to provide a method for fabricating a bonding assembly of a semiconductor chip to solve the above problems in the prior art.
[ summary of the invention ]
One of the objectives of the present invention is to provide a method for fabricating a bonding assembly of semiconductor chips to solve the above problems.
The invention provides a manufacturing method of a pressure welding assembly of a semiconductor chip, which comprises the following steps: forming a pressure welding block on the surface of the semiconductor substrate; forming a passivation layer on the surface of the semiconductor substrate, wherein the passivation layer covers the pressure welding block and is a composite film layer comprising a plurality of passivation material film layers; sequentially etching the plurality of passivation material film layers of the passivation layer to enable the passivation layer to form a regular trapezoid opening at the position where the pressure welding block is located; and forming a metal thickening layer on the surface of the pressure welding block through the regular trapezoid opening.
As an improvement of the method for manufacturing a bonding module of a semiconductor chip provided by the present invention, in a preferred embodiment, the plurality of passivation material film layers have different etching selection ratios, and when one passivation material film layer of the composite film layer is etched, no corrosion is caused to other passivation material film layers.
As an improvement of the method for manufacturing a bonding assembly of a semiconductor chip provided by the present invention, in a preferred embodiment, the plurality of passivation material films includes a first film, a second film and a third film sequentially formed on the surface of the semiconductor substrate from top to bottom.
As an improvement of the method for manufacturing a bonding assembly of a semiconductor chip provided in the present invention, in a preferred embodiment, the first film layer, the second film layer and the third film layer are a silicon nitride layer, a polysilicon layer and a silicon dioxide layer, respectively.
As an improvement of the method for manufacturing a bonding assembly of a semiconductor chip provided in the present invention, in a preferred embodiment, the step of sequentially etching the plurality of passivation material films of the passivation layer includes: coating a first photoresist on the surface of the silicon nitride layer, and etching the silicon nitride layer by using the first photoresist to form a first opening in the region of the silicon nitride layer corresponding to the pressure welding block.
As an improvement of the method for manufacturing a bonding assembly of a semiconductor chip provided in the present invention, in a preferred embodiment, the step of sequentially etching the plurality of passivation material films of the passivation layer further includes: and after the first opening is formed, etching the polycrystalline silicon layer through the first opening to form a second opening in the multilayer silicon layer, wherein the opening width of the second opening is larger than that of the first opening.
As an improvement of the method for manufacturing a bonding assembly of a semiconductor chip provided in the present invention, in a preferred embodiment, the step of sequentially etching the plurality of passivation material films of the passivation layer further includes: after the second opening is formed, etching the silicon dioxide layer through the first opening and the second opening to form a third opening in the silicon dioxide, wherein the opening width of the third opening is greater than the opening width of the second opening.
As an improvement of the method for manufacturing a bonding assembly of a semiconductor chip provided by the present invention, in a preferred embodiment, the silicon nitride layer is etched in an isotropic or anisotropic manner, and the polysilicon layer and the silicon dioxide layer are etched in an isotropic manner.
As an improvement of the method for manufacturing a bonding assembly of a semiconductor chip provided in the present invention, in a preferred embodiment, the trapezoidal openings include the first opening, the second opening, and the third opening, and the opening widths of the first opening, the second opening, and the third opening are all smaller than the width of the bonding pad.
As an improvement of the method for manufacturing a bonded assembly of a semiconductor chip provided in the present invention, in a preferred embodiment, the metal thickening layer is located inside the regular trapezoid opening, and the metal thickening layer is automatically broken at an edge position of the bonding pad during the growth process of the metal thickening layer.
Compared with the prior art, the manufacturing method of the bonding assembly of the semiconductor chip provided by the invention has the advantages that the material combination of the passivation layer composite film layer is changed, different corrosion amounts are adopted for different film layers in the composite film layer in the passivation layer etching process, so that the inverted trapezoidal structure similar to the stripping process is formed, and the thickened metal layer is grown on the basis of the bonding block subsequently, so that the bonding assembly with the thickness meeting the requirement is formed. According to the manufacturing method of the pressure welding assembly of the semiconductor chip, the metal thickening layer formed on the surface of the pressure welding block does not need to be stripped, so that the manufacturing cost of the chip can be effectively reduced; in addition, the metal thickening layer does not grow on the photoresist, and the influence of the temperature of the metal during growth on the photoresist does not exist, so that the difficulty in process implementation is reduced. Furthermore, because the passivation layer is a composite film layer comprising a plurality of passivation material film layers, and the transverse corrosion amount of each passivation material film layer can be freely controlled, an inverted ladder-shaped structure with an inclination angle meeting the preset requirement can be formed, so that the metal thickening layer at the pressure welding block is completely disconnected from other areas when the metal thickening layer grows.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
FIG. 1 is a schematic flow chart illustrating a method for fabricating a bonding assembly of a semiconductor chip according to an embodiment of the present invention;
fig. 2 ~ fig. 7 is a schematic diagram illustrating the process steps of the method for fabricating a bonded assembly of the semiconductor die of fig. 1.
[ detailed description ] embodiments
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a method for manufacturing a bonding assembly of a semiconductor chip, which aims to solve the problem of thickening of a bonding block in the prior art, improve the feasibility of the process and reduce the process cost.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a bonding assembly of a semiconductor chip according to an embodiment of the present invention. The manufacturing method of the bonding assembly of the semiconductor chip mainly comprises the following steps:
step S1, forming a pressure welding block on the surface of the semiconductor substrate;
specifically, referring to fig. 2, a semiconductor substrate, such as a silicon substrate, is provided, and based on a chip circuit design, a chip circuit structure and metal traces are fabricated on the silicon substrate. After the chip circuit structure and the metal routing are formed, a bonding block is formed in a preset area on the surface of the semiconductor substrate, wherein the bonding block is a metal block, such as a copper block, and is mainly used for routing when the semiconductor chip is packaged, namely, a metal connecting wire is manufactured when the semiconductor chip is packaged.
Step S2, forming a passivation layer on the surface of the semiconductor substrate, wherein the passivation layer covers the pressure welding block and is a composite film layer comprising a plurality of passivation material film layers;
referring to fig. 3, in an embodiment, the passivation layer is a composite film layer including a plurality of passivation material film layers, and the passivation material film layers have different etching selection ratios, that is, when one passivation material film layer of the composite film layer is etched, no significant corrosion is caused to other passivation material film layers. In this embodiment, the composite film layer is described as having three passivation material film layers, it should be understood that in other alternative embodiments, the number of the passivation material film layers may be determined according to the design requirement of the actual chip, and the application is not particularly limited thereto.
In addition, in this embodiment, as shown in fig. 3, the three passivation materials may be a silicon dioxide layer (layer 3), a polysilicon layer (layer 2) and a silicon nitride layer (layer 1), respectively, wherein the silicon dioxide layer is formed on the surface of the semiconductor substrate and covers the bonding pad as a whole, the polysilicon layer is formed on the surface of the silicon dioxide layer, and the silicon nitride layer is formed on the surface of the polysilicon layer. That is, the silicon nitride layer (first film layer or film layer 1), the polysilicon layer (second film layer or film layer 2), and the silicon dioxide layer (third film layer or film layer 3) are sequentially formed on the surface of the semiconductor substrate from top to bottom.
Step S3, sequentially etching the plurality of passivation material film layers of the passivation layer to enable the passivation layer to form a regular trapezoid opening at the position of the pressure welding block;
specifically, referring to fig. 4, in step S3 of the present embodiment, a first photoresist is first coated on a surface of the silicon nitride layer, and the silicon nitride layer is etched by using the first photoresist, so that a first opening is formed in a region of the silicon nitride layer corresponding to the bonding pad, and an opening width of the first opening is smaller than a width of the bonding pad. The silicon nitride layer can be etched in an isotropic etching mode or an anisotropic etching mode.
Then, referring to fig. 5, after the first opening is formed, the photoresist on the surface of the silicon nitride layer is retained, and the polysilicon layer is etched by an isotropic etching method. Because the polycrystalline silicon layer and the silicon nitride layer have different etching selection ratios, the silicon nitride layer is not influenced when the polycrystalline silicon layer is subjected to isotropic etching, and the silicon nitride layer is not corroded basically in the etching process of the polycrystalline silicon layer, so that the first opening of the silicon nitride layer basically keeps the original width. And because the polycrystalline silicon layer adopts an isotropic etching mode, the second opening formed on the polycrystalline silicon layer has a certain concave relative to the side wall of the first opening of the silicon nitride layer, namely, the opening width of the second opening of the polycrystalline silicon layer is larger than that of the first opening of the silicon nitride layer.
Referring to fig. 6, after the second opening is formed, the silicon dioxide layer is continuously etched, and the silicon dioxide layer is also etched in an isotropic etching manner. Similarly, since the silicon dioxide layer has different etching selection ratios with the polysilicon layer and the silicon nitride layer, the first opening of the silicon nitride layer and the second opening of the polysilicon layer are kept at the original widths during the etching of the silicon dioxide layer, and the opening width of the third opening formed by etching the silicon dioxide layer is larger than that of the second opening of the silicon dioxide layer, but preferably, the opening width of the third opening is smaller than that of the bonding pad.
Therefore, after the etching in step S3, the widths of the openings of the plurality of passivation material film layers of the passivation layer are sequentially increased at the positions corresponding to the bonding pads, so that the regular trapezoid-shaped openings are formed at the positions of the bonding pads, and the bonding pads are exposed through the regular trapezoid-shaped openings.
It should be understood that the above embodiments are only described by taking three passivation material film layers as an example, in other embodiments, when the number of the passivation material film layers of the passivation layer may also be any other value, no special limitation is made in this application, and when the number of the passivation material film layers is other values, reference may be made to the etching manner in step S3, and details are not described here again.
And step S4, forming a metal thickening layer on the surface of the pressure welding block through the regular trapezoid opening, wherein the metal thickening layer is positioned in the regular trapezoid opening and forms a pressure welding unit for routing with the pressure welding block.
Referring to fig. 7, in step S4, after the formation of the regular trapezoid opening, the photoresist on the surface of the silicon nitride layer is first removed, and then a metal thickening layer is grown on the surface of the pad through the regular trapezoid opening. Since the passivation layer has a regular trapezoid opening with a larger inclination angle at the position of the bonding pad before the growth of the metal thickening layer, the passivation layer is automatically broken at the edge position of the bonding pad during the growth of the metal thickening layer, and therefore, the metal thickening layer at the region outside the bonding pad does not need to be removed through an etching process. Since the metal thickening layer is formed on the surface of the bonding pad through the regular trapezoid opening, the metal thickening layer is located inside the regular trapezoid opening after being subjected to star finishing, and forms a bonding unit for subsequent wire bonding with the bonding pad, as shown in fig. 7.
Therefore, according to the manufacturing method of the pressure welding assembly of the semiconductor chip, the metal thickening layer formed on the surface of the pressure welding block does not need to be stripped, and the manufacturing cost of the chip can be effectively reduced; in addition, the metal thickening layer does not grow on the photoresist, and the influence of the temperature of the metal during growth on the photoresist does not exist, so that the difficulty in process implementation is reduced. Furthermore, because the passivation layer is a composite film layer comprising a plurality of passivation material film layers, and the transverse corrosion amount of each passivation material film layer can be freely controlled, an inverted ladder-shaped structure with an inclination angle meeting the preset requirement can be formed, so that the metal thickening layer at the pressure welding block is completely disconnected from other areas when the metal thickening layer grows.
While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.
Claims (3)
1. A method for manufacturing a bonding assembly of a semiconductor chip is characterized by comprising the following steps:
forming a pressure welding block on the surface of the semiconductor substrate;
forming a passivation layer on the surface of the semiconductor substrate, wherein the passivation layer covers the pressure welding block and is a composite film layer comprising a plurality of passivation material film layers; the plurality of passivation material film layers comprise a first film layer, a second film layer and a third film layer which are sequentially formed on the surface of the semiconductor substrate from top to bottom; the first film layer, the second film layer and the third film layer are respectively a silicon nitride layer, a polycrystalline silicon layer and a silicon dioxide layer;
sequentially etching the plurality of passivation material film layers of the passivation layer to enable the passivation layer to form a regular trapezoid opening at the position where the pressure welding block is located;
forming a metal thickening layer on the surface of the pressure welding block through the regular trapezoid opening;
the step of sequentially etching the plurality of passivation material film layers of the passivation layer comprises the following steps:
coating a first photoresist on the surface of the silicon nitride layer, and etching the silicon nitride layer by using the first photoresist to form a first opening in the region of the silicon nitride layer corresponding to the pressure welding block;
the step of sequentially etching the plurality of passivation material film layers of the passivation layer further comprises:
after the first opening is formed, etching the polycrystalline silicon layer through the first opening to form a second opening in the polycrystalline silicon layer, wherein the opening width of the second opening is larger than that of the first opening;
the step of sequentially etching the plurality of passivation material film layers of the passivation layer further comprises:
after the second opening is formed, etching the silicon dioxide layer through the first opening and the second opening to form a third opening in the silicon dioxide, wherein the opening width of the third opening is larger than that of the second opening;
the silicon nitride layer is etched in an isotropic or anisotropic mode, and the polycrystalline silicon layer and the silicon dioxide layer are etched in an isotropic mode; the regular trapezoid opening comprises the first opening, the second opening and the third opening, and the opening widths of the first opening, the second opening and the third opening are all smaller than the width of the pressure welding block.
2. The method of claim 1, wherein the plurality of passivation material film layers have different etching selection ratios, and when one passivation material film layer of the composite film layer is etched, the other passivation material film layers are not corroded.
3. Method according to any one of claims 1 to 2, characterized in that said metal thickening layer is located inside said trapezium-shaped openings, said metal thickening layer automatically breaking at the edge positions of said pads during the growth thereof.
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Address after: 518000 Guangdong Province, Shenzhen New District of Longhua City, Dalang Street Lang Kou community Hua Chang Lu Hua Chang Industrial Zone second 1-3 Patentee after: Shenzhen Jinyu Semiconductor Co.,Ltd. Address before: 518000 Guangdong Province, Shenzhen New District of Longhua City, Dalang Street Lang Kou community Hua Chang Lu Hua Chang Industrial Zone second 1-3 Patentee before: SHENZHEN JINYU SEMICONDUCTOR Co.,Ltd. |
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Denomination of invention: Manufacturing method of pressure welding assembly of semiconductor chip Effective date of registration: 20210729 Granted publication date: 20200114 Pledgee: Shenzhen small and medium sized small loan Co.,Ltd. Pledgor: Shenzhen Jinyu Semiconductor Co.,Ltd. Registration number: Y2021440020069 |
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