CN103094134B - Method and chip of increasing thickness of metal layer of chip bonding block area - Google Patents
Method and chip of increasing thickness of metal layer of chip bonding block area Download PDFInfo
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- CN103094134B CN103094134B CN201110338607.7A CN201110338607A CN103094134B CN 103094134 B CN103094134 B CN 103094134B CN 201110338607 A CN201110338607 A CN 201110338607A CN 103094134 B CN103094134 B CN 103094134B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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Abstract
The invention discloses a method and a chip of increasing thickness of a metal layer of a chip bonding block area, so that the thickness of the metal layer of the chip bonding block area in the chip is increased, and the probability of punching the metal layer of the chip bonding block area in the process of wire bonding of the chip is lowered. The method of increasing the thickness of the metal layer of the chip bonding block area comprises the following steps. A passivation layer is deposited on a first metal layer of the chip, and the first metal layer covers a silicon substrate with the bonding block area; the passivation layer is coated with a photoetching glue layer; the photoetching glue layer is conducted with exposure and etching, and the photoresist in the bonding block area covering the chip is etched away; the passivation layer is conducted with isotropic etching, the passivation layer which covers the bonding block area and a part of the passivation layer which is covered by the photoetching glue layer are etched away, and the metal layer, covering the bonding block area, of the first metal layer is bared; second metal layers are generated on the photoetching glue layer and the metal layer which covers the bonding block area; stripping liquid is adopted to dissolve the photoetching glue layer so as to eliminate the photoetching glue layer and strip the metal layer which covers the photoetching glue layer.
Description
Technical field
The present invention relates to semiconductor chip and manufacture field, particularly relate to a kind of method and the chip that increase the metal layer thickness in chip pressure welding block region.
Background technology
At present, in the process of packaged chip, need to carry out routing to chip, routing position is mainly distributed in the press welding block region on chip, but at present because the metal layer thickness in press welding block region is thinner, be therefore easy to occur that metal level (generally this metal level is aluminium lamination) is by the problem of punching in bonding process.
Along with the development of chip package process, because copper cash has cheap, that resistivity is low, thermal conductance is high and hardness is higher advantage, therefore, adopt copper cash as the wire rod of routing in the process of chip being carried out to routing; But copper cash hardness is comparatively large, therefore higher to the thickness requirement of the metal level in the press welding block region of chip.
At present for avoiding the metal level in press welding block region in bonding process by the problem of punching, adopt following solution: when making chip, when making the metal level on chip, the thickness of appropriate increase metal level, thus the metal level in press welding block region on chip is also increased accordingly.Adopt existing solution, although the metal level that can reduce press welding block region to a certain extent in bonding process by the probability punched, after but the metal level of chip thickeies, larger difficulty is brought to follow-up etching metal level when wiring, those skilled in the art should easy understand, when strip width/spacing is all identical, the thicker difficulty etched this metal level of metal level is larger; Therefore, for reducing the follow-up difficulty etched metal level when wiring, needing compromise to consider, generally, the metal level on chip being increased to the thickness of 10%; But when routing being carried out to chip owing to adopting copper cash, the words only metal level being increased to the thickness of 10% still can not meet copper cash to press welding block regional metal layer and thickness requirement, still there is the metal level in press welding block region by the problem of punching.
Summary of the invention
The embodiment of the present invention provides a kind of method and the chip that increase the metal layer thickness in chip pressure welding block region, to increase the thickness of the metal level in press welding block region in chip, reduces probability chip being carried out to the metal level punching press welding block region in bonding process.
Increase a method for the metal layer thickness in chip pressure welding block region, comprising:
Deposit passivation layer on the first metal layer of described chip, described the first metal layer cover be provided with press welding block region silicon substrate on;
Described passivation layer applies photoresist layer;
Described photoresist layer is exposed and etches, the photoresist in the press welding block region covered on chip is etched away;
Isotropic etching is carried out to described passivation layer, to the passivation layer in described press welding block region be covered and be etched away by the partial deactivation layer that photoresist layer covers, with the etched surface making the etched surface of passivation layer be greater than photoresist layer, and the etched surface of passivation layer covers the etched surface of photoresist layer completely; The metal level in described press welding block region is covered in exposed described the first metal layer;
Metal deposition is carried out to described chip, described photoresist layer with the metal level covering press welding block region generate the second metal level;
Stripper is adopted to dissolve photoresist layer, to remove photoresist layer and to peel off in the second metal level the metal level covered on photoresist layer.
Preferably, the thickness of described second metal level is lower than the thickness of passivation layer, and the thickness of the thickness of described the first metal layer and described second metal level and be worth, be greater than the routing degree of depth of described chip being carried out to routing, the degree of depth of the described routing degree of depth for adopting metal wire described chip to be carried out to the groove that metal wire described in bonding process is formed in described press welding block region.
Preferably, described metal wire is copper cash.
Preferably, described the first metal layer and described second metal level are aluminium lamination, and it is the aluminium of 99.5% and the copper of 0.5% that described aluminium lamination comprises proportion.
Based on the method for the metal layer thickness in aforementioned increase chip pressure welding block region, the embodiment of the present invention also provides a kind of chip, and this chip comprises:
Be provided with the silicon substrate in press welding block region;
Cover the first metal layer on described silicon substrate and press welding block region, the metal level covering described press welding block region in described the first metal layer is provided with the second metal level, and the region overlay in described the first metal layer except covering the metal level in described press welding block region has passivation layer.
Preferably, the thickness of described second metal level is lower than the thickness of described passivation layer, and the thickness of the thickness of described the first metal layer and described second metal level be greater than the routing degree of depth with value, the degree of depth of the described routing degree of depth for adopting metal wire described chip to be carried out to the groove that metal wire described in bonding process is formed in described press welding block region.
Preferably, described metal wire is copper cash.
Preferably, described the first metal layer and described second metal level are aluminium lamination, and it is the aluminium of 99.5% and the copper of 0.5% that described aluminium lamination comprises proportion.
In the embodiment of the present invention, on the one hand, not only the first metal layer is coated with but also be coated with the second metal level in the press welding block region of chip, therefore, materially increase the metal level covering press welding block region, reduce probability chip being carried out to the metal level punching press welding block region in bonding process; In addition, because the metal level in other regions in silicon substrate does not thicken, the difficulty that the metal level in other regions is etched can not therefore be increased; Two on the one hand, isotropic etching is carried out to passivation layer, to the passivation layer in described press welding block region be covered and be etched away by the partial deactivation layer that photoresist layer covers, with the etched surface making the etched surface of passivation layer be greater than photoresist layer, and the etched surface of passivation layer covers the etched surface of photoresist layer completely; The metal level in described press welding block region is covered in exposed described the first metal layer, therefore, in the process of subsequent deposition second metal level, be deposited on photoresist layer and be off state between metal level and the metal level being deposited on press welding block region, can not be connected with between the metal level covering argon spot area, therefore, after dissolving photoresist, the metal covered on photoresist layer is easier to peel off.
Accompanying drawing explanation
Fig. 1 is the method flow diagram of the metal layer thickness increasing chip pressure welding block region in the embodiment of the present invention;
Fig. 2 is the structural representation of deposit passivation layer on the first metal layer of chip in the embodiment of the present invention;
Fig. 3 is the structural representation applying photoresist layer in the embodiment of the present invention over the passivation layer;
Fig. 4 be in the embodiment of the present invention, photoresist layer is exposed, etch after structural representation;
Fig. 5 is the structural representation in the embodiment of the present invention, passivation layer being carried out to isotropic etching;
Fig. 6 rubs at the metal in photoresist layer and press welding block region the structural representation generating the second metal level in the embodiment of the present invention;
Fig. 7 is the structural representation that the embodiment of the present invention dissolves photoresist layer metal level above stripping photolithography glue-line.
Embodiment
For the problems referred to above that prior art exists, the embodiment of the present invention provides a kind of method and the chip that increase the metal layer thickness in chip pressure welding block region, to increase the thickness of the metal level in press welding block region in chip, reduce probability chip being carried out to the metal level punching press welding block region in bonding process.Increase the method for metal layer thickness in chip pressure welding block region, comprising: deposit passivation layer on the first metal layer of described chip, described the first metal layer cover be provided with press welding block region silicon substrate on; Described passivation layer applies photoresist layer; Described photoresist layer is exposed and etches, the photoresist in the press welding block region covered on chip is etched away; Isotropic etching is carried out to described passivation layer, to the passivation layer in described press welding block region be covered and be etched away by the partial deactivation layer that photoresist layer covers, with the etched surface making the etched surface of passivation layer be greater than photoresist layer, and the etched surface of passivation layer covers the etched surface of photoresist layer completely; The metal level in described press welding block region is covered in exposed described the first metal layer; Metal deposition is carried out to described chip, described photoresist layer with the metal level covering press welding block region generate the second metal level; Stripper is adopted to dissolve photoresist layer, to remove photoresist layer and to peel off in the second metal level the metal level covered on photoresist layer.
Carry out describing in detail, clearly to technical solution of the present invention below in conjunction with Figure of description.
See Fig. 1, for increasing the method flow diagram of the metal layer thickness in chip pressure welding block region in the embodiment of the present invention, the method comprises:
Step 101, on the first metal layer 1 of chip deposit passivation layer 2, described the first metal layer 1 cover be provided with press welding block region 3 silicon substrate on, as shown in Figure 2.
Step 102, on passivation layer 2, apply photoresist layer 4, as shown in Figure 3.
Step 103, photoresist layer 4 exposed and etches, the photoresist in the press welding block region 3 covered on chip being etched away, as shown in Figure 4.
Step 104, isotropic etching is carried out to passivation layer 2, to the passivation layer 2 in press welding block region 3 be covered and be etched away by the partial deactivation layer that photoresist layer 4 covers, with the etched surface making the etched surface of passivation layer 2 be greater than photoresist layer 4, and the etched surface of passivation layer 2 covers the etched surface of photoresist layer 4 completely; The metal level 11 in described press welding block region is covered, as shown in Figure 5 in exposed described the first metal layer 1.
Step 105, metal deposition is carried out to chip, photoresist layer 4 with the metal level 11 covering press welding block region 3 generate the second metal level 5, as shown in Figure 6.
Step 106, employing stripper dissolve photoresist layer 4, to remove photoresist layer 4 and to peel off in the second metal level 5 metal level covered on photoresist layer, as shown in Figure 7.
Preferably, for guaranteeing that the metal level in press welding block region avoids punching carrying out bonding process to chip further, in the embodiment of the present invention, as shown in Figure 7, the thickness d 1 of the second metal level 5 is lower than the thickness of passivation layer 2, and the thickness d 1 of the thickness d 2 of described the first metal layer 1 and described second metal level 5 and be worth, be greater than the routing degree of depth of described chip being carried out to routing, the degree of depth of the described routing degree of depth for adopting metal wire described chip to be carried out to the groove that metal wire described in bonding process is formed in described press welding block region 3.
Preferably, can be gold thread, aluminum steel or copper cash for carrying out the wire rod of routing to chip; Preferably, because copper cash has the advantages such as hardness is larger, oxidizable, so the metal wire adopted in the embodiment of the present invention is copper cash.
Preferably, owing to being the target better effects if of aluminium lamination of the aluminium of 99.5% and the copper of 0.5% containing proportion, therefore in the embodiment of the present invention, the first metal layer 2 and the second metal level 3 are aluminium lamination, and described aluminium lamination comprises proportion is the aluminium of 99.5% and the copper of 0.5%.
Based on aforesaid technological process, the embodiment of the present invention also provides a kind of chip, and the structure of this chip as shown in Figure 7, comprising:
Be provided with the silicon substrate in press welding block region;
Cover the first metal layer on described silicon substrate and press welding block region, the metal level covering described press welding block region in described the first metal layer is provided with the second metal level, and the region overlay in described the first metal layer except covering the metal level in described press welding block region has passivation layer.
Preferably, the thickness of described second metal level is lower than the thickness of described passivation layer, and the thickness of the thickness of described the first metal layer and described second metal level be greater than the routing degree of depth with value, the degree of depth of the described routing degree of depth for adopting metal wire described chip to be carried out to the groove that metal wire described in bonding process is formed in described press welding block region.
Preferably, described metal wire is copper cash.
Preferably, described the first metal layer and described second metal level are aluminium lamination, and it is the aluminium of 99.5% and the copper of 0.5% that described aluminium lamination comprises proportion.
In the embodiment of the present invention, on the one hand, not only the first metal layer is coated with but also be coated with the second metal level in the press welding block region of chip, therefore, materially increase the metal level covering press welding block region, reduce probability chip being carried out to the metal level punching press welding block region in bonding process; In addition, because the metal level in other regions in silicon substrate does not thicken, the difficulty that the metal level in other regions is etched can not therefore be increased; Two on the one hand, isotropic etching is carried out to passivation layer, to the passivation layer in described press welding block region be covered and be etched away by the partial deactivation layer that photoresist layer covers, with the etched surface making the etched surface of passivation layer be greater than photoresist layer, and the etched surface of passivation layer covers the etched surface of photoresist layer completely; The metal level in described press welding block region is covered in exposed described the first metal layer, therefore, in the process of subsequent deposition second metal level, be deposited on photoresist layer and be off state between metal level and the metal level being deposited on press welding block region, can not be connected with between the metal level covering argon spot area, therefore, after dissolving photoresist, the metal covered on photoresist layer is easier to peel off.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if belong within the scope of the claims in the present invention and equivalent technologies thereof to these amendments of the present invention and modification, then the present invention is also intended to comprise these change and modification.
Claims (4)
1. increase a method for the metal layer thickness in chip pressure welding block region, it is characterized in that, comprising:
Deposit passivation layer on the first metal layer of chip, described the first metal layer cover be provided with press welding block region silicon substrate on;
Described passivation layer applies photoresist layer;
Described photoresist layer is exposed and etches, the photoresist in the press welding block region covered on chip is etched away;
Isotropic etching is carried out to described passivation layer, to the passivation layer in described press welding block region be covered and be etched away by the partial deactivation layer that photoresist layer covers, with the etched surface making the etched surface of passivation layer be greater than photoresist layer, and the etched surface of passivation layer covers the etched surface of photoresist layer completely; The metal level in described press welding block region is covered in exposed described the first metal layer;
Metal deposition is carried out to described chip, described photoresist layer with the metal level covering press welding block region generate the second metal level;
Stripper is adopted to dissolve photoresist layer, to remove photoresist layer and to peel off in the second metal level the metal level covered on photoresist layer.
2. the method for claim 1, it is characterized in that, the thickness of described second metal level is lower than the thickness of passivation layer, and the thickness of the thickness of described the first metal layer and described second metal level and be worth, be greater than the routing degree of depth of described chip being carried out to routing, the degree of depth of the described routing degree of depth for adopting metal wire described chip to be carried out to the groove that metal wire described in bonding process is formed in described press welding block region.
3. method as claimed in claim 2, it is characterized in that, described metal wire is copper cash.
4. the method as described in any one of claims 1 to 3, is characterized in that, described the first metal layer and described second metal level are aluminium lamination, and it is the aluminium of 99.5% and the copper of 0.5% that described aluminium lamination comprises proportion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110338607.7A CN103094134B (en) | 2011-10-31 | 2011-10-31 | Method and chip of increasing thickness of metal layer of chip bonding block area |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110338607.7A CN103094134B (en) | 2011-10-31 | 2011-10-31 | Method and chip of increasing thickness of metal layer of chip bonding block area |
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| CN103094134A CN103094134A (en) | 2013-05-08 |
| CN103094134B true CN103094134B (en) | 2015-07-15 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108109925B (en) * | 2017-12-12 | 2020-08-14 | 温州曼昔维服饰有限公司 | Method for manufacturing pressure welding module of semiconductor chip |
| CN108133922B (en) * | 2017-12-14 | 2020-01-14 | 深圳市金誉半导体有限公司 | Method for manufacturing pressure welding assembly of semiconductor chip |
| CN113270324A (en) * | 2021-05-13 | 2021-08-17 | 深圳中宝新材科技有限公司 | Metal pressure welding block thick aluminum process for bonding copper wire |
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| JPS60154547A (en) * | 1984-01-24 | 1985-08-14 | Nec Corp | Semiconductor device |
| CN1979837A (en) * | 2005-12-01 | 2007-06-13 | 上海华虹Nec电子有限公司 | Application method of press welding block on top of logic integrated circuit |
| CN201336308Y (en) * | 2009-01-16 | 2009-10-28 | Bcd半导体制造有限公司 | Integrated circuit chip structure |
| CN101740428A (en) * | 2009-12-15 | 2010-06-16 | 无锡中微晶园电子有限公司 | Aluminum thickening process for metal pressure-welding block for bonding copper wire |
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2011
- 2011-10-31 CN CN201110338607.7A patent/CN103094134B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60154547A (en) * | 1984-01-24 | 1985-08-14 | Nec Corp | Semiconductor device |
| CN1979837A (en) * | 2005-12-01 | 2007-06-13 | 上海华虹Nec电子有限公司 | Application method of press welding block on top of logic integrated circuit |
| CN201336308Y (en) * | 2009-01-16 | 2009-10-28 | Bcd半导体制造有限公司 | Integrated circuit chip structure |
| CN101740428A (en) * | 2009-12-15 | 2010-06-16 | 无锡中微晶园电子有限公司 | Aluminum thickening process for metal pressure-welding block for bonding copper wire |
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Effective date of registration: 20220719 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District Cheng Fu Road 298, founder building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |
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