CN201336308Y - Integrated circuit chip structure - Google Patents
Integrated circuit chip structure Download PDFInfo
- Publication number
- CN201336308Y CN201336308Y CN 200920002913 CN200920002913U CN201336308Y CN 201336308 Y CN201336308 Y CN 201336308Y CN 200920002913 CN200920002913 CN 200920002913 CN 200920002913 U CN200920002913 U CN 200920002913U CN 201336308 Y CN201336308 Y CN 201336308Y
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- integrated circuit
- metal
- circuit chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The utility model provides an integrated circuit chip structure, which comprises a semi-conductor underlay, structures such as a N-shaped or P-shaped doping area, polycrystalline silicon, an insulation layer and multiple layers of metal wirings, which are arranged on the semi-conductor underlay, a passivation layer which is precipitated on the above structure and is provided with a plurality of connection holes which are formed by photoetching, and multiple top layers of metal areas which are galvanized on the connection holes, wherein, the lower part of the top layers of metal areas is provided with a blocking layer, and the upper layer is provided with a protection layer. The top layer of metal layers can effectively increase the thickness of the local metal layer of the power part and can be used as a pressure welding metal layer which is arranged on the active parts, thereby reducing the area of the chip; moreover, a copper sealing technique is directly utilized, so that the production cost of the integrated circuit is reduced.
Description
Technical field
The utility model relates to integrated circuit (IC) chip and makes the field, and is particularly related to a kind of integrated circuit chip structure.
Background technology
Usually, integrated circuit (IC) chip all needs the pressure welding metal area that is used to encapsulate bonding of independent chip occupying area, under the promptly general pressure welding metal area, can not place active device, particularly for the integrated circuit of single-layer metal and double-level-metal.Please refer to Fig. 1, Figure 1 shows that prior art integrated circuit chip structure schematic diagram.Deposit insulating barrier 20 on the Semiconductor substrate 10, insulating barrier 20 can be SiO
2Dielectric layer, deposit Al metal level 30 spaced apart on the insulating barrier 20 as the pressure welding metal level, deposit passivation layer 40 on the said structure, has the pressure welding point spaced apart 50 that photoetching forms on the passivation layer 40, as seen, the pressure welding metal level has only insulating barrier 20 and Semiconductor substrate 10 for 30 times, and does not have active device, and passivation layer 40 is arranged on the pressure welding metal level 30.
Along with the development of ic core chip technology, the application of power tube more and more widely, and is also more and more higher for the parameter request of power tube.When being integrated into power tube in the circuit, can produce power tube needs thick metal level and the contradiction of the metal level that other parts of circuit only need approach.Make thick metal level and need the design rule of large-size (live width/spacing), thereby increased chip area, this and the chip requirement of miniaturization day by day run in the opposite direction, because the increase of chip size certainly will reduce producible number of chips on the same wafer, reduced output and improved production cost simultaneously.Also can adopt the method for multiple layer metal to solve the problem of power tube metal thickness in the prior art, but need increase by two photoetching levels at least like this.Above method has not only been brought the increase of cost, also owing to the restriction of technology, is difficult to the thickness of single-layer metal is accomplished more than the 4um.
Be to reduce packaging cost, when substituting gold thread and encapsulate with copper cash, because the copper bonding needs higher bonding power, the metal thickness of pressure welding metal area must reach more than the 3um, yet prior art faces equally and needs will challenging of thick metal layers.
The utility model content
The utility model proposes a kind of integrated circuit chip structure, by increasing a photoetching level and using the plated metal technology, can effectively increase the thickness of the localized metallic layer in power device and pressure welding zone, thereby reduce chip area, use the copper encapsulation technology, reduce the production cost of integrated circuit.
In order to achieve the above object, the utility model proposes a kind of integrated circuit chip structure, it comprises:
Semiconductor substrate;
N type or P type doped region, polysilicon, structures such as insulating barrier and multi-layer metal wiring are produced on the described Semiconductor substrate;
Passivation layer is deposited on the said structure, and it has the connecting hole that a plurality of photoetching form
A plurality of top-level metallics zone, plating is formed on described a plurality of connecting hole,
Wherein said a plurality of second metallic region bottom has the barrier layer, and top has protective layer.
Further, described barrier layer is Ti, TiN, Ta or TaN layer.
Further, the thickness on described barrier layer is 300 dusts～3000 dusts.
Further, described a plurality of second metallic region is a copper metal layer.
Further, the thickness of described a plurality of second metallic region is 3 μ m～50 μ m.
Further, described protective layer comprises Ni metal level and Sn or Au metal level.
Further, the thickness of described protective layer is 500 dusts～5000 dusts.
The integrated circuit chip structure that the utility model proposes, behind common integrated circuit passivation technology, by increasing a photoetching level and use the copper electroplating technology, with the thick copper metal layer preparation of 3um-50um on integrated circuit (IC) chip.When it is used as the pressure welding metal of chip, both can under thick copper pressure welding metal area, be placed with the source device, also can directly encapsulate with copper cash.When it is used as the metal of thickening power tube, the resistance of metal level is reduced, thereby reduce the area of power tube.In a word, adopt thick copper metal layer can dwindle chip area and reduction packaging cost, thereby reduce the integrated circuit cost.
Description of drawings
Figure 1 shows that the integrated circuit chip structure schematic diagram of prior art.
Figure 2 shows that the integrated circuit chip structure schematic diagram of the utility model preferred embodiment.
Figure 3 shows that the plane graph of the power tube of the utility model preferred embodiment.
Figure 4 shows that the profile of the power tube of the utility model preferred embodiment.
Embodiment
In order more to understand technology contents of the present utility model, especially exemplified by specific embodiment and cooperate appended graphic being described as follows.
The utility model proposes a kind of integrated circuit chip structure, the thickness that it can effectively increase power device localized metallic layer does not need to increase the photoetching level and do not need to increase chip size yet, has reduced production cost.
Please refer to Fig. 2, Figure 2 shows that the integrated circuit chip structure schematic diagram of the utility model preferred embodiment.The integrated circuit chip structure that the utility model proposes, it comprises: Semiconductor substrate 100; Insulating barrier 110 is deposited on the described Semiconductor substrate 100; A plurality of first metallic region 120 have the compartment of terrain and are deposited on the described insulating barrier 110; Passivation layer 130 is deposited on the said structure, and its connecting hole 140 with a plurality of photoetching formation is connected in described a plurality of first metallic region 120; A plurality of second metallic region 150, plating is formed on described a plurality of connecting hole 140, and wherein said a plurality of second metallic region 150 bottoms have barrier layer 160, and top has protective layer 170.
According to the utility model preferred embodiment, described insulating barrier 110 is a silicon oxide layer; Described first metallic region 120 is an aluminum metal layer, and its thickness is 0.5 μ m～4 μ m; Described passivation layer 130 is silica/silicon nitride composite bed; Described a plurality of second metallic region 150 is a copper metal layer, and its thickness is 3 μ m～50 μ m; Described barrier layer 160 is Ti, TiN, Ta or TaN layer, and its thickness is 300 dusts～3000 dusts; Described protective layer 170 comprises Ni metal level and Sn or Au metal level, and its thickness is 500 dusts～5000 dusts.
Behind common integrated circuit passivation technology, leave the connecting hole 140 that needs to connect copper metal layer 150 during by the passivation photoetching, increase the figure of photoetching level definition copper metal layer 150, electroplate through copper, with thick copper metal layer 150 preparations of 3um～50um on integrated circuit (IC) chip.Since the fast diffusion property of copper, 150 times needs barrier metal layers 160 of copper metal layer, and as Ti/TiN or Ta/TaN, because the easily oxidizable of copper, for the reliability of bonding, the metal level 170 that needs protection on the copper metal layer 150 is as Ni and Sn or Au.
Please refer to Fig. 3 and Fig. 4 again, Figure 3 shows that the plane graph of the power tube of the utility model preferred embodiment, Figure 4 shows that the profile of the power tube of the utility model preferred embodiment.Closed area shown in the chain-dotted line shown in Figure 3 is the comb that is connected with the PN junction dress metal electrode of power transistor, and closed area shown in the dotted line is the passivation connecting hole perforate on the metal electrode, and the solid line closed area is depicted as the copper metal.Among Fig. 4, because copper metal layer 150 is enough thick, the power rush that is enough to bear bonding, thus under thick copper pressure welding metal area, can place active device, and the Direct Bonding copper cash encapsulates.Copper metal layer 150 can be used to thicken the metal of power transistor, and the metal level resistance of power transistor is reduced, thereby reduces the area of power tube.The directly output of general power transistor, so the thick copper metal layer 150 on the power transistor also allows the encapsulation of copper cash Direct Bonding.
In sum, the integrated circuit chip structure that the utility model proposes and the difference of traditional structure are:
1.3um the thick copper metal layer of～50um, is different from traditional dielectric passivation as the final level of integrated circuit (IC) chip as final level;
2. thick copper metal layer can place active device under it and directly do the copper cash encapsulation, and the chip of traditional die, particularly single-layer metal and double-level-metal can not be placed active device under its pressure welding metal during as the pressure welding metal;
3. thick copper metal layer can be used for reducing the metal level resistance of power transistor in the integrated circuit, and directly does the copper cash encapsulation, and traditional die is not accomplished.
Though the utility model discloses as above with preferred embodiment, so it is not in order to limit the utility model.Have in the technical field under the utility model and know the knowledgeable usually, in not breaking away from spirit and scope of the present utility model, when being used for a variety of modifications and variations.Therefore, protection range of the present utility model is as the criterion when looking claims person of defining.
Claims (7)
1. integrated circuit chip structure is characterized in that comprising:
Semiconductor substrate;
N type or P type doped region, polysilicon, structures such as insulating barrier and multi-layer metal wiring are produced on the described Semiconductor substrate;
Passivation layer is deposited on the said structure, and it has the connecting hole that a plurality of photoetching form;
A plurality of top-level metallics zone, plating is formed on described a plurality of connecting hole,
Wherein said a plurality of second metallic region bottom has the barrier layer, and top has protective layer.
2. integrated circuit chip structure according to claim 1 is characterized in that described barrier layer is Ti, TiN, Ta or TaN layer.
3. integrated circuit chip structure according to claim 1, the thickness that it is characterized in that described barrier layer are 300 dusts～3000 dusts.
4. integrated circuit chip structure according to claim 1 is characterized in that described a plurality of top-level metallics zone is copper metal layer.
5. integrated circuit chip structure according to claim 1, the thickness that it is characterized in that described a plurality of top-level metallics zone are 3 μ m～50 μ m.
6. integrated circuit chip structure according to claim 1 is characterized in that described protective layer comprises Ni metal level and Sn or Au metal level.
7. integrated circuit chip structure according to claim 1, the thickness that it is characterized in that described protective layer are 500 dusts～5000 dusts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200920002913 CN201336308Y (en) | 2009-01-16 | 2009-01-16 | Integrated circuit chip structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200920002913 CN201336308Y (en) | 2009-01-16 | 2009-01-16 | Integrated circuit chip structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201336308Y true CN201336308Y (en) | 2009-10-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200920002913 Expired - Fee Related CN201336308Y (en) | 2009-01-16 | 2009-01-16 | Integrated circuit chip structure |
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| CN (1) | CN201336308Y (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102064154A (en) * | 2009-11-05 | 2011-05-18 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
| CN102237327A (en) * | 2010-05-05 | 2011-11-09 | 北大方正集团有限公司 | Chip with thickened metal layer of press welding block and manufacturing method for chip |
| CN102543717A (en) * | 2012-01-13 | 2012-07-04 | 杭州矽力杰半导体技术有限公司 | Metal layer structure of semiconductor device as well as manufacturing method of metal layer structure and semiconductor device using metal layer structure |
| CN103050418A (en) * | 2011-10-13 | 2013-04-17 | 北大方正集团有限公司 | Pad manufacturing method and pad |
| CN103094134A (en) * | 2011-10-31 | 2013-05-08 | 北大方正集团有限公司 | Method and chip of increasing thickness of metal layer of chip bonding block area |
| CN103426848A (en) * | 2012-05-25 | 2013-12-04 | 北大方正集团有限公司 | Chip and manufacturing method thereof |
-
2009
- 2009-01-16 CN CN 200920002913 patent/CN201336308Y/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102064154A (en) * | 2009-11-05 | 2011-05-18 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
| CN102064154B (en) * | 2009-11-05 | 2012-10-03 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
| CN102237327A (en) * | 2010-05-05 | 2011-11-09 | 北大方正集团有限公司 | Chip with thickened metal layer of press welding block and manufacturing method for chip |
| CN103050418A (en) * | 2011-10-13 | 2013-04-17 | 北大方正集团有限公司 | Pad manufacturing method and pad |
| CN103050418B (en) * | 2011-10-13 | 2015-05-27 | 北大方正集团有限公司 | Pad manufacturing method and pad |
| CN103094134A (en) * | 2011-10-31 | 2013-05-08 | 北大方正集团有限公司 | Method and chip of increasing thickness of metal layer of chip bonding block area |
| CN103094134B (en) * | 2011-10-31 | 2015-07-15 | 北大方正集团有限公司 | Method and chip of increasing thickness of metal layer of chip bonding block area |
| CN102543717A (en) * | 2012-01-13 | 2012-07-04 | 杭州矽力杰半导体技术有限公司 | Metal layer structure of semiconductor device as well as manufacturing method of metal layer structure and semiconductor device using metal layer structure |
| CN102543717B (en) * | 2012-01-13 | 2014-03-12 | 矽力杰半导体技术(杭州)有限公司 | Semiconductor device |
| CN103426848A (en) * | 2012-05-25 | 2013-12-04 | 北大方正集团有限公司 | Chip and manufacturing method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20091028 Termination date: 20150116 |
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| EXPY | Termination of patent right or utility model |