CN103094134A - Method and chip of increasing thickness of metal layer of chip bonding block area - Google Patents
Method and chip of increasing thickness of metal layer of chip bonding block area Download PDFInfo
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- CN103094134A CN103094134A CN2011103386077A CN201110338607A CN103094134A CN 103094134 A CN103094134 A CN 103094134A CN 2011103386077 A CN2011103386077 A CN 2011103386077A CN 201110338607 A CN201110338607 A CN 201110338607A CN 103094134 A CN103094134 A CN 103094134A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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Abstract
The invention discloses a method and a chip of increasing thickness of a metal layer of a chip bonding block area, so that the thickness of the metal layer of the chip bonding block area in the chip is increased, and the probability of punching the metal layer of the chip bonding block area in the process of wire bonding of the chip is lowered. The method of increasing the thickness of the metal layer of the chip bonding block area comprises the following steps. A passivation layer is deposited on a first metal layer of the chip, and the first metal layer covers a silicon substrate with the bonding block area; the passivation layer is coated with a photoetching glue layer; the photoetching glue layer is conducted with exposure and etching, and the photoresist in the bonding block area covering the chip is etched away; the passivation layer is conducted with isotropic etching, the passivation layer which covers the bonding block area and a part of the passivation layer which is covered by the photoetching glue layer are etched away, and the metal layer, covering the bonding block area, of the first metal layer is bared; second metal layers are generated on the photoetching glue layer and the metal layer which covers the bonding block area; stripping liquid is adopted to dissolve the photoetching glue layer so as to eliminate the photoetching glue layer and strip the metal layer which covers the photoetching glue layer.
Description
Technical field
The present invention relates to semiconductor chip and make the field, relate in particular to a kind of method and chip that increases the metal layer thickness in chip pressure welding piece zone.
Background technology
At present, in the process of packaged chip, need to carry out routing to chip, the routing position is mainly the press welding block zone that is distributed on chip, but at present the metal layer thickness due to the press welding block zone is thinner, therefore is easy to occur the problem that metal level (generally this metal level is aluminium lamination) is punched in the routing process.
Along with the development of chip package process, due to copper cash have advantages of cheap, resistivity is low, thermal conductance is high and hardness is higher, therefore, adopts copper cash as the wire rod of routing in the process of chip being carried out routing; Therefore but copper cash hardness is larger, and the thickness requirement to the metal level in the press welding block zone of chip is higher.
At present for avoiding the metal level problem that quilt is punched in the routing process in press welding block zone, adopt following solution: when making chip, during metal level on making chip, the thickness of appropriate increase metal level, thus make the metal level in press welding block zone on chip also increase accordingly.Adopt existing solution, although can reduce to a certain extent the metal level probability that quilt is punched in the routing process in press welding block zone, but after the thickening of the metal level of chip, metal level is carried out etching when the wiring and bring larger difficulty follow-up, those skilled in the art should easily understand, in the situation that bonding jumper width/spacing is all identical, metal level is thicker, and that this metal level is carried out etched difficulty is larger; Therefore, for reducing follow-up difficulty of metal level being carried out when the wiring etching, need compromise to consider, generally, the metal level on chip is increased by 10% thickness; But owing to adopting copper cash to carry out routing to chip, the words that only metal level increased by 10% thickness still can not satisfy copper cash to press welding block regional metal layer and thickness requirement, the problem that still exists the metal level in press welding block zone to be punched.
Summary of the invention
The embodiment of the present invention provides a kind of method and chip that increases the metal layer thickness in chip pressure welding piece zone, to increase the thickness of the metal level in press welding block zone in chip, reduces the probability that chip is carried out punching in the routing process metal level in press welding block zone.
A kind of method that increases the metal layer thickness in chip pressure welding piece zone comprises:
Deposit passivation layer on the first metal layer of described chip, described the first metal layer cover on the silicon substrate that is provided with the press welding block zone;
Apply photoresist layer on described passivation layer;
Described photoresist layer is exposed and etching, the photoresist that covers the press welding block zone on chip is etched away;
Described passivation layer is carried out isotropic etching, to cover the passivation layer in described press welding block zone and be etched away by the part passivation layer that photoresist layer covers, so that the etched surface of passivation layer is greater than the etched surface of photoresist layer, and the etched surface of passivation layer covers the etched surface of photoresist layer fully; Cover the metal level in described press welding block zone in exposed described the first metal layer;
Described chip is carried out metal deposition, generate the second metal level at described photoresist layer on the metal level in press welding block zone with covering;
Adopt stripper dissolving photoresist layer, to remove photoresist layer and to peel off the metal level that covers in the second metal level on photoresist layer.
Preferably, the thickness of described the second metal level is lower than the thickness of passivation layer, and the thickness of the thickness of described the first metal layer and described the second metal level and the value, greater than described chip being carried out the routing degree of depth of routing, the described routing degree of depth is for adopting metal wire to carry out metal wire described in the routing process in the degree of depth of the formed groove in described press welding block zone to described chip.
Preferably, described metal wire is copper cash.
Preferably, described the first metal layer and described the second metal level are aluminium lamination, and it is 99.5% aluminium and 0.5% copper that described aluminium lamination comprises proportion.
Based on the method for the metal layer thickness in aforementioned increase chip pressure welding piece zone, the embodiment of the present invention also provides a kind of chip, and this chip comprises:
Be provided with the silicon substrate in press welding block zone;
Cover the first metal layer on described silicon substrate and press welding block zone, cover in described the first metal layer on the metal level in described press welding block zone and be provided with the second metal level, the zone in described the first metal layer except the metal level that covers described press welding block zone is coated with passivation layer.
Preferably, the thickness of described the second metal level is lower than the thickness of described passivation layer, and the thickness of the thickness of described the first metal layer and described the second metal level with value greater than the routing degree of depth, the described routing degree of depth is for adopting metal wire to carry out metal wire described in the routing process in the degree of depth of the formed groove in described press welding block zone to described chip.
Preferably, described metal wire is copper cash.
Preferably, described the first metal layer and described the second metal level are aluminium lamination, and it is 99.5% aluminium and 0.5% copper that described aluminium lamination comprises proportion.
In the embodiment of the present invention, on the one hand, press welding block zone at chip not only is coated with the first metal layer but also be coated with the second metal level, therefore, increase to a great extent the metal level that covers the press welding block zone, reduced the probability that chip is carried out punching in the routing process metal level in press welding block zone; In addition, due to not thickening of other the regional metal levels in silicon substrate, therefore can not increase other regional metal levels are carried out etched difficulty; Two on the one hand, passivation layer is carried out isotropic etching, to cover the passivation layer in described press welding block zone and be etched away by the part passivation layer that photoresist layer covers, so that the etched surface of passivation layer is greater than the etched surface of photoresist layer, and the etched surface of passivation layer covers the etched surface of photoresist layer fully; Cover the metal level in described press welding block zone in exposed described the first metal layer, therefore, in the process of subsequent deposition the second metal level, be deposited on metal level on photoresist layer and be deposited between the metal level in press welding block zone and be off-state, can not be connected between the metal level regional with covering argon welding point, therefore, after the dissolving photoresist, the metal that covers on photoresist layer is easier to peel off.
Description of drawings
Fig. 1 is the method flow diagram of the metal layer thickness in increase chip pressure welding piece zone in the embodiment of the present invention;
Fig. 2 be in the embodiment of the present invention on the first metal layer of chip the structural representation of deposit passivation layer;
Fig. 3 applies the structural representation of photoresist layer on passivation layer in the embodiment of the present invention;
Fig. 4 be in the embodiment of the present invention to photoresist layer expose, structural representation after etching;
Fig. 5 carries out the structural representation of isotropic etching to passivation layer in the embodiment of the present invention;
Fig. 6 is that in the embodiment of the present invention, the metal in photoresist layer and press welding block zone rubs the structural representation that generates the second metal level;
Fig. 7 is the structural representation of embodiment of the present invention dissolving photoresist layer and the metal level above the stripping photolithography glue-line.
Embodiment
The problems referred to above for the prior art existence, the embodiment of the present invention provides a kind of method and chip that increases the metal layer thickness in chip pressure welding piece zone, to increase the thickness of the metal level in press welding block zone in chip, reduce the probability that chip is carried out punching in the routing process metal level in press welding block zone.The method of the metal layer thickness in increase chip pressure welding piece zone, comprising: deposit passivation layer on the first metal layer of described chip, described the first metal layer cover on the silicon substrate that is provided with the press welding block zone; Apply photoresist layer on described passivation layer; Described photoresist layer is exposed and etching, the photoresist that covers the press welding block zone on chip is etched away; Described passivation layer is carried out isotropic etching, to cover the passivation layer in described press welding block zone and be etched away by the part passivation layer that photoresist layer covers, so that the etched surface of passivation layer is greater than the etched surface of photoresist layer, and the etched surface of passivation layer covers the etched surface of photoresist layer fully; Cover the metal level in described press welding block zone in exposed described the first metal layer; Described chip is carried out metal deposition, generate the second metal level at described photoresist layer on the metal level in press welding block zone with covering; Adopt stripper dissolving photoresist layer, to remove photoresist layer and to peel off the metal level that covers in the second metal level on photoresist layer.
Below in conjunction with Figure of description, technical solution of the present invention is carried out in detail, clearly described.
Referring to Fig. 1, be the method flow diagram of the metal layer thickness in increase chip pressure welding piece zone in the embodiment of the present invention, the method comprises:
Preferably, avoid punching chip is carried out the routing process for the metal level of further guaranteeing the press welding block zone, in the embodiment of the present invention, as shown in Figure 7, the thickness d 1 of the second metal level 5 is lower than the thickness of passivation layer 2, and the thickness d 2 of described the first metal layer 1 and the thickness d 1 of described the second metal level 5 and value, greater than described chip being carried out the routing degree of depth of routing, the described routing degree of depth is for adopting metal wire to carry out metal wire described in the routing process in the degree of depth of the regional 3 formed grooves of described press welding block to described chip.
Preferably, can be gold thread, aluminum steel or copper cash for the wire rod that chip is carried out routing; Preferably, hardness is large, the easy advantage such as oxidation because copper cash has, so the metal wire that adopts in the embodiment of the present invention is copper cash.
Preferably, owing to containing the target better effects if of aluminium lamination that proportion is the copper of 99.5% aluminium and 0.5%, so in the embodiment of the present invention, the first metal layer 2 and the second metal level 3 are aluminium lamination, and described aluminium lamination to comprise proportion be 99.5% aluminium and 0.5% copper.
Based on aforesaid technological process, the embodiment of the present invention also provides a kind of chip, and the structure of this chip comprises as shown in Figure 7:
Be provided with the silicon substrate in press welding block zone;
Cover the first metal layer on described silicon substrate and press welding block zone, cover in described the first metal layer on the metal level in described press welding block zone and be provided with the second metal level, the zone in described the first metal layer except the metal level that covers described press welding block zone is coated with passivation layer.
Preferably, the thickness of described the second metal level is lower than the thickness of described passivation layer, and the thickness of the thickness of described the first metal layer and described the second metal level with value greater than the routing degree of depth, the described routing degree of depth is for adopting metal wire to carry out metal wire described in the routing process in the degree of depth of the formed groove in described press welding block zone to described chip.
Preferably, described metal wire is copper cash.
Preferably, described the first metal layer and described the second metal level are aluminium lamination, and it is 99.5% aluminium and 0.5% copper that described aluminium lamination comprises proportion.
In the embodiment of the present invention, on the one hand, press welding block zone at chip not only is coated with the first metal layer but also be coated with the second metal level, therefore, increase to a great extent the metal level that covers the press welding block zone, reduced the probability that chip is carried out punching in the routing process metal level in press welding block zone; In addition, due to not thickening of other the regional metal levels in silicon substrate, therefore can not increase other regional metal levels are carried out etched difficulty; Two on the one hand, passivation layer is carried out isotropic etching, to cover the passivation layer in described press welding block zone and be etched away by the part passivation layer that photoresist layer covers, so that the etched surface of passivation layer is greater than the etched surface of photoresist layer, and the etched surface of passivation layer covers the etched surface of photoresist layer fully; Cover the metal level in described press welding block zone in exposed described the first metal layer, therefore, in the process of subsequent deposition the second metal level, be deposited on metal level on photoresist layer and be deposited between the metal level in press welding block zone and be off-state, can not be connected between the metal level regional with covering argon welding point, therefore, after the dissolving photoresist, the metal that covers on photoresist layer is easier to peel off.
Obviously, those skilled in the art can carry out various changes and modification and not break away from the spirit and scope of the present invention the present invention.Like this, if of the present invention these are revised and within modification belongs to the scope of claim of the present invention and equivalent technologies thereof, the present invention also is intended to comprise these changes and modification interior.
Claims (8)
1. a method that increases the metal layer thickness in chip pressure welding piece zone, is characterized in that, comprising:
Deposit passivation layer on the first metal layer of chip, described the first metal layer cover on the silicon substrate that is provided with the press welding block zone;
Apply photoresist layer on described passivation layer;
Described photoresist layer is exposed and etching, the photoresist that covers the press welding block zone on chip is etched away;
Described passivation layer is carried out isotropic etching, to cover the passivation layer in described press welding block zone and be etched away by the part passivation layer that photoresist layer covers, so that the etched surface of passivation layer is greater than the etched surface of photoresist layer, and the etched surface of passivation layer covers the etched surface of photoresist layer fully; Cover the metal level in described press welding block zone in exposed described the first metal layer;
Described chip is carried out metal deposition, generate the second metal level at described photoresist layer on the metal level in press welding block zone with covering;
Adopt stripper dissolving photoresist layer, to remove photoresist layer and to peel off the metal level that covers in the second metal level on photoresist layer.
2. the method for claim 1, it is characterized in that, the thickness of described the second metal level is lower than the thickness of passivation layer, and the thickness of the thickness of described the first metal layer and described the second metal level and the value, greater than described chip being carried out the routing degree of depth of routing, the described routing degree of depth is for adopting metal wire to carry out metal wire described in the routing process in the degree of depth of the formed groove in described press welding block zone to described chip.
3. method as claimed in claim 2, is characterized in that, described metal wire is copper cash.
4. method as described in claim 1～3 any one, is characterized in that, described the first metal layer and described the second metal level are aluminium lamination, and it is 99.5% aluminium and 0.5% copper that described aluminium lamination comprises proportion.
5. a chip, is characterized in that, comprising:
Be provided with the silicon substrate in press welding block zone;
Cover the first metal layer on described silicon substrate and press welding block zone, cover in described the first metal layer on the metal level in described press welding block zone and be provided with the second metal level, the zone in described the first metal layer except the metal level that covers described press welding block zone is coated with passivation layer.
6. chip as claimed in claim 5, it is characterized in that, the thickness of described the second metal level is lower than the thickness of described passivation layer, and the thickness of the thickness of described the first metal layer and described the second metal level with value greater than the routing degree of depth, the described routing degree of depth is for adopting metal wire to carry out metal wire described in the routing process in the degree of depth of the formed groove in described press welding block zone to described chip.
7. chip as claimed in claim 6, is characterized in that, described metal wire is copper cash.
8. chip as described in claim 5～7 any one, is characterized in that, described the first metal layer and described the second metal level are aluminium lamination, and it is 99.5% aluminium and 0.5% copper that described aluminium lamination comprises proportion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110338607.7A CN103094134B (en) | 2011-10-31 | 2011-10-31 | Method and chip of increasing thickness of metal layer of chip bonding block area |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110338607.7A CN103094134B (en) | 2011-10-31 | 2011-10-31 | Method and chip of increasing thickness of metal layer of chip bonding block area |
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| CN103094134A true CN103094134A (en) | 2013-05-08 |
| CN103094134B CN103094134B (en) | 2015-07-15 |
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| CN201110338607.7A Active CN103094134B (en) | 2011-10-31 | 2011-10-31 | Method and chip of increasing thickness of metal layer of chip bonding block area |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108109925A (en) * | 2017-12-12 | 2018-06-01 | 深圳市晶特智造科技有限公司 | The pressure welding module making method of semiconductor chip |
| CN108133922A (en) * | 2017-12-14 | 2018-06-08 | 深圳市金誉半导体有限公司 | The bonded assemblies production method of semiconductor chip |
| CN113270324A (en) * | 2021-05-13 | 2021-08-17 | 深圳中宝新材科技有限公司 | Metal pressure welding block thick aluminum process for bonding copper wire |
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| JPS60154547A (en) * | 1984-01-24 | 1985-08-14 | Nec Corp | Semiconductor device |
| CN1979837A (en) * | 2005-12-01 | 2007-06-13 | 上海华虹Nec电子有限公司 | Application method of press welding block on top of logic integrated circuit |
| CN201336308Y (en) * | 2009-01-16 | 2009-10-28 | Bcd半导体制造有限公司 | Integrated circuit chip structure |
| CN101740428A (en) * | 2009-12-15 | 2010-06-16 | 无锡中微晶园电子有限公司 | Aluminum thickening process for metal pressure-welding block for bonding copper wire |
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2011
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS60154547A (en) * | 1984-01-24 | 1985-08-14 | Nec Corp | Semiconductor device |
| CN1979837A (en) * | 2005-12-01 | 2007-06-13 | 上海华虹Nec电子有限公司 | Application method of press welding block on top of logic integrated circuit |
| CN201336308Y (en) * | 2009-01-16 | 2009-10-28 | Bcd半导体制造有限公司 | Integrated circuit chip structure |
| CN101740428A (en) * | 2009-12-15 | 2010-06-16 | 无锡中微晶园电子有限公司 | Aluminum thickening process for metal pressure-welding block for bonding copper wire |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108109925A (en) * | 2017-12-12 | 2018-06-01 | 深圳市晶特智造科技有限公司 | The pressure welding module making method of semiconductor chip |
| CN108109925B (en) * | 2017-12-12 | 2020-08-14 | 温州曼昔维服饰有限公司 | Method for manufacturing pressure welding module of semiconductor chip |
| CN108133922A (en) * | 2017-12-14 | 2018-06-08 | 深圳市金誉半导体有限公司 | The bonded assemblies production method of semiconductor chip |
| CN113270324A (en) * | 2021-05-13 | 2021-08-17 | 深圳中宝新材科技有限公司 | Metal pressure welding block thick aluminum process for bonding copper wire |
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| CN103094134B (en) | 2015-07-15 |
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Effective date of registration: 20220719 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District Cheng Fu Road 298, founder building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |
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