TW201513244A - A packaging structure and a method of making the same - Google Patents

Abstract

The invention provides a packaging structure and a method of making the same. The method includes the trenches by etching the wafer along scribe lines, and the trench width is larger than the scribe line, then forming the second pad and connecting line on the trench, then forming the connecting line to connect the wafer and circuit board. The whole thickness of package is more thin, compared with the prior art structure. It is beneficial to the miniaturization of the package.

Description

Chip package structure and forming method

The present invention relates to semiconductor packaging technology, and in particular to a chip package structure and a method of forming the same.

With the continuous development of technology standards, more and more consumer electronic products are becoming more and more compact in size. For example, the current smart phones are increasingly thin and light, to meet the needs of consumers for smart phones. Strong, high-intelligence expectations. As consumer electronics products become more and more miniaturized, there is an increasing demand for electronic chip packaging technology in consumer electronics.

The Chinese Patent Publication No. CN102844769A discloses a sensor package structure. Referring to FIG. 1, a schematic cross-sectional view of the sensor package structure includes: a substrate 10, a sensing wafer 12 on the surface of the substrate 10, and a first a connection pad 11 , a second connection pad 14 on the surface of the sensing chip 12 , the first connection pad 11 and the second connection pad 14 are connected by a wire 15; Encapsulating layer 16 surrounding the wire 15 , the encapsulation layer 16 completely covering the surface of the wire 15 , the surface of the second connection pad 14 and the surface of the first connection pad 11 , and using the package layer 16 to sense the wafer 12 The substrate 10 is fixed.

Since a portion of the encapsulation layer 16 is located on the surface of the sensing wafer 12 such that the total thickness of the sensor package structure is the sum of the thickness of the substrate 10, the thickness of the sensing wafer 12, and the thickness of the encapsulation layer 16 on the surface of the sensing wafer 12, The thickness of the sensor package structure is large, which is not conducive to miniaturization of the product.

The problem solved by the present invention is to provide a chip package structure and a forming method capable of effectively reducing the total thickness of the chip package structure.

In order to solve the above problems, the present invention provides a method for forming a chip package structure, including: providing a wafer to be packaged, the wafer to be packaged includes a plurality of wafers, each of the wafers including a wafer functional region and located outside the functional area of the wafer a plurality of first pads; etching the package wafers along a scribe line direction of the wafer to be packaged to form trenches having a width greater than a width of the scribe lines; trenches on both sides of the scribe lines Forming a second pad on the bottom surface, forming a metal interconnection layer connecting the first pad and the second pad on the surface of the wafer to be packaged, the sidewall and the bottom surface of the trench; in the first pad and the metal Forming a passivation layer on the surface of the interconnect layer, and the passivation layer exposes a surface of the second pad; forming a connection structure on the surface of the second pad; cutting the wafer to be packaged along the scribe line to form a discrete wafer; The connection structure securely connects the discrete wafer to the package circuit board.

Optionally, the connecting structure is a solder ball, a copper pillar or a copper pillar having a gold layer on the top surface.

Optionally, when the connection structure is a copper pillar, the specific technology for forming the copper pillar is: forming a photomask layer having a through hole on the surface of the wafer to be packaged, the through hole exposing the second solder pad; A copper pillar is formed in the via hole by a plating technique; the photomask layer is removed.

Optionally, when the connection structure is a copper pillar having a gold layer on the top surface, a specific technique of forming the copper pillar having the gold layer on the top surface is: forming a mask layer having a through hole on the surface of the wafer to be packaged The through hole exposes a second pad; forming a copper pillar in the through hole by using a plating technique; forming a gold layer on a top surface of the copper pillar by using an electroplating technique or a chemical vapor deposition technique; removing the light Cover layer.

Optionally, the technology for fixedly connecting the discrete wafers to the package circuit board by using the connection structure is a metal bonding technology.

Optionally, when the first pads are located on both sides of the functional area of the wafer, a groove is formed at a corresponding position of each of the wafers having the first pads on the first pads; when the first pads are located on the wafer Around the functional area, a groove is formed at a corresponding position of the dicing street around each of the wafers having the first pad.

Optionally, the height of the connecting structure is smaller than the depth of the trench.

Optionally, the depth of the trench is equal to the sum of the height of the connection structure and the thickness of the package circuit board.

Optionally, the trench has a depth ranging from 50 micrometers to 200 micrometers.

Optionally, the package circuit board is a printed circuit board or a flexible circuit board.

The present invention also provides a wafer package structure comprising: a wafer and a package circuit board; the wafer including a wafer functional region, a plurality of first pads located outside the wafer functional region, and a trench at an edge of the wafer, a second pad of the bottom surface of the trench, the second pad is electrically connected to the first pad through the metal interconnect layer, covering the metal interconnect layer, the first pad and exposing the second pad a passivation layer, a connection structure on the surface of the second pad; through the connection structure, the wafer and the package circuit board are fixedly connected.

Optionally, the connecting structure is a solder ball, a copper pillar or a copper pillar having a gold layer on the top surface.

Optionally, when the first pads are located on both sides of the functional area of the wafer, the trenches are located on both sides of each of the wafers having the first pads; when the first pads are located in the wafer function area The trenches are located on the periphery of each of the wafers having the first pads.

Optionally, the package circuit board is a printed circuit board or a flexible circuit board.

Optionally, the height of the connecting structure is smaller than the depth of the trench.

Optionally, the depth of the trench is equal to the sum of the height of the connection structure and the thickness of the package circuit board.

Optionally, the trench has a depth ranging from 50 micrometers to 200 micrometers.

Compared with the prior art, the technical solution of the present invention has the following advantages: The present invention etches the package wafer along the scribe line direction of the wafer to be packaged to form a trench having a width greater than a width of the scribe line; Forming a second pad and a connection structure on a bottom surface of the groove on both sides of the scribe line; and the connection structure is used to securely connect the wafer and the package circuit board. Since the connection structure is located in the trench at the edge of the wafer, the total thickness of the wafer package structure of the present invention is smaller than the sum of the thickness of the wafer, the height of the connection structure, and the thickness of the package circuit board, thereby facilitating product miniaturization. And because at least part of the scribe line is formed with a groove, the position of the wafer to be packaged at the corresponding position of the dicing street is thinned, and the wafer to be packaged can be smoothly cut with less cutting time, and the package is not easy to be processed. The wafer is damaged. Further, when the depth of the trench is equal to the sum of the height of the connection structure and the thickness of the package circuit board, the total thickness of the chip package structure is only equal to the thickness of the wafer, so that the package size of the wafer can be greatly reduced, and Conducive to the miniaturization of electronic products.

Since the total thickness of the prior art sensor package structure is the sum of the thickness of the substrate, the thickness of the sensing wafer, and the thickness of the encapsulation layer on the surface of the sensing wafer, the total thickness of the sensor package structure is large, which is disadvantageous for the product. Miniaturization, therefore, the present invention provides a chip package structure and a method for forming the same, first forming a trench at the edge of the wafer, and forming a connection structure at the bottom of the trench, by which the wafer and the package circuit board are fixedly connected. Since the connection structure for the fixed connection is located in the trench, the total thickness of the chip package structure of the embodiment of the present invention is smaller than the sum of the thickness of the wafer, the height of the connection structure, and the thickness of the package circuit board, thereby facilitating the product to be small. Chemical.

The above described objects, features, and advantages of the present invention will be more apparent from the aspects of the invention.

The embodiment of the invention provides a method for forming a chip package structure. Please refer to FIG. 2 to FIG. 13 , which are schematic structural diagrams of a method for forming the chip package structure.

Please refer to FIG. 2, FIG. 3 and FIG. 4 together. FIG. 2 is a schematic top view of the entire wafer to be packaged, FIG. 3 is a schematic top view of a portion of the wafer to be packaged, and FIG. 4 is along the line AA' of FIG. A schematic cross-sectional view of a portion of the wafer to be packaged, providing a wafer 100 to be packaged, the wafer 100 to be packaged including a plurality of wafers 110 and a dicing street 120 between the wafers 110, each wafer 110 including a wafer functional region 111 and a plurality of first pads 112 located outside the wafer functional area 111.

The wafer to be packaged 100 includes a plurality of wafers 110 arranged in a matrix and a dicing street 120 between the wafers 110. The wafers to be packaged 100 are cut along the dicing streets 120 when the wafers 100 to be packaged are subsequently sliced. A plurality of discrete wafers.

Each of the wafers 110 of the wafer 100 to be packaged includes a wafer functional region 111 and a plurality of first pads 112 located outside the wafer functional region 111. The wafer functional area 111 is a core circuit or a sensor unit of the wafer, such as a photosensitive unit of an image sensor, a fingerprint sensing unit, and the like. The first pad 112 is electrically connected to the wafer functional region 111 for electrically connecting the wafer functional region 111 to a subsequently packaged package circuit board. In this embodiment, the wafer 110 is a fingerprint sensor wafer, and the wafer function area 111 has a fingerprint sensing unit therein.

In this embodiment, the first pads 112 are located on both sides of the wafer function area 111, and then grooves are formed at corresponding positions of the dicing streets 120 of each of the wafers 110 having the first pads 112 on both sides. In other embodiments, when the first pad is located around the functional area of the wafer, a trench is subsequently formed at a corresponding location of the dicing street around each of the wafers having the first pad.

Please refer to FIG. 5 and FIG. 6. FIG. 5 is a schematic top view of a portion of the wafer to be packaged, and FIG. 6 is a cross-sectional structural view of a portion of the wafer to be packaged along the line AA' of FIG. The dicing street 120 of the wafer 100 etches the package wafer 110 in a direction to form a trench 130 having a width greater than the width of the scribe line 120.

In this embodiment, the forming of the trench 130 includes forming a first photoresist layer (not shown) on the surface of the wafer 100 to be packaged, and exposing and developing the first photoresist layer to form a patterned first photoresist layer, wherein the patterned first photoresist layer corresponds to a position of a subsequently formed trench; and the patterned first photoresist layer is a photomask for the crystal to be packaged The surface of the circle 100 is etched to form trenches 130.

The position of the groove 130 corresponds to the position of the dicing street 120, the length direction of the groove 130 is parallel to the direction of the corresponding dicing street 120, and the width direction of the groove 130 is parallel to the direction of the corresponding dicing street 120. In the present embodiment, the first pads 112 are located on both sides of the wafer function region 111, so that the trenches 130 are formed at corresponding positions of the dicing streets 120 of each of the wafers 110 having the first pads 112 on both sides. In other embodiments, when the first pad is located around the functional area of the wafer, a trench is formed at a corresponding location of the dicing street around each of the wafers having the first pad.

In this embodiment, the length of the groove 130 corresponding to each wafer 110 is equal to the length of the side of the wafer 110, that is, the position corresponding to all lateral or all longitudinal dicing streets 120 when etching the surface of the wafer 100 to be packaged. The grooves 130 are all formed by cutting. In other embodiments, referring to FIG. 7 , the length of the corresponding trench 130 of each of the wafers 110 may also be smaller than the length of the sides of the wafer 110 .

In this embodiment, the centerline position of the trench 130 overlaps with the centerline position of the dicing street 120, and since the width of the trench 130 is greater than the width of the dicing street 120, the trenches on both sides of the dicing street 120 The bottom of the 130 is subsequently used to form a second pad and a connection structure. In other embodiments, the centerline position of the groove is slightly offset from the centerline position of the cutting lane, but the cutting lane is completely located in the area of the groove, and the bottom of the groove on both sides of the cutting lane is subsequently used. Forming a second pad and a connection structure.

In this embodiment, the depth of the trench 130 ranges from 50 micrometers to 200 micrometers. In other embodiments, the depth and width of the grooves may also be other suitable values.

Please refer to FIG. 8 and FIG. 9. FIG. 8 is a schematic top view of a portion of the wafer to be packaged, and FIG. 9 is a cross-sectional structural view of a portion of the wafer to be packaged along the line AA' of FIG. A second pad 113 is formed on the bottom surface of the trench 130 on both sides of the track 120, and a metal connecting the first pad 112 and the second pad 113 is formed on the surface of the wafer 100 to be packaged, the sidewall and the bottom surface of the trench 130. Interconnect layer 114.

In this embodiment, a specific technique for forming the second pad 113 and the metal interconnection layer 114 includes: forming a surface of the wafer 100 to be packaged, a sidewall and a bottom surface of the trench 130 by using a physical vapor deposition technique. a metal interconnect film (not shown) for etching the metal interconnect film to form a second pad 113 on a bottom surface of the trench 130 on both sides of the scribe line 120 and connecting the first pad 112 and The metal interconnect layer 114 of the second pad 113. The second pads 113 are in one-to-one correspondence with the first pads 112. The material of the second pad 113 and the metal interconnection layer 114 is aluminum, aluminum copper alloy or the like.

In other embodiments, the second pad and metal interconnect layer can also be formed using electroplating techniques. In other embodiments, the second pad and metal interconnect layer can also be formed separately using different techniques.

Referring to FIG. 10, a passivation layer 115 is formed on the surface of the first pad 112 and the metal interconnection layer 114, and the passivation layer 115 exposes the surface of the second pad 113.

The passivation layer 115 is used to isolate the first pad 112 and the metal interconnect layer 114 from the outside, so as to prevent external moisture and impurities from affecting the electrical properties of the first pad 112 and the metal interconnect layer 114. The material of the passivation layer 115 is ruthenium oxide, ruthenium nitride, ruthenium oxynitride, ruthenium oxynitride or a resin. In this embodiment, the material of the passivation layer 115 is yttrium oxide, and the specific technology for forming the passivation layer 115 is: on the surface of the wafer 100 to be packaged, the first pad 112, the second pad 113, and A surface of the metal interconnection layer 114 is formed with a passivation film, and the passivation film at the corresponding position of the second pad 113 and the wafer functional region 111 is etched until the second pad 113 and the wafer functional region 111 are exposed to form a cover. The first pad 112 and the surface of the metal interconnect layer 114 are exposed and the passivation layer 115 on the surface of the second pad 113 is exposed. The exposed surface of the second pad 113 is subsequently used to form a connection structure.

In the present embodiment, since the wafer 110 is a fingerprint sensor wafer, the passivation film on the surface of the wafer functional region 111 is etched away. In other embodiments, the passivation film on the surface of the wafer functional region may not be removed, and only the passivation layer on the surface of the second pad may be removed.

Referring to FIG. 11, a connection structure 135 is formed on the surface of the second pad 113.

The connection structure 135 is used to subsequently securely connect the wafer to the package circuit board. The connecting structure 135 is a solder ball, a copper pillar or a copper pillar having a gold layer on the top surface.

In this embodiment, the connection structure 135 is a copper pillar, and the technology for forming the copper pillar includes: forming a photomask layer (not shown) having a through hole on the surface of the wafer 100 to be packaged, the through Forming a surface of the second pad 113 at the bottom of the hole; forming a copper pillar in the through hole by using a plating technique, the height of the copper pillar being smaller than a height of the through hole and smaller than a depth of the trench; The mask layer is described. In this embodiment, the photomask layer is a photoresist layer. In other embodiments, the photomask layer may also be other hard mask layers, such as a hafnium oxide layer, a tantalum nitride layer, a resin layer, or the like. Since the connection structure 135 for the fixed connection is located in the trench 130, the total thickness of the wafer package structure of the embodiment of the present invention is smaller than the sum of the thickness of the wafer, the height of the connection structure, and the thickness of the package circuit board, thereby facilitating Product miniaturization. And since the height of the copper pillar is smaller than the depth of the trench, when the connection structure 135 is used to fix the wafer to the package circuit board, the total thickness of the finally formed wafer package structure is less than the thickness of the wafer and the package circuit board. The sum of the thicknesses further facilitates miniaturization of the resulting electronic device.

In other embodiments, the connection structure may further be a copper pillar having a gold layer on the top surface, and the forming technique includes: forming a photomask layer having a through hole on the surface of the wafer to be packaged, the bottom of the via hole being exposed a surface of the second pad; forming a copper pillar in the through hole by using a plating technique, the height of the copper pillar being smaller than the height of the through hole and smaller than the depth of the trench; using electroplating technology or chemical gas phase The deposition technique forms a gold layer on the top surface of the copper pillar; the photomask layer is removed. Since the on-resistance of the gold layer is smaller, it is advantageous to improve the on-current, and the ductility is better, and it is easier to use a metal bonding method to bond with the corresponding pads of the package circuit board to fix the connection.

When the connection structure 135 is a copper pillar or a copper pillar having a gold layer on the top surface, the copper pillar or the copper pillar having a gold layer on the top surface is formed first, and then the wafer to be packaged is cut to form a discrete wafer. .

In other embodiments, when the connection structure is a solder ball, the wafer to be packaged is first cut to form a discrete wafer, and then a solder ball is formed on the exposed surface of the second pad, and the solder ball is used. The discrete wafers are fixedly coupled to the package circuit board.

Referring to FIG. 12, the packaged wafer 100 is cut along the dicing street 120 (please refer to FIG. 11) to form a discrete wafer 110.

The technique for slicing the packaged wafer 100 is slicing or laser cutting, in which the laser is used to cut the packaged wafer 100 because the laser cutting has a smaller slit width. The cutting technique cuts the packaged wafer 100 along the scribe line 120, and since at least a portion of the scribe line is formed with a groove at a corresponding position, the position of the wafer 100 to be packaged at a corresponding position is thinned, using less cutting time. The wafer 100 to be packaged can be smoothly cut, and damage to the package wafer 100 is not easily caused.

Referring to FIG. 13, the discrete wafer 110 is fixedly coupled to the package circuit board 140 by the connection structure 135.

The package circuit board 140 is a printed circuit board (PCB) or a flexible circuit board (FPC), and the package circuit board 140 has a pad (not shown) and a metal wire (not shown), and the connection structure 135 and The pads of the package circuit board 140 are connected such that the discrete wafers 110 are fixedly coupled to the package circuit board 140. The thickness of the package circuit board 140 may be less than, equal to, or greater than the depth of the trench. In this embodiment, the sum of the thickness of the package circuit board 140 and the height of the connection structure 135 is equal to the depth of the trench, so that the total thickness of the chip package structure is only equal to the thickness of the wafer, so that the package of the wafer can be greatly reduced. The size is conducive to the miniaturization of electronic products.

In this embodiment, the connection structure 135 is a copper pillar, and the copper pillars are connected and bonded to the pads of the package circuit board 140 through a metal bonding technique, so that the discrete wafers 110 are fixed to the package circuit board 140. connection. The metal bonding technique is one of eutectic bonding, metal diffusion bonding, anodic bonding, and bonding bonding.

In other embodiments, the connection structure is a copper pillar having a gold layer on the top surface, and the copper pillar having the gold layer on the top surface is bonded to the pad of the package circuit board through a metal bonding technique, so that The discrete wafers are fixedly connected to the package circuit board. The metal bonding technique is one of eutectic bonding, metal diffusion bonding, anodic bonding, and bonding bonding.

In other embodiments, when the connection structure is a solder ball, after the wafer to be packaged is cut to form a discrete wafer, a solder ball is formed on the surface of the second pad exposed by the wafer, and is soldered. The solder balls are soldered to the pads of the package circuit board such that the discrete wafers are fixedly coupled to the package circuit board.

The embodiment of the present invention further provides a chip package structure. Referring to FIG. 13 , a schematic cross-sectional view of the chip package structure includes: a wafer 110 and a package circuit board 140 . The wafer 110 includes a wafer function. a region 111, a plurality of first pads 112 located outside the wafer functional region 111, and a trench at the edge of the wafer 110, a second pad 113 on the bottom surface of the trench, the second pad 113 and the first A solder pad 112 is electrically connected through the metal interconnect layer 114, covering the metal interconnect layer 114, the first pad 112, and exposing the passivation layer 115 of the second pad 113. The second pad 114 is located on the second pad 114. The surface connection structure 135; the wafer 110 and the package circuit board 140 are fixedly connected through the connection structure 135.

The connecting structure 135 is a solder ball, a copper pillar or a copper pillar having a gold layer on the top surface. The height of the connection structure 135 is greater than, less than, or equal to the depth of the trench. In this embodiment, the connection structure 135 is smaller than the depth of the trench, and the depth of the trench is equal to the sum of the height of the connection structure and the thickness of the package circuit board, thereby effectively reducing the chip package structure. The thickness is conducive to the miniaturization of electronic products.

In the present embodiment, when the first pads 112 are located on both sides of the wafer functional region 111, the trenches are located on both sides of each of the wafers 110 having the first pads 112. In other embodiments, the trench is located on a peripheral edge of each wafer having a first pad when the first pad is positioned around the functional area of the wafer.

In this embodiment, the depth of the trench ranges from 50 micrometers to 200 micrometers. In other embodiments, the depth of the trenches may also be other suitable values.

Although the present invention has been disclosed above, the present invention is not limited thereto. Any changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be determined by the scope of the claims.

10‧‧‧Base
11‧‧‧First connection pad
12‧‧‧Induction chip
14‧‧‧Second connection pad
15‧‧‧Wire
16‧‧‧Encapsulation layer
100‧‧‧ wafer
110‧‧‧ wafer
111‧‧‧ Chip Functional Area
112‧‧‧First pad
113‧‧‧Second pad
114‧‧‧Metal interconnect layer
115‧‧‧ Passivation layer
120‧‧‧ cutting road
130‧‧‧ trench
135‧‧‧ Connection structure
140‧‧‧Package board

1 is a schematic cross-sectional structural view of a sensor package structure of the prior art; and FIGS. 2 to 13 are structural schematic views of a process of forming a chip package structure according to an embodiment of the present invention.

110‧‧‧ wafer

111‧‧‧ Chip Functional Area

112‧‧‧First pad

113‧‧‧Second pad

114‧‧‧Metal interconnect layer

115‧‧‧ Passivation layer

135‧‧‧ Connection structure

140‧‧‧Package board

Claims (17)

A method for forming a chip package structure, comprising: providing a wafer to be packaged, the wafer to be packaged comprising a plurality of wafers, each of the wafers comprising a wafer functional region and a plurality of first pads located outside the functional area of the wafer; The scribe line to be packaged wafer is etched to form a trench, the trench has a width greater than a width of the scribe line; and a second pad is formed on a bottom surface of the trench on both sides of the scribe line, Forming a metal interconnection layer connecting the first pad and the second pad on the surface of the wafer to be packaged, the sidewall and the bottom surface of the trench; forming a passivation layer on the surface of the first pad and the metal interconnection layer, And the passivation layer exposes a second pad surface; forming a connection structure on the surface of the second pad; cutting the wafer to be packaged along the scribe line to form a discrete wafer; using the connection structure to separate the discrete The wafer is fixedly connected to the package circuit board. The method of forming a wafer package structure according to claim 1, wherein the connection structure is a solder ball, a copper pillar, or a copper pillar having a gold layer on a top surface. The method for forming a chip package structure according to claim 2, when the connection structure is a copper pillar, the specific technology for forming the copper pillar is: forming a photomask layer having a through hole on the surface of the wafer to be packaged The via hole exposes the second pad; a copper pillar is formed in the via hole by using a plating technique; and the photomask layer is removed. The method for forming a chip package structure according to claim 2, wherein when the connection structure is a copper pillar having a gold layer on the top surface, a specific technique of forming the copper pillar having the gold layer on the top surface is: in the crystal to be packaged Forming a photomask layer having a via hole, the via hole exposing a second pad; forming a copper pillar in the via hole by electroplating; using a plating technique or a chemical vapor deposition technique on the copper pillar The top surface forms a gold layer; the photomask layer is removed. The method of forming a chip package structure according to claim 2 or 4, wherein the connection structure is used to securely connect the discrete wafers to the package circuit board by a metal bonding technique. The method for forming a chip package structure according to claim 1, wherein when the first pads are located on both sides of the function area of the wafer, grooves are formed at corresponding positions of the dicing streets on both sides of the first pad with each of the pads. When the first pad is located around the functional area of the wafer, a groove is formed at a corresponding position of the dicing street around each of the wafers having the first pad. The method of forming a chip package structure according to claim 1, wherein the height of the connection structure is smaller than a depth of the trench. The method of forming a chip package structure according to claim 1, wherein the depth of the trench is equal to a sum of a height of the connection structure and a thickness of the package circuit board. The method of forming a chip package structure according to claim 1, wherein the trench has a depth ranging from 50 micrometers to 200 micrometers. The method of forming a chip package structure according to claim 1, wherein the package circuit board is a printed circuit board or a flexible circuit board. A chip package structure comprising: a wafer and a package circuit board; the wafer comprising: a wafer functional region; a plurality of first pads located outside the wafer functional region; and a trench at an edge of the wafer; a second solder pad, the second pad is electrically connected to the first pad through the metal interconnect layer; covering the metal interconnect layer, the first pad and exposing the passivation layer of the second pad; a connection structure on the surface of the second pad; the wafer and the package circuit board are fixedly connected through the connection structure. The wafer package structure according to claim 11, wherein the connection structure is a solder ball, a copper pillar or a copper pillar having a gold layer on the top surface. The wafer package structure of claim 11, wherein when the first pads are located on both sides of the functional area of the wafer, the grooves are located on both sides of each of the wafers having the first pads; When a pad is located around the functional area of the wafer, the trench is located on the peripheral edge of each of the wafers having the first pad. The chip package structure of claim 11, wherein the package circuit board is a printed circuit board or a flexible circuit board. The wafer package structure of claim 11, wherein the height of the connection structure is smaller than the depth of the trench. The wafer package structure of claim 11, wherein the depth of the trench is equal to a sum of a height of the connection structure and a thickness of the package circuit board. The wafer package structure of claim 11, wherein the trench has a depth ranging from 50 micrometers to 200 micrometers.